EDA技术使用教程

ENTITY mux21a ISPORT(a,b,s:IN BIT;y:OUT BIT);END ENTITY mux21a; ARCHITECTURE bhv OF mux21a IS BEGINPROCESS (a,b,s) BEGINIF(s=‟1‟) THEN y<=a;ELSE y<=b;END IF; END PROCESS;END ARCHITECTURE bhv;例3-2LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL; ENTITY h_adder ISPORT(A:IN STD_LOGIC;B:IN STD_LOGIC;SO:OUT STD_LOGIC;CO:OUT STD_LOGIC;);END ENTITY h_adder ISSO<= A XOR B;CO<=A AND B;END ARCHITECTURE fh1;例3-3LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY MUX41A ISPORT (a,b,c,d,s0,s1:IN STD_LOGIC; y:OUT STD_LOGIC); END ENTITY MUX41A;ARCHITECTURE BHV OF MUX41A isSIGNAL S:STD_LOGIC_VECTOR(1 DOWNTO 0);BEGINS<=s1&s0;PROCESS(s1,s0)BEGINCASE (S) ISWHEN “00”=>y<=a;WHEN”01”=>y<=b;WHEN”10”=>y<=c;WHEN”11”=>y<=d;WHEN OTHERS=>NULL;END CASE;END PROCESS;END BHV;例3-4sel:IN INTEGER RANGE 0 TO 15;...CASE sel ISWHEN 0 =>z1<=”010”;WHEN 1|3 =>z2<=”110”;WHEN 4 TO 7|2 =>z3<=”011”;WHEN OTHERS =>z4<=“111”;END CASE;例3-5SIGNAL value:INTEGER RANGE 0 TO 15; SIGNAL OUT1:STD_LOGIC;...CASE value ISWHEN 0>=out1<=‟1‟;WHEN 1>=out1<=‟0‟;END CASE...CASE value ISWHEN 0 TO 10=>out1<=‟1‟;WHEN 5 TO 15 =>out1<=‟0‟; END CASE;例3-6S<=s1&s0;PROCESS(s1,s0) BEGINIF (S=”00”) THEN y<=a; ELSIF(S=”01”)THEN y<=b; ELSIF(S=”10”) THEN y<=c; ELSE y<=d; END IF;END PROCESS;END BHV;例3-7S<=s1&s0;Y<=a WHEN S=”00” ELSEb WHEN S=”01” ELSEc WHEN S=”10” ELSEd ;END BHV例3-8S<=s1 &s0;WITH S SELECTY<=a WHEN”00”,b WHEN”01”,c WHEN”10:,d WHEN”11”;END BHV;例3-9LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALLENTITY f_adder ISPORT (ain,bin,cin : IN STD_LOGIC;Cout,sum : OUT STD_LOGIC );END ENTITY f_adder;ARCHITECTURE fdl OF f_adder ISCOMPONENT h_adderPORT (A, B : IN STD_LOGIC; CO, SO : OUT STD_LOGIC);END COMPONENT;COMPONENT or2aPORT (a, b : IN STD_LOGIC; C : OUT STD_LOGIC);END COMPONENT;SIGNAL net1,net2,net3 : STD_LOGIC;BEGINu1 : h_adder PORT MAP(A=ain,B=>bin,CO=>net2,SO=>net1);u2 : h_adder PORT MAP(net1, cin, net3 sum);u3 : or2a PORT MAP(a=>net2, b=>net3, c=>cout); END ARCHITECTURE fdl;例3-10LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL；ENTITY or2a ISPORT (a, b : IN STD_LOGIC; C : OUT STD_LOGIC); END ENTITY or2a;ARCHITECTURE one OF or2a ISBEGINC<= a OR b;END ARCHITECTURE one;例3-11LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL；USE IEEE.STD_LOGIC_UNSIGNED.ALL；ENTITY ADDER8B ISPORT (A, B : IN STD_LOGIC_VECTOR(7 DOWNTO 0);CIN : IN STD_LOGIC; COUT : OUTSTD_LOGIC;DOUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) );END ENTITY ADDER8B ;ARCHITECTURE BHV OF ADDER8B ISSIGNAL DATA : STD_LOGIC_VECTOR(8 DOWNTO 0) ; BEGINDATA <= (…0‟ & A) + (…0‟ & B) + (“0 0 0 0 0 0 0 0” & CIN); COUT <= DATA(8) ; DOUT <= DATA(7 DOWNTO 0) ;END ARCHITECTURE BHV;例3-12LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL；USE IEEE.STD_LOGIC_UNSIGNED.ALL；ENTITY CNTC ISPORT (DIN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);CNTH : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ); END CNTC;ARCHITECTURE BHV OF CNTC ISBEGINProcess(DIN)V ARIABLE Q : STD_LOGIC_VECTOR (3 DOWNTO 0);beginQ := ”0 0 0 0”;FOR n in 0 to 7 LOOPIF (DIN(n) = …1‟ ) THEN Q:=Q+1; END IF;END LOOP;CNTH<=Q;end process;END BHV;例3-13LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL；USE IEEE.STD_LOGIC_UNSIGNED.ALL；USE IEEE.STD_LOGIC_ARITH.ALL；ENTITY MULT4B ISGENERIC ( S : INTEGER := 4);PORT ( R : OUT STD_LOGIC_VECTOR(2*S DOWNTO 1);A, B : IN STD_LOGIC_VECTOR (S DOWNTO 1);END ENTITY MULT4B;ARCHITECTURE ONE OF MULT4B ISSIGNAL A0 :STD_LOGIC_VECTOR(2*S DOWNTO 1);BEGINA0 <= CONV_STD_LOGIC_VECTOR(0,S) & A; PROCESS (A, B)V ARIABLE R2 : STD_LOGIC_VECTOR(2*S DOWNTO 1);BEGINR1 := (others => …0‟);FOR i IN 1 TO S LOOPIF (B(i) = …1‟) THENR1 := R1 + TO_STDLOGICVECTOR(TO_BITVECTOR(A0) SLL (i-1));END IF;R <= R1;END PROCESS;END ARCHITECTURE ONE;例3-14LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL；USE IEEE.STD_LOGIC_UNSIGNED.ALL；ENTITY decoder3to8 ISPort(DIN :IN STD_LOGIC_VECTOR(2 DOWNTO 0));END decoder3to8;ARCHITECTURE behave OF decoder3to8 ISBEGINDOUT<=”00000001”SLL CONV_INTEGER(DIN);END behave;例3-25LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY MULT8B ISPORT(D1,D2 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);Q : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ); END ;ARCHITECTURE BHV OF MULT8B ISCOMPONENT MULT4BGENERIC ( S : integer );PORT ( R : OUT std_logic_vector(2*S DOWNTO 1);A ,B : IN std_logic_vector(S DOWNTO 1) ); END COMPONENT ;BEGINu1 : MULT4B GENERIC MAP (S=>8)PORT MAP (R =>Q , A=> D1, B=>D2);END;例3-24LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL; PACKAGE n_pack ISSUBTYPE nat IS Integer range 0 to 255;TYPE Bit8 IS array (7 downto 0) OF std_logic; FUNCTION nat_to_Bit8 ( s : nat) RETURN Bit8; END n_pack;PACKAGE BODY n_pack ISFUNCTION nat_to_Bit8 (s: nat) RETURN Bit8 IS V ARIABLE Din: Integer range 255 downto 0;V ARIABLE Rut: Bit8;V ARIABLE Rig:Integer :=2**7;BEGINDin := s;FOR I in 7 downto 0 LOOPIF Din/Rig > 0 THEN Rut(i) :='1';Din := Din-Rig; ELSE Rut (i):= '0'; END IF;Rig := Rig / 2;END LOOP;RETURN Rut;END nat_to_Bit8;END n_pack;例3-23LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE WORK.n_pack.ALL ;ENTITY axamp ISPORT(dat : IN nat ;ou : OUT Bit8);END ;ARCHITECTURE bhv OF axamp ISBEGINou <= nat_to_Bit8(dat);END ;例3-22FUNCTION To_bit ( s : std_ulogic; xmap : BIT:='0' )RETURN BIT ; FUNCTION To_bitvector ( s : std_logic_vector;xmap : BIT := '0' )RETURN BIT_VECTOR ;FUNCTION To_bitvector ( s : std_ulogic_vector;xmap : BIT := '0' )RETURN BIT_VECTOR ;FUNCTION To_bitvector ( s : std_logic_vector;xmap : BIT := '0' )RETURN BIT_VECTOR IS; ALIAS sv : std_logic_vector(s'LENGTH-1 DOWNTO 0 )IS s ;V ARIABLE result : BIT_VECTOR(s'LENGTH-1 DOWNTO 0); BEGINFOR i IN result'RANGE LOOPCASE sv(i)ISWHEN '0'|'L' => result(i):= '0';WHEN '0'|'H' => result(i):= '1';WHEN OTHERS => result(i):= xmap;END CASE ;END LOOP ;RETURN result ;END ;例3-21LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY decoder3to8 ISPORT ( input : IN STD_LOGIC_VECTOR (2 DOWNTO 0);Output : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)); END decoder3to8;ARCHITECTURE behave OF decoder3to8 ISBEGINPROCESS (input) BEGINoutput<=(OTHERS =>'0') ; output(CONV_INTEGER(input))<='1'; END PROCESS;END behave;例3-20LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY amp ISPORT ( a1, a2 : IN BIT_VECTOR(3 DOWNTO 0);c1, c2, c3 : IN STD_LOGIC_VECTOR (3 DOWNTO 0);b1, b2, b3 :INTEGER RANGE 0 TO 15;d1,d2,d3,d4 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ); END amp;d1 <= TO_STDLOGICVECTOR(a1 AND a2);d2 <= CONV_STD_LOGIC_VECTOR(b1,4) WHEN CONV_INTEGER(b2)=9else CONV_STD_LOGIC_VECTOR(b3,4);d3 <= c1 WHEN CONV_INTEGER(c2)= 8 ELSE c3; d4 <= c1 WHEN c2 = else c3;例3-18LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;ENTITY COMP ISPORT ( C , D : IN SIGNED(3 DOWNTO 0);RA : OUT SIGNED(3 DOWNTO 0);RM : OUT SIGNED(7 DOWNTO 0);R : OUT BOOLEAN );END ENTITY COMP;ARCHITECTURE ONE OF COMP ISBEGINR<= (C>D); RA <=C+D; RM<= C*D;END ARCHITECTURE ONE;例3-17LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;ENTITY COMP ISPORT ( C , D : IN UNSIGNED(3 DOWNTO 0);RA : OUT UNSIGNED(3 DOWNTO 0);RM : OUT UNSIGNED(7 DOWNTO 0);R : OUT BOOLEAN );END ENTITY COMP;ARCHITECTURE ONE OF COMP ISBEGINR<= (C>D); RA <=C+D; RM<= C*D;END ARCHITECTURE ONE;例3-16LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_SIGNED.ALL;ENTITY COMP ISPORT ( C , D : IN STD_LOGIC_VECTOR(3 DOWNTO 0);RA : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);RM : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);R : OUT BOOLEAN );END ENTITY COMP;ARCHITECTURE ONE OF COMP ISBEGINR<= (C>D); RA <=C+D; RM<= C*D;END ARCHITECTURE ONE;例3-15LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY COMP ISPORT ( C , D : IN STD_LOGIC_VECTOR(3 DOWNTO 0);RA : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);RM : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);R : OUT BOOLEAN );END ENTITY COMP;ARCHITECTURE ONE OF COMP ISBEGINR<= (C>D); RA <=C+D; RM<= C*D;END ARCHITECTURE ONE;。