清华PLL讲义

Æ Simply speaking, we will learn where to, when to, and how to use PLL for various applications.
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W. Rhee, Institute of Microelectronics, Tsinghua University
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W. Rhee, Institute of Microelectronics, Tsinghua University
I. Overview of Clocking and Frequency Generation
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W. Rhee, Institute of Microelectronics, Tsinghua University
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W. Rhee, Institute of Microelectronics, Tsinghua University
Course Assessment
• Homework: • Midterm exam: • Final exam: • Term project:
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PLL DESIGN AND CLOCK/FREQUENCY GENERATION (Lecture 1)
Woogeun Rhee Institute of Microelectronics Tsinghua University
PLL Design and Clock/Frequency Generation (PLL设计与时钟/频率产生)
Course Outline – First Half
I. Overview of Clocking and Frequency Generation 1. Course introduction 2. Phase-locked clocking in modern communication systems II. Phase-Lock Basics 1. PLL linear model 2. Loop components 3. Loop dynamics 4. Transient response and acquisition 5. PLL behavioral simulations III. PLL Design 1. System design perspectives - spur and modulation - phase noise/jitter - settling time - bandwidth optimization 2. Circuit design aspects - phase detector - charge pump - frequency divider - voltage-controlled oscillator 3. Delay-locked loop (Midterm Examination)
• Course #: 80260042 • Time: Tuesday, 7:20pm – 8:55pm (spring’07) • Place: 六教6B206 • TA: 孙远峰 • Office hour: Thursday 2-4pm (10-11am for those who have time conflict) • Prerequisite: Basic analog/digital circuit design
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W. Rhee, Institute of Microelectronics, Tsinghua University
Textbook & References
• Main Textbook
R. E. Best, Phase-Locked Loops, 5th ed., McGraw-Hill, New York, 2003
W. Rhee, Institute of Microelectronics, Tsinghua University
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Course Outline – Second Half
IV. Applications 1. Frequency synthesizers for RF applications - system design consideration; phase noise, spur, and settling time - integer-N/fractional-N frequency synthesizers - direct digital frequency synthesizer 2. Clock-and-data recovery for serial link and optical communications - system design considerations; jitter transfer, jitter tolerance, and jitter generation - circuit design aspects in multi-Gb/s SerDes systems - DLL-based CDR for serial-link backplane applications - D/PLL-based CDR for SONET applications 3. Clock multiplier unit for digital clock generation - system design considerations; RJ, DJ, long-term jitter, and short-term jitter - circuit design for high supply rejection - examples; PLL design for FB-DRAM, multiplying DLL (MDLL) for low jitter accumulation 4. PLL for “design on demand” V. Advanced Topics 1. Recent PLL works and trends 2. Coupling effects on PLL performance 3. Various in-situ calibration/compensation methods for technology-friendly PLL 4. Future challenges VI. Project Discussion (Final Examination)
• References:
Theory and System Analysis W. Egan, Phase-Lock Basics, Wiley, New York, 1998 F. M. Gardner, Phaselock Techniques, 3rd ed., Wiley, New Jersey, 2005 D. H. Wolaver, Phase-Locked Loop Circuit Design, Prentice Hall, New Jersey, 1991 U. Rhode, Microwave and Wireless Synthesizers, Wiley, New York, 1997 W. Egan, Frequency Synthesis by Phase Lock, Wiley, New York, 2000 J. Smith, Modern Communication Circuits, McGraw Hill, New York, 1986 Architectures and Circuit Design B. Razavi, RF Microelectronics, Prentice Hall, New Jersey, 1998 T. Lee, The Design of CMOS Radio-Frequency Integrated Circuits, Cambridge, UK, 1997 Collection of Selected Papers B. Razavi, Monolithic Phase-Locked Loops and Clock Recovery Circuits, IEEE Press, New York, 1996 B. Razavi, Phase-Locking in High-Performance Systems, IEEE Press, New York, and Wiley, New Jersey, 2003
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W. Rhee, Institute of Microelectronics, Tsinghua University
Lecture & Workshop by Prof. Perrott (MIT)
• Invited Lecture (will replace our PLL lecture, Apr. 17) - Fractional-N synthesizer and simulation • Workshop (Apr. 18 – 19) - PLL behavioral simulation tutorial - Lab exercise
What Is Phase-Locked Loop?
θin
PD
ቤተ መጻሕፍቲ ባይዱLPF
VCO
θout
• A circuit that synchronizes the signal from an oscillator with a second input signal (reference) so that they operate at the same frequency (Egan/Best). • A feedback system in which the feedback signal is used to lock the output frequency and phase to the frequency and phase of an input signal (Smith). • Basically an oscillator whose frequency is locked onto some frequency component of an input signal, which is done with a feedback control loop (Wolaver).
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W. Rhee, Institute of Microelectronics, Tsinghua University
Course Objective
• This course gives insights into phase-locked clocking as well as the ability of gaining system perspectives and circuit design aspects of phase-locked loop (PLL) for various applications. In the first half of this course, basic theoretical analysis of the PLL and system/circuit design considerations will be discussed. The second half of the course consists of extensive lectures covering practical design aspects in various PLL applications. Some advanced topics such as coupling, testability, and on-chip compensation will be also useful for those who are interested in system-on-chip (SoC) design and advanced mixed-signal IC design. From this course, the students expect to learn followings; - role of clock generation/synchronization in modern communication systems - basic concept and theoretical analysis of PLL - system design perspectives and architectures - practical circuit design aspects - advanced topics; coupling, testability, on-chip compensation, …