逆变器控制

Design and Control for LCL-Based Inverters with Both Grid-Tie and Standalone Parallel Operations Chien-Liang Chen, Jih-Sheng Lai, Yu-Bin Wang, Sung-Yeul Park, and Hide MiwaVirginia Polytechnic Institute and State UniversityFuture Energy Electronics Center415 Whittemore Hall, Blacksburg, VA 24061-0111, USAjlchen99@, laijs@, ybwang@, supark@, and hmiwa1@Abstract—The inductor-capacitor-inductor (LCL) filter allows higher noise attenuation and universal output in which a power conditioning system or an inverter can operate in both grid-tie and standalone modes. In this paper, the LCL filter design considerations including sensor position selection and component selections are discussed for single-phase paralleled inverters operating in both grid-tie and standalone modes. For grid-tie mode operation, each inverter is operating under a single current loop with proportional-resonant controller and admittance path compensation to reduce the steady-state error by providing a high gain at the fundamental frequency. For standalone mode operation, one of the inverters is implemented with a dual-loop controller to regulate the output voltage while the rest inverters operate in single current-loop controller with communication channels in between to ensure the uniformity of current sharing. Both the simulation and experimental results verify that the designed controllers are capable of paralleling inverter operation in grid-tie and standalone modes by adapting to different controller settings while keeping the same hardware setup.Keywords-LCL filter, grid-tie inverter, dual-loop control, PR controller, parallel inverter, admittance compensation.I.I NTRODUCTIONThe parallel inverter systems have demonstrated many advantages compared to a single high-power inverter [1-8]. For example, an inverter can be designed in modular manner which allows the system capacity to be multiplied and the reliability can be greatly improved with redundancy. Parallel inverter operation has been a major topic in uninterruptible power system (UPS) applications where the design is focused on the standalone operation, and the output stage is typically an inductor-capacitor (LC) filter. When connecting the paralleled inverters to utility grids, the capacitor becomes redundant, and thus either a pure inductor (L) or an LCL filter can be used as the inverter output stage. Compared with the L filter, the LCL filter is more attractive [9] because it can not only provide higher high-frequency harmonics attenuation with the same inductance value, but also allow the inverter to operate in both standalone and grid-tie modes, which makes it a universal inverter for distributed generation applications such as fuel cell and photovoltaic power conditioning system (PCS).Major factors that were used in LCL design considerations include inductor current ripple magnitude and reactive power consumption in capacitor [10], the range of LCL resonant frequency, and the total inductance value of LCL filter [11]. In this paper, the sensor position selection and the universal application in both grid-tie and standalone modes are added as the LCL design factors.The compliance of interconnect standards IEEE 1547 and 1547.1 [12,13] and their current harmonic limits can also be used in the LCL design criteria. However, the cause of inverter harmonic distortions were mainly found in nonlinear effects such as nonlinear device voltage drop, dead time, limited PWM resolution and lack of stiffness in dc link [14]. The controller with high gain at the harmonic frequencies such as proportional-resonant (PR) controller [15] and direct-quadrant (DQ) frame current controller [16,17] can be potential candidates to alleviate such harmonic distortions.In addition to harmonic concerns, the controller design for parallel inverter systems must consider stability and steady-state error issues. In general, parallel inverters are designed in standalone mode for UPS and distributed generation (DG) systems that supply regulated output voltages when grid is not available. Most reported standalone inverter systems use a LC filter and proportional-integral (PI) controller in their control loops [18-20]. In [18,19], multiple feedback loops were proposed to improve the output voltage performance and to damp the poles of LC filter. In [20], feedback, feed-forward, and nonlinear controls were considered for the entire UPS control system. These parallel inverter systems, however, are usually designed with LC filter [1-8] which will have difficulties in grid-tie operations due to the undetermined resonant frequency caused by the change of grid-side source impedance [21]. The design of parallel inverters also needs to consider the current sharing capability [5-6] and the communication [7-8] among paralleled inverters. In [5], some current-sharing schemes for parallel inverter systems including master-salve control, current-limit control, and circular-chain control are examined and compared. In [6], a current-weight-distribution control was proposed to allow inverters in parallel with different output current capability. In [7], the controller area network (CAN) communication interface is utilized in a parallel inverter system to obtain a higher reliability. In [8], a new voltage and frequency droop control for parallel inverter systems is proposed to allow a robust current sharing without communication between inverters.In this paper, the paralleled inverters adopt the LCL filter as the output stage to allow the inverter to operate in both grid-tieand standalone modes. The design procedure of LCL filter in this universal inverter including sensor position and component selection will be discussed. By selecting the filter capacitor voltage and inverter-side inductor current as control feedbacks, the controller of LCL-filter inverter can be easily designed. For grid-tie operation, the current loop employs a PR controller and admittance compensation to achieve high loop gain at the fundamental frequency and to eliminate negative power flow transient during start-up. For standalone operation, one of inverters is selected to incorporate a voltage loop in a dual-loop control system with PR-controller on the voltage loop and a P-controller on the current loop to limit current magnitude under transient, to enhance voltage loop stability, to allow equal current sharing, and to reduce voltage steady-state error. The rest of inverters operate in grid-tie mode with only current loop control to share the load current. Both the simulation and experimental results verify that the designed controllers are capable of paralleling inverter operation in grid-tie and standalone modes by adapting to different controller setting while keeping the same hardware setup.II. LCL D ESIGN C ONSIDERATIONSA. System Configuration of LCL-Based InverterFig. 1(a) shows the system configuration of an LCL filter inverter operating in the grid-tie mode. Depending on the input voltage level, if the input voltage V in is low and highly unregulated such as fuel cell and PV source, a dc-dc converter is needed before the inverter stage. The inverter output inductor L i , the filter capacitor C f , and the grid-side inductor L g constitute the LCL filter of the inverter. In grid-tie applications, the load is normally modeled as a constant voltage source v s in series with a source impedance L s . Because the grid voltage is known, the way to control the power sending to the grid is to control the inverter output current with current-mode control. Fig. 1(b) represents the LCL inverter used for the standalone operation. On the other hand, most of the standalone loads require the output voltage to be regulated to supply the loads with a desired voltage.s V(a)V(b)Fig. 1. (a) LCL based inverter in grid-tie application, and (b) LCL basedinverter in standalone application.B. Sensor Position Selection for the LCL-Based Inverter First of all, the grid-side voltage v g needs to be sensed for synchronization in grid-tie operations. Next, the capacitor voltage v ac needs to be sensed to regulate output voltage in standalone mode operations. In addition, by selecting the v ac and inverter-side-inductor current i ac as feedback signals instead of v g or grid-side inductor current i g , the duty-cycle-to-output-current transfer function in grid-tie mode will be a first-order system which will greatly simplify the controller design [9]. Furthermore, compared to the current sensor signal i g , feedback of current i ac not only allows the sensor to be easily integrated into the inverter but also reduces the noise in the sensor conditioning circuit because the physical sensor location is closer to the controller board.C. Selection of Inverter-Side Inductor L iThe selection of the inverter-side inductor L i should compromise the output current performance, system cost, size, and efficiency. For example, with a higher L i value, lower current ripple can be obtained and higher controller gain can be designed to obtain better current performance. Using i ac as the feedback current signal, the simplified duty-cycle-to-current transfer function of an LCL inverter G id (s ) can be expressed in (1).i dc ac id sL V s d s i s G ==)()()( (1) Here d is the inverter duty cycle, and V dc is the dc link voltage. However, higher inductance value requires higher cost and occupies larger volume. As for the efficiency, higher inductance allows lower current ripple in the inductor L i , which decreases core losses of the inductor. On the other hand, higher inductance value increases the winding loss for longer wire required. The total inductor losses depend on the core materials, core structures, wires, and winding methods.D. Selection of the Filter CapacitorIf the inverters are implemented only for grid-tie applications, the selection of C f can be determined by limiting the reactive power consumed in C f [10,11]. On the other hand, in the design of universal inverters, the selection of the filter capacitor will be determined by the required voltage ripple damping because the inverter-side inductor L i and the filter capacitor C f will form a second-order filter that provides a -40dB/dec attenuation after the resonant frequency of this L i -C f filter.E. Selection of the Grid-Side Inductor L gFor the grid-tie inverter shown in Fig. 1(a), the transfer function from duty cycle d to i ac can be derived in (2). ()()2()()()1ac dci g s i g s f i g s i s V d s L L L s L L L s C L L L =⎧⎫⎡⎤+⎪⎪⎡⎤+++⎢⎥⎨⎬⎣⎦++⎢⎥⎪⎪⎣⎦⎩⎭(2)As compared to (1), the denominator of (2) has two more resonant poles that may cause the stability issues. In [21], this resonant frequency was limited in the range neither close to thecurrent cross-over frequency nor close to the switching frequency to avoid resonance issues. After L i and C f are determined, L g needs to be selected so that the resonant frequency is in a proper frequency range to ensure the stability.III. P ROPORTIONAL -R ESONANT C ONTROLLER FORG RID -T IE I NVERTER O PERATIONThe control object in grid-tie operation is its output current because the output voltage is already determined by the grid. The control system shown in Fig. 2 employs the voltage acrossthe f iltering capacitor , v ac and the current of the inverter-side inductor , i ac as the f eedback signals. Such an arrangement allows the first-order control-to-current transfer function G id (s ) shown in (1) to be used for controller design.operation.As indicated in [9], capacitor voltage v ac introduces anundesired current, and its relationship can be expressed in (3). Here G iv (s) can be considered as an intrinsic admittance, which causes a negative current flow and can damage the system by overcharging the dc-link capacitors.iLi ac ac iv sL r s v s i s G +==1)()()( (3) Here the L i and r Li are the inverter-side inductance and itsequivalent resistance, respectively. This undesired admittanceterm G iv (s) can be eliminated by an admittance compensation,and thus allowing the following duty-cycle-to-output-currentG id (s) to be used in the controller design .i Li dc ac id sL r V s d s i s G +==)()()( (4) Equations (4) and (1) are essentially the same except the (1) neglects the resistive component r Li . For the system under test, V dc = 420V, r Li = 80m Ω, and L i = 1mH. Negligence of r Lishould not impact the controller design. The open current loop gain G ioloop (s) controlled inverter can be obtained in (5).()*()**()ioloop m id i lf G s F G s H G s =Here G lf (s) is the low-pass filter combination in the hardware which includes a second-order low-pass filter at 48 kHz and a first-order anti-aliasing filter at 9.6 kHz. H i is the current feedback gain with a 34.133 magnitude, and F m is the DSP modulation gain with a magnitude of 1/1250. The design purpose of the current-controlled inverter is to provide an output current that tracks the external command as close as possible, a PR controller shown in (6) is utilized to provide a high loop gain at the fundamental frequency [15].2212()2c r i p c k sG s k s s ωωω=+++ (6) Here k p is the proportional gain, k r is the resonant gain, ωc is the equivalent bandwidth, and ω1 is the fundamental angular frequency. With the designed controllers, the compensated loop gain T i (s) can be represented in (7).()()*()i i ioloop T s G s G s = (7) By choosing k p = 0.78, k r = 97.5, ωc = 10 rad/second, andω1 = 377 rad/second in G i (s), the Bode plots of G ioloop (s) and T i (s) can be shown in Fig. 3.M a g n i t u d e (d B )101010104P h a s e (d e g )Frequency (Hz) Fig.3. The Bode plots of compensated current loop gain T i (s) and current open loop gain G ioloop (s). IV. V OLAGE D UAL -L OOP C ONTROLLR FORS TANDALONE I NVERTER O PERATION A. Control Block DiagramAs shown in Fig. 4, the inverter is controlled in a dual-loopvoltage control [18,19] to ensure system safety and enablecurrent sharing capability among parallel inverters. In thisdual-loop controller, a current inner loop damps the LCresonance pole while a voltage outer loop regulates the outputvoltage.standalone operation.B. Inner Current Controller DesignBecause of the same inverter hardware setup, the current open loop transfer function G ioloop (s) is the same as that shown in (5). However, the design goal of the current loop in a dual-loop control is to have a high loop bandwidth with enough stability margin rather than to reduce the current steady-state error by providing a high gain at fundamental frequency. Withthe first-order loop transfer function G ioloop (s), this current controller is only a simple proportional gain with a softwarelow-pass filter shown in (8). ()0.5()SWFi SWF G s s ωω=+ (8)Even though the control system does not contain any resonant poles by carefully selecting the sensor positions, the LCL filter hardware does contain resonant poles that could cause resonance on output voltage and current, as indicated in (2). The LCL parameters are L i = 1 mH, C f = 6.8 μF, L g = 0.22 mH which results in a resonant frequency at 4.54 kHz. Thus a 1.5 kHz software first-order low-pass filter is designed to damp possible oscillations at outputs. With the designed current controller, the compensated current loop gain T i (s ) is shown in (9). The Bode plots of T i (s) and G ioloop (s) can be shown in Fig. 5.T i (s) = G i (s)⋅G ioloop (s) (9)101010104P h a s e (d e g )M a g n i t u d e (d B )Frequency (Hz)Fig.5. The Bode plots of compensated current loop gain T i (s) and current openloop gain G ioloop (s).C. Outer Voltage Controller DesignAfter closing the inner current loop, the outer open voltageloop gain can be expressed in (10).G voloop (s) = G icloop (s)*G vi (s)*H v *G lf (s) (10)Here H v is the voltage sensor feedback gain, which is 5.12 in the test case. G icloop (s ) and G vi (s ) are the current closed loop gain and output current to output voltage transfer function, respectively. Equation (11) expresses the closed-loop gain of the inner current loop, G icloop (s ). ()**()()1()i m id icloop i G s F G s G s T s =+Assume that the load is a pure resistive load with a R o value in Fig. 1(b), the output current to output voltage transfer function G vi (s) can be represented in (12).()211211()**(),,,11,,g z vi g f oz p p g o g g fL s G s L C s p s p R L R a b c L L C ωωωω+=++==−⎢⎥⎣⎦=== (12) The design goal of a dual-loop voltage controller is to obtain a high gain at the fundamental frequency while providing enough bandwidth and stability margin. As shown in (13), a PR controller is adopted here to eliminate the steady-state error by providing a high gain at the fundamental frequency.2212()(2c r v p c k sG s k s s ωωω=+++ (13)With 20% load as the design plant, a PR controller is designed to have k p = 0.02, k r = 12, c = 10 rad/s, and 1 = 377 rad/s. The resulting Bode plots of the compensated voltage loop gain T v (s) = G v (s)*G voloop (s) along with the uncompensated voltage loop gain G voloop (s) are shown in Fig. 6.10M a g n i t u d e (d B )1010104P h a s e (d e g )Frequency (Hz)Fig.6. The Bode plots of compensated voltage loop gain T v (s) and voltage open loop gain G ioloop (s) in a dual loop controlled inverter at 20% rated power.V. P ARALLEL I NVERTERS WITH LCL F ILTERSUNDER S TANDALONE M ODEA. System ConfigurationThe parallel inverter system under standalone has the same hardware configuration as that under grid-tie modeconfiguration except that the load is replaced with a source.Fig. 7 shows the entire system diagram. In this system, one of the inverters needs to be operating in dual loop control and serve as the voltage reference or the grid voltage source. The rest of inverters will be operating in grid-tie mode, and a single current loop will serve the control purpose.LoadV in-V in-V Fig. 7. Hardware configuration of paralleled LCL based inverters.The selection of the inverter running in dual-loop mode orsingle-loop mode is determined by the upper level command line, which comes from a CAN bus. Fig. 8 shows the control system diagram with multiple inverters in parallel. Hereinverter 1 operates in dual loop and provides the voltage reference. Inverter 2 and the rest will lock the phase to the reference voltage and operate in single current loop.Fig. 8. Control block diagram of a paralleled LCL inverter system.B. Current Sharing and Synchronization through CAN BusIn order to share the current between inverters, the CAN bus is utilized to ensure a reliable communication interface [7]. The simplest way to transmit the current reference is to send the current reference directly in ac quantity. However, this method is not practical for the increasing phase delay in ac signal if the transmission length is too long which limits the transmission speed of the CAN interface.In order to overcome the phase delay in ac signal, the transmission signal is the magnitude of i ref1 in dc quantity. The current reference magnitude information shares the current evenly which minimizes the thermal stress of whole system. The phase is synchronized with a phase-locked loop control, similar to the grid-tie control system. The automatic phase adjustment block shown in Fig. 8 is to adjust the phase information of current reference i ref2 automatically by monitoring the phase difference of i ac2 and v ac2.VI.I MPLEMENTATION R ESULTSA. Experimental SetupThe hardware setup consists of two 5-kW power conditioning systems. Each PCS consists of a dc-dc converter to boost the low-voltage input 48 V to 400 V and a dc-ac inverter that produces 208 V ac output for the grid connection. The source of the dc-dc converter can be a fuel cell or a photovoltaic, but for this testing, a 60-V, 20-kW fuel cell simulator was used to serve as the source. Each PCS is packaged in a standard 19” rack-mount case with power connection on the back panel, and the DSP controller on the front panel. Fig. 9 shows the photograph of the hardware setup with two identical PCS’s sitting side by side.dc-dc converter dc-ac inverterfilter boardPCS-1PCS-2Fig. 9. Photograph showing two parallel connected PCS’s packaged instandard rack-mount cases.B. Grid-Tie Mode OperationFig. 10(a) shows the simulation results of the LCL-filter inverter running in current-mode control with PR controller and admittance compensation. The results show that the output current follows a 32-A peak command current very well because of a high loop gain at the fundamental frequency. Fig. 10(b) shows the experimental results under 32-A peak current command in the grid-tie condition. Waveforms indicate that the output current well follows the command, which suggests the current loop PR controller with admittance compensation provides a high loop gain at the fundamental frequency to eliminate the steady-state output error.Time100ms150ms200msI(Lg)-40A0A40ASEL>>V(Vac)- V(Vb0)-400V0V400Vvacig(a)t:10ms/div20A300Vv aci g(b)Fig. 10. Current loop implementation results at 4.85kW (a) Pspice simulation result at 32A i ref, pk, , and (b) experimental result at 32A i ref, pk.C. Standalone Mode Operation Fig. 11(a) and Fig. 11(b) show the simulation and experimental results of the duel-loop controlled LCL-filterinverter with a PR-controller based outer voltage-loop and a P-controller based inner current-loop operation. The output voltage v ac is 215 V rms, and the output current i load is 24.2 Arms. The power output of 5.2-kW goes into a pure resistive load in both simulated and tested cases. The simulation includes all the dynamics of system transfer function andcontroller blocks shown in Fig. 4. Again, the experimental result agrees with the simulation result very well.SEL>>Time 100ms 125ms150ms 175ms200msI(RLoad)-40A0A40A V(Vac1)- V(Vb01)-400V0V400V(a)t :10ms/div300V20Av aci load(b)Fig. 11. Voltage dual-loop results at 215V v ac, rms , 5.2kW (a) Pspice simulationresult, and (b) experimental result.Fig. 12 shows the simulation and experimental results of the paralleled inverters supplying to a 7.6 kW load. Load voltage v load and total current i load are the waveforms observed at the load terminal. Current i out1 and i out2 are monitored at the individual inverters. Both simulation and experimental results indicate that output currents are in phase between two inverters, and both parallel inverters share current evenly to supply the load together. With the observation of total current i load being equal to the sum of i out 1 and i out 2, one can easily conclude that there is no circulating current in between the dual-loop controlled and single-loop controlled inverters. The phase-locked loop and automatic phase adjustment control work effectively.The even distribution of current between paralleled inverters also indicates that the CAN communication, that transmits the reference current magnitude to different PCS’sworks well, and the proposed design should allow modular inverter design for a high power paralleled inverter system.SEL>>Time100ms 125ms150ms 175ms200msI(Lg_i)-80A 80AI(Lg_v)-80A0A 80AI(RLoad)-80A0A80AV(Vload)- V(Vb01)-400V0V 400Vi out1i out2(a)v load i load i out1t :10ms/div40Ai out240A40A(b)Fig.12. Parallel inverters operation at 215V v load, rms , 7.6kW (a) Pspicesimulation result, and (b) experimental result.VII. C ONCLUSIONComplete design and implementation results of a paralleled power conditioning system operating in both grid-tie and standalone modes were presented in this paper. Key design features of the proposed inverter system are summarized as follows.1. Design of LCL filterThis paper suggested design considerations on current ripple, stability, output performance, sensor location, noise, and ease of controller design. 2. Design of dual- and single-loop controllersFor grid-tie operation, a single current loop controller design with PR controller and admittance compensation is proposed to reduce the steady-state error while maintaining system stability. For standalone operation, a dual-loop control system with PR-controller for outervoltage loop and a P-controlled for inner current loop isproposed to limit peak current magnitude undertransient, enhance voltage loop stability, and reducevoltage steady-state error.3.Design of synchronization and equal current sharingThe synchronization is implemented with PLL and anautomatic phase adjustment to synchronize the outputcurrents among different inverters. The CAN bus isadapted as upper level commander to specify one unit tooperate in dual loop control and to transmit currentreference command magnitude to individual inverters. Simulation and experimental results show that the designed inverters are capable of parallel operation in both grid-tie and standalone modes by adapting to different controller sets with the same hardware setup. The LCL filter based inverter controlled with the proposed single- and dual-loop controllers for different operating modes shows stable output waveforms. The output current is equally shared among different inverters without noticeable circulating current by the use of the proposed synchronization and upper level control methods. The successful parallel operation results suggest that the proposed design with LCL filter based inverter, mix of dual- and single-loop voltage and current controllers, PLL synchronization and CAN bus communication architecture can be extended to microgrid or smartgrid applications where both the grid-tie and standalone operations are needed.A CKNOWLEDGMENTThe authors would like to thank Mr. M. H. Lin and his group of Tatung System Technologies, Taipei, Taiwan for both financial and technical supports of the project.R EFERENCES[1]S. J. Chiang, C. M. Liaw, W. C. Chang and W. Y. Chang, “Multi-moduleparallel small battery energy storage system,” IEEE Trans. Energy Conversion, vol. 11, pp. 146-54, Mar. 1996.[2]J. F. Chen, C. L. Chu, and C. L. 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