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Data Memory
数据存储器
Te context with microcontrollers,
术语“数据存储器”用于微控制器。
The memory which stores data,i.e.RAM,is called data memory.
用来存储数据的存储器，即RAM，被称作数据存储器
The diffenent versions of 8048 series of microcontrollers microcontrollers contain 64,128.256 bytes of RAM.
8048系列的不同版本的微控制器包含64、128、256字节的RAM。
Data Memory The term data memory is used in the context with microcontrollers,The memory which stores data,i.e.RAM,is called data memory.The diffenent versions of 8048 series of microcontrollers microcontrollers contain 64,128.256 bytes of RAM.The 8048AH,8049AH and 8050AH contain 64,128 and 256 bytes of RAM respectively.64/128/256 bytes of RAM is used either as read/write memory or general-purpose registers.
There is need of cyclical reading (lower than 1 minute periods) of the actual values from the real-time clock and the sensors for pressure and temperature, and to store the read values into the microcontroller’s memory. The communication with the real-time clock and the sensors is possible with the use of I2C interface and the previously defined in the specifications protocols for reading and writing.

51单片机英文及其翻译

英文翻译原文：51 Microcontroller IntroductionMicrocontrollers basic component is a central processing unit (CPU in the computing device and controller), read-only memory (usually expressed as a ROM), read-write memory (also known as Random Access Memory MRAM is usually expressed as a RAM) , input / output port (also divided into parallel port and serial port, expressed as I / O port), and so composed. In fact there is also a clock circuit microcontroller, so that during operation and control of the microcontroller, can rhythmic manner. In addition, there are so-called "break system", the system is a "janitor" role, when the microcontroller control object parameters that need to be intervention to reach a particular state, can after this "janitor" communicated to the CPU, so that CPU priorities of the external events to take appropriate counter-measures.Microcontrollers are used in a multitude of commercial applications such as modems, motor-control systems, air conditioner control systems, automotive engine and among others. The high processing speed and enhanced peripheral set of these microcontrollers make them suitable for such high-speed event-based applications. However, these critical application domains also require that these microcontrollers are highly reliable. The high reliability and low market risks can be ensured by a robust testing process and a proper tools environment for the validation of these microcontrollers both at the component and at the system level. Intel Platform Engineering department developed an object-oriented multi-threaded test environment for the validation of its AT89C51 automotive microcontrollers. The goals of this environment was not only to provide a robust testing environment for the AT89C51 automotive microcontrollers, but to develop an environment which can be easily extended and reused for the validation of several other future microcontrollers. The environment was developed in conjunction with Microsoft Foundation Classes (AT89C51). The paper describes the design and mechanism of this test environment, its interactions with various hardware/software environmental components, and how to use AT89C51.Are 8-bit microcontroller early or 4 bits. One of the most successful is the INTEL 8031, for a simple, reliable and good performance was a lot of praise. Then developed in 8031 out of MCS51 MCU Systems. SCM systems based on this system until now is still widely used. With the increased requirements of industrial control field, began a 16-bit microcontroller, but not ideal because the cost has not been very widely used. After 90 years with the great development of consumer electronics, microcontroller technology has been a huge increase. With INTEL i960 series, especially the later series of widely used ARM, 32-bit microcontroller quickly replace high-end 16-bit MCU status and enter the mainstream market. The traditional 8-bit microcontroller performance have been therapid increase capacity increase compared to 80 the number of times. Currently, high-end 32-bit microcontroller clocked over 300MHz, the performance catching the mid-90s dedicated processor, while the average model prices fall to one U.S. dollar, the most high-end model is only 10 dollars. Modern SCM systems are no longer only in the development and use of bare metal environment, a large number of proprietary embedded operating system is widely used in the full range of SCM. The handheld computers and cell phones as the core processing of high-end microcontroller can even use a dedicated Windows and Linux operating systems.SCM relies on the program, and can be modified. Through different procedures to achieve different functions, in particular special unique features, this is another device much effort needs to be done, some are great efforts are very difficult to achieve. A not very complex functions if the 50's with the United States developed 74 series, or the 60's CD4000 series of these pure hardware buttoned, then the circuit must be a large PCB board! But if the United States if the 70's with a series of successful SCM market, the result will be a drastic change! Just because you are prepared by microcomputer programs can achieve high intelligence, high efficiency and high reliability!IntroductionThe 8-bit AT89C51 CHMOS microcontrollers are designed to handle high-speed calculations and fast input/output operations. MCS 51 microcontrollers are typically used for high-speed event control systems. Commercial applications include modems, motor-control systems, printers, photocopiers, air conditioner control systems, disk drives, and medical instruments. The automotive industry use MCS 51 microcontrollers in engine-control systems, airbags, suspension systems, and antilock braking systems (ABS). The AT89C51 is especially well suited to applications that benefit from its processing speed and enhanced on-chip peripheral functions set, such as automotive power-train control, vehicle dynamic suspension, antilock braking, and stability control applications. Because of these critical applications, the market requires a reliable cost-effective controller with a low interrupt latency response, ability to service the high number of time and event driven integrated peripherals needed in real time applications, and a CPU with above average processing power in a single package. The financial and legal risk of having devices that operate unpredictably is very high. Once in the market, particularly in mission critical applications such as an autopilot or anti-lock braking system, mistakes are financiallyProhibitive. Redesign costs can run as high as a $500K, much more if the fix means back annotating it across a product family that share the same core and/or peripheral design flaw. In addition, field replacements of components are extremely expensive, as the devices are typically sealed in modules with a total value several times that of the component. To mitigate these problems, it is essential that comprehensive testing of the controllers be carried out at both the component level and system level under worst case environmental and voltage conditions. This complete and thorough validation necessitates not only a well-defined process but also a proper environment and tools to facilitate and execute the mission successfully.Intel Chandler Platform Engineering group provides postSilicon system validation (SV) of various micro-controllers and processors. The system validation process can be broken into three major parts. The type of the device and its application requirements determine which types of testing are performed on the device.The AT89C51 provides the following standard features: 4Kbytes of flash, 128 bytes of RAM, 32 I/O lines, two 16-bittimer/counters, five vector two-level interrupt architecture, a full duple ser -ail port, on-chip oscillator and clock circuitry. In addition, the AT89C51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt sys -tem to continue functioning. The Power-down Mode saves the RAM contents but freezes the social -labor disabling all other chip functions until the next hardware reset.Pin DescriptionVCC Supply voltage.GND Ground.Port 0Port 0 is an 8-bit open-drain bi-directional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high impedance inputs.Port 0 may also be configured to be the multiplexed lowered address/data bus during accesses to external program and data memory. In this mode P0 has internal pull-ups’.Port 0 also receives the code bytes during Flash programming, and outputs the code bytes during program verification. External pull-ups are required during program verification.Port 1Port 1 is an 8-bit bi-directional I/O port with internal pullups.The Port 1 output buffers can sink/so -urge four TTL inputs. When 1s are written to Port 1 pins they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups.Port 1 also receives the low-order address bytes during Flash programming and verification.Port 2Port 2 is an 8-bit bi-directional I/O port with internal pullups.The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups.Port 2 emits the high-order address byte during fetches from external program memory and during accesses to Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups.Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that uses 16-bit addresses (MOVX @DPTR). In this application, it uses strong internal pull-ups when emitting 1s. During accesses to external data memory that uses 8-bit addresses (MOVX @ RI); Port 2 emits the contents of the P2 Special Function Register.Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.Port 3Port 3 is an 8-bit bi-directional I/O port with internal pullups.The Port 3 output buffers can sink/soul -race four TTL inputs. When 1s are written to Port 3 pins they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pull-ups.RSTReset input. A high on this pin for two machine cycles while the oscillator is running resets the device.ALE/PROGAddress Latch Enable output pulse for latching the low byte of the address during accesses to external memory.This pin is also the program pulse input (PROG) during Flash programming.In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped dui -nag each access to external DataMemory.If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.PSENProgram Store Enable is the read strobe to external program memory. When the AT89C51 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory.EA/VPPExternal Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. A should be strapped to VCC for internal program executions. This pin also receives the 12-volt programming enable voltage (VPP) during Flash programming, for parts that require 12-volt VPP.The AT89C51 code memory array is programmed byte-by byte in either programming mode. To program any nonblank byte in the on-chip Flash Memory, the entire memory must be erased using the Chip Erase Mode.Data Polling: The AT89C51 features Data Polling to indicate the end of a write cycle. During a write cycle, an attempted read of the last byte written will result in the complement of the written datum on PO.7. Once the write cycle has been completed, true data are valid on all outputs, andThe next cycle may begin. Data Polling may begin any time after a write cycle has been initiated.Ready/Busy: The progress of byte programming can also be monitored by the RDY/BSY output signal. P3.4 is pulled low after ALE goes high during programming to indicate BUSY. P3.4 is pulled high again when programming is done to indicate READY.Program Verify: If lock bits LB1 and LB2 have not been programmed, the programmed code data can be read back via the address and data lines for verification. The lock bits cannot be verified directly. Verification of the lock bits is achieved byobserving that their features are enabled.A microcomputer interface converts information between two forms. Outside the microcomputer the information handled by an electronic system exists as a physical signal, but within the program, it is represented numerically. The function of any interface can be broken down into a number of operations which modify the data in some way, so that the process of conversion between the external and internal forms is carried out in a number of steps.An analog-to-digital converter (ADC) is used to convert a continuously variable signal to a corresponding digital form which can take any one of a fixed number of possible binary values. If the output of the transducer does not vary continuously, no ADC is necessary. In this case the signal conditioning section must convert the incoming signal to a form which can be connected directly to the next part of the interface, the input/output section of the microcomputer itself.Output interfaces take a similar form, the obvious difference being that here the flow of information is in the opposite direction; it is passed from the program to the outside world. In this case the program may call an output subroutine which supervises the operation of the interface and performs the scaling numbers which may be needed for a digital-to-analog converter (DAC). This subroutine passes information in turn to an output device which produces a corresponding electrical signal, which could be converted into analog form using a DAC. Finally the signal is conditioned (usually amplified) to a form suitable for operating an actuator.The signals used within microcomputer circuits are almost always too small to be connected directly to the “outside world” and some kind of interface must be used to translate them to a more appropriate form. The design of section of interface circuits is one of the most important tasks facing the engineer wishing to apply microcomputers. We have seen that in microcomputers information is represented as discrete patterns of bits; this digital form is most useful when the microcomputer is to be connected to equipment which can only be switched on or off, where each bit might represent the state of a switch or actuator.To solve real-world problems, a microcontroller must have more than just a CPU, a program, and a data memory. In addition, it must contain hardware allowing the CPU to access information from the outside world. Once the CPU gathers information and processes the data, it must also be able to effect change on some portion of the outside world. T hese hardware devices, called peripherals, are the CPU’s window t o the outside.The most basic form of peripheral available on microcontrollers is the general purpose I70 port. Each of the I/O pins can be used as either an input or an output. The function of each pin is determined by setting or clearing corresponding bits in a corresponding data direction register during the initialization stage of a program. Each output pin may be driven to either a logic one or a logic zero by using CPU instructions to pin may be viewed (or read.) by the CPU using program instructions.Some type of serial unit is included on microcontrollers to allow the CPU to communicate bit-serially with external devices. Using a bit serial format instead of bit-parallel format requires fewer I/O pins to perform the communication function, which makes it less expensive, but slower. Serial transmissions are performed either synchronously or asynchronously.Its applicationsSCM is widely used in instruments and meters, household appliances, medical equipment, aerospace, specialized equipment, intelligent management and process control fields, roughly divided into the following several areas:SCM has a small size, low power consumption, controlling function, expansion flexibility, the advantages of miniaturization and ease of use, widely used instrument, combining different types of sensors can be realized, such as voltage, power, frequency, humidity, temperature, flow, speed, thickness, angle, length, hardness, elemental, physical pressure measurement. SCM makes use of digital instruments, intelligence, miniaturization, and functionality than the use of more powerful electronic or digital circuits. Such as precision measuring equipment (power meter, oscilloscope, various analytical instrument).译文：51单片机简介单片机的基本组成是由中央处理器（即CPU中的运算器和控制器）、只读存贮器（通常表示为ROM）、读写存贮器（又称随机存贮器通常表示为RAM）、输入/输出口（又分为并行口和串行口，表示为I/O口）等等组成。

完整word版,51单片机英文及其翻译

AT89C51单片机中英文对照外文翻译文献

(文档含英文原文和中文翻译) 中英文资料对照外文翻译原文：DescriptionThe AT89C51 is a low-power, high-performance CMOS 8-bit microcomputer with 4K bytes of Flash Programmable and Erasable Read Only Memory (PEROM) and 128 bytes RAM. The device is manufactured using At mel’s high density nonvolatile memory technology and is compatible with the industry standardMCS-51™ instruction set and pinout. The chip combines a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89C51 is a powerful microcomputer which provides a highly flexible and cost effective solution to many embedded control applications.Features:• Compatible with MCS-51™ Products• 4K Bytes of In-System Reprogrammable Flash Memory• Endurance: 1,000 Write/Erase Cycles• Fully Static Operation: 0 Hz to 24 MHz• Three-Level Program Memory Lock• 128 x 8-Bit Internal RAM• 32 Programmable I/O Lines• Two 16-Bit Timer/Counters• Six Interrupt Sources• Programmable Serial Channel• Low Power Idle and Power Down ModesThe AT89C51 provides the following standard features: 4K bytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bit timer/counters, a five vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator and clock circuitry. In addition, the AT89C51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt system to continue functioning. The Power Down Mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset.Pin Description:VCC Supply voltage.GND Ground.Port 0Port 0 is an 8-bit open drain bidirectional I/O port. As an output port each pin cansink eight TTL inputs. When is are written to port 0 pins, the pins can be used as highimpedance inputs.Port 0 may also be configured to be the multiplexed loworder address/data bus during accesses to external program and data memory. In this mode P0 has internal pullups.Port 0 also receives the code bytes during Flash programming, and outputs the code bytes during program verification. External pullups are required during program verification.Port 1Port 1 is an 8-bit bidirectional I/O port with internal pullups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pullups.Port 1 also receives the low-order address bytes during Flash programming and verification.Port 2Port 2 is an 8-bit bidirectional I/O port with internal pullups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (I IL) because of the internal pullups.Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @ DPTR). In this application it uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register.Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.Port 3Port 3 is an 8-bit bidirectional I/O port with internal pullups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pullups.Port 3 also serves the functions of various special features of the AT89C51 as listed below:Port pin alternate functionsP3.0 rxd (serial input port)P3.1 txd (serial output port)P3.2 ^int0 (external interrupt0)P3.3 ^int1 (external interrupt1)P3.4 t0 (timer0 external input)P3.5 t1 (timer1 external input)P3.6 ^WR (external data memory write strobe)P3.7 ^rd (external data memory read strobe)Port 3 also receives some control signals for Flash programming and verification.RSTReset input. A high on this pin for two machine cycles while the oscillator is running resets the device.ALE/PROGAddress Latch Enable output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming.In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory.If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.PSENProgram Store Enable is the read strobe to external program memory.When the AT89C51 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory.EA/VPPExternal Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset.EA should be strapped to VCC for internal program executions.This pin also receives the 12-volt programming enable voltage(VPP) during Flash programming, for parts that require 12-volt VPP.XTAL1Input to the inverting oscillator amplifier and input to the internal clock operating circuit.XTAL2Output from the inverting oscillator amplifier.Oscillator CharacteristicsXTAL1 and XTAL2 are the input and output, respectively, of an invertingamplifier which can be configured for use as an on-chip oscillator, as shown in Figure 1. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 2. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through adivide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed.Idle ModeIn idle mode, the CPU puts itself to sleep while all the onchip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset.It should be noted that when idle is terminated by a hard ware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory.Status of External Pins During Idle and Power Down Modesmode Program memory ALE ^psen Port0 Port1Port2Port3idle internal 1 1 data data data Data Idle External 1 1 float Data data Data Power down Internal 0 0 Data Data Data Data Power down External 0 0 float data Data data Power Down ModeIn the power down mode the oscillator is stopped, and the instruction that invokes power down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the power down mode is terminated. The only exitfrom power down is a hardware reset. Reset redefines the SFRs but does not changethe on-chip RAM. The reset should not be activated before VCC is restored to itsnormal operating level and must be held active long enough to allow the oscillator torestart and stabilize.Program Memory Lock BitsOn the chip are three lock bits which can be left unprogrammed (U) or can be programmed (P) to obtain the additional features listed in the table below: Lock Bit Protection ModesProgram lock bits Protection typeLb1 Lb2 Lb31 U U U No program lock features2 P U U Movc instructions executed from external programmemory are disable from fetching code bytes frominternal memory, ^ea is sampled and latched onreset, and further programming of the flash disabled3 P P U Same as mode 2, also verify is disable.4 P P P Same as mode 3, also external execution is disabled.When lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during reset. If the device is powered up without a reset, the latch initializes to a random value, and holds that value until reset is activated. It is necessary that the latched value of EA be in agreement with the current logic level at that pin in order for the device to function properly.Programming the Flash：The AT89C51 is normally shipped with the on-chip Flash memory array in the erased state (that is, contents = FFH) and ready to be programmed.The programming interface accepts either a high-voltage (12-volt) or a low-voltage (VCC) program enable signal.The low voltage programming mode provides a convenient way to program the AT89C51 inside the user’s system, while the high-voltage programming mode is compatible with conventional third party Flash or EPROM programmers.The AT89C51 is shipped with either the high-voltage or low-voltage programming mode enabled. The respective top-side marking and device signature codes are listed in the following table.Vpp=12v Vpp=5vTop-side mark AT89C51xxxxyyww AT89C51 xxxx-5 yywwsignature (030H)=1EH(031H)=51H(032H)=FFH (030H)=1EH (031H)=51H (032H)=05HThe AT89C51 code memory array is programmed byte-bybyte in either programming mode. To program any nonblank byte in the on-chip Flash Programmable and Erasable Read Only Memory, the entire memory must be erased using the Chip Erase Mode.Programming Algorithm:Before programming the AT89C51, the address, data and control signals should be set up according to the Flash programming mode table and Figures 3 and 4. To program the AT89C51, take the following steps.1. Input the desired memory location on the address lines.2. Input the appropriate data byte on the data lines.3. Activate the correct combination of control signals.4. Raise EA/VPP to 12V for the high-voltage programming mode.5. Pulse ALE/PROG once to program a byte in the Flash array or the lock bits.The byte-write cycle is self-timed and typically takes no more than 1.5 ms. Repeatsteps 1 through 5, changing the address and data for the entire array or until the end ofthe object file is reached.Data Polling: The AT89C51 features Data Polling to indicate the end of a write cycle. During a write cycle, an attempted read of the last byte written will result in the complement of the written datum on PO.7. Once the write cycle has been completed,true data are valid on all outputs, and the next cycle may begin. Data Polling maybegin any time after a write cycle has been initiated.Ready/Busy: The progress of byte programming can also be monitored by theRDY/BSY output signal. P3.4 is pulled low after ALE goes high during programmingto indicate BUSY. P3.4 is pulled high again when programming is done to indicate READY.Program Verify: If lock bits LB1 and LB2 have not been programmed, the programmed code data can be read back via the address and data lines for verification.The lock bits cannot be verified directly. Verification of the lock bits is achieved by observing that their features are enabled.Chip Erase: T he entire Flash Programmable and Erasable Read Only Memoryarray is erased electrically by using the proper combination of control signals and by holding ALE/PROG low for 10 ms. The code array is written with all “1”s. The chiperase operation must be executed before the code memory can be re-programmed.Reading the Signature Bytes: The signature bytes are read by the sameprocedure as a normal verification of locations 030H, 031H, and 032H, except thatP3.6 and P3.7 must be pulled to a logic low. The values returned are as follows.(030H) = 1EH indicates manufactured by Atmel(031H) = 51H indicates 89C51(032H) = FFH indicates 12V programming(032H) = 05H indicates 5V programmingProgramming InterfaceEvery code byte in the Flash array can be written and the entire array can beerased by using the appropriate combination of control signals. The write operationcycle is selftimed and once initiated, will automatically time itself to completion.P2.6 P2.7 P3.6 P3.7 mode RST ^PSEN ALE/^PROG ^EA/VppWrite code data H L H/12V L H H H Read code data H L H H L L H H Bit-1 H L H/12V H H H HTable 1 Flash Programming ModesNote: 1.chip erase requires a 10-ms PROG pulseFigure 3. Programming the Flash Figure 4. Verifying the FlashFlash Programming and Verification CharacteristicsTA = 0°C to 70°C, VCC = 5.0 10%Symbol parameter minmax Units Vpp ⑴ Programming enablevoltage11.5 12.5 V Ipp ⑴ Programming enablecurrent1.0 mA 1/Tclcl Oscillator frequency 324 MHZ Tavgl Address setup to ^PSEN low48TclclTghax Address hole after ^PSEN48TclclTdvgl Data setup to ^PSEN low48TclclTghdx Data hole after ^PSEN 48TclclTehsh P2.7(^enable)high to 48TclclWrite lock Bit-2 HL H/12V H H L L Bit-3 H LH/12V H L H L Chip erase H LH/12V H L L L Read signature syte HL H H L L L LVppTshgl Vpp setup to ^PSEN10 uslow10 usTghsl⑴Vpp hole after^PSENTglgh ^PSEN width 1 110 us Tavqv Address to data valid 48Tclcl48TclclTelqv ^enable low to datavalidTehqz Data float after0 48Tclcl^enable1.0 usTghbl ^PSEN high to ^busylowTwc Byte write cycle time 2.0 ms Note: 1. Only used in 12-volt programming mode.Flash Programming and Verification Waveforms - High Voltage Mode (VPP = 12V)Flash Programming and Verification Waveforms - Low Voltage Mode (VPP = 5V)Absolute Maximum Ratings*Operating Temperature.................................. -55°C to +125°C Storage Temperature ..................................... -65°C to +150°C Voltage on Any Pinwith Respect to Ground .....................................-1.0V to +7.0V Maximum Operating Voltage............................................. 6.6VDC Output Current...................................................... 15.0 mADC CharacteristicsTA = -40°C to 85°C, VCC = 5.0V 20% (unless otherwise noted)symb ol parameter condition min max unitsVil Input low voltage (except ^EA) -0.5 0.2Vcc-0.1VVil1 Input low voltage(^EA) -0.5 0.2Vcc-0.3VVih Input high voltage ExceptXTAL1,XTAL2 0.2Vcc+0.9Vcc+0.5 VVih1 Input high voltage (XTAL1,RST) 0.7Vcc Vcc+0.5 V Vol Output lowvoltage⑴(ports 1,2,3 )Iol=1.6mA 0.45 VVol1 Output lowvoltage⑴(port0,ALE,^PSEN) Ioh=3.2mA 0.45 V Ioh=-60uA,Vcc=-5V+10%2.4Ioh=-25uA 0.75VccVoh Output highvoltage⑴(ports 1,2,3 ) Ioh=-60uA,Vcc=5V+10%0.9Vcc VVoh1 Output lowvoltage⑴(port0,ALE,^Ioh=-800UA,Vcc=5V+10%2.4 V Ioh=-300uA, 0.75Vcc VPSEN) Ioh=-80uA 0.9Vcc V Iil Logical 0 inputcurrent(ports 1,2,3)Vin=0.45V -50 uAItl Logical 1 to 0 transitioncurrent(ports 1,2,3) Vin=2V,Vcc=5V+10%-650 uAIli Input leakagecurrent(port 0, ^EA)0.45<Vin<Vcc 50 +10 uARRS T Reset pulldown resistor 300 komCio Pin capacitance Testfreq=1MHZ,TA=25℃10 pFIcc Power supplycurrent Active mode, 12MHZ 20 mA Idlemode,12MHZ5 mAPower down mode⑵Vcc=6V 100 uA Vcc=3V 40 uANotes: 1. Under steady state (non-transient) conditions, IOL must be externally limited as follows:Maximum IOL per port pin: 10 mAMaximum IOL per 8-bit port: Port 0: 26 mAPorts 1, 2, 3: 15 mAMaximum total IOL for all output pins: 71 mA2. Minimum VCC for Power Down is 2V.AC Characteristics(Under Operating Conditions; Load Capacitance for Port 0, ALE/PROG, and PSEN = 100 pF; Load Capacitance for all other outputs = 80 pF)External Program and Data Memory CharacteristicsSymbol Parameter 12MHzOscillator 16to 24 MHz Oscillator UnitsMin Max Min Max1/T CLCL Oscillator Frequency024MHz T LHLL ALE Pulse Width 127 2T CLCL-40 ns T AVLL Address Valid to ALE Low 43 T CLCL-13 ns T LLAX Address Hold After ALE Low 48 T CLCL-20 ns T LLIV ALE Low to Valid Instruction In 233 4T CLCL-65 ns T LLPL ALE Low to PSEN Low 43 T CLCL-13 ns T PLPH PSEN Pulse Width 205 3T CLCL-20 ns T PLIV PSEN Low toValid Instruction In 145 3T CLCL-45 ns T PXIX InputInstructionHold After PSEN 0 0 ns T PXIZ InputInstructionFloat AfterPSEN 59 T CLCL-10 ns T PXAV PSEN to Address Valid 75 T CLCL-8 ns T AVIV Address to Valid Instruction In 312 5T CLCL-55 ns T PLAZ PSEN Low to Address Float 10 10 nsT RLRH RD Pulse Width 400 6T CLCL-100 ns T WLWH WR Pulse Width 400 6T CLCL-100 ns T RLDV RD Low to Valid Data In 252 5T CLCL-90 ns T RHDX Data Hold After RD 0 0 ns T RHDZ Data Float After RD 97 2T CLCL-28 ns T LLDV ALE Low to Valid Data In 517 8T CLCL-150 ns T AVDV Address to Valid Data In 585 9T CLCL-165 ns T LLWL ALE Low to RD or WR Low 200 300 3T CLCL-50 3T CLCL+50 ns T AVWL Address to RD or WR Low 203 4T CLCL-75 ns T QVWX Data Valid to WR Transition 23 T CLCL-20 ns T QVWH Data Valid to WR High 433 7T CLCL-120 ns T WHQX Data Hold After WR 33 T CLCL-20 ns T RLAZ RD Low to Address Float 0 0 ns T WHLH RD or WR High to ALE High 43 123 T CLCL-20 T CLCL+25 ns External Program Memory Read CycleExternal Data Memory Read CycleExternal Data Memory Write CycleExternal Clock Drive WaveformsExternal Clock Drive 符号参数最小值最大值单位 1/T CLCL Oscillator Frequency0 24MHz T CLCL Clock Period 41.6 ns T CHCX High Time 15 ns T CLCX Low Time 15 ns T CLCH Rise Time 20 ns T CHCL Fall Time20 nsSerial Port Timing: Shift Register Mode Test Conditions(VCC = 5.0 V 20%; Load Capacitance = 80 pF)符号参数12 MHz Osc VariableOscillator UnitsMi n M ax Min Max T XLXL Serial Port Clock Cycle Time 期1.0 12T CLCL usT QVXH Output Data Setup to Clock Rising Edge 700 10T CLCL -133 ns T XHQX Output Data Hold After Clock Rising Edge 50 2T CLCL -117 ns T XHDX Input Data Hold After Clock Rising Edge0 0 ns T XHDVClock Rising Edge to Input Data Valid 700 10T CLCL -133 nsShift Register Mode Timing WaveformsAC Testing Input/Output Waveforms(1)Note: 1. AC Inputs during testing are driven at VCC - 0.5V for a logic 1 and0.45V for a logic 0. Timing measurements are made at VIH min. for a logic 1 and VIL max. for a logic 0.Float Waveforms(1)Note: 1. For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to float when 100 mV change from the loaded VOH/VOL level occurs.Ordering InformationSpeed(MHz) PowerSupply Ordering Code Package OperationRange12 5V+20% AT89C51-12AC AT89C51-12JC AT89C51-12PC AT89C51-12QC 44A 44J 40P6 44QCommercial (0C to 70C) AT89C51-12AI AT89C51-12JI AT89C51-12PI AT89C51-12QI 44A 44J 40P6 44Q Industrial (-40C to 85C)16 5V +20%AT89C51-16ACAT89C51-16JCAT89C51-16PCAT89C51-16QC 44A44J40P644QCommercial(0C to 70C)AT89C51-16AI AT89C51-16JI AT89C51-16PI AT89C51-16QI 44A44J40P644QIndustrial(-40C to 85C)20 5V +20%AT89C51-20ACAT89C51-20JCAT89C51-20PCAT89C51-20QC 44A44J40P644QCommercial(0C to 70C)AT89C51-20AI AT89C51-20JI AT89C51-20PI AT89C51-20QI 44A44J40P644QIndustrial(-40C to 85C)24 5V +20%AT89C51-24ACAT89C51-24JCAT89C51-24PCAT89C51-24QC 44A44J40P644QCommercial(0C to 70C)AT89C51-24AI AT89C51-24JI AT89C51-24PI AT89C51-24QI 44A44J40P644QIndustrial(-40C to 85C)Package Type44A 44 Lead, Thin Plastic Gull Wing Quad Flatpack (TQFP) 44J 44 Lead, Plastic J-Leaded Chip Carrier (PLCC)40P6 40 Lead, 0.600” Wide, Plastic Dual Inline Package (PDIP) 44Q 44 Lead, Plastic Gull Wing Quad Flatpack (PQFP)SYM BOL DESCRIPTIONBYTESADDRESSBIT ADDRESS, SYMBOLACC Accumulator E0H E7 E6 E5 E4 E E2 E1 E0ACC.7 ACC.6 ACC.5 ACC.4 ACC.3 ACC.2 ACC.1 ACC.0B* Bregister F0H F7 F6 F5 F4 F3 F2 F1 F0B.7 B.6 B.5 B.4 B.3 B.2 B.1 B.0DPH DataPointer High83HDPL DataPointer Low82HIE InterruptEnable A8H AF –- –- AC AB AA A9 A8EA ES ET1 EX1 ET0EX0IP* InterruptPriority B8H –- –- –- BC BB BA B9 B8–- –- –- PS PT1 PX1 PT0PX0P0* Port 0 80H 87 86 85 84 83 82 81 80P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0 P1* Port 1 90H 97 96 95 94 93 92 91 90P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0 P2* Port 2 A0H A7 A6 A5 A4 A3 A2 A1 A0P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0 P3* Port 3 B0H B7 B6 B5 B4 B3 B2 B1 B0P3.7 P3.6 P3.5 P3.4 P3.3 P3.2 P3.1 P3.0PCON PowerControl 87H 8D –- –- –- –- –- –- –- SMODPSW* ProgramStatusWord D0H D7 D6 D5 D4 D3 D2 D1 D0 CY AC F0 RS1 RS0 OV –- PSBUF SerialDataBuffer99HSCON * SerialControl98H 9F 9E 9D 9C 9B 9A 99 98 SM0 SM1 SM2 REN TB8 RB8 TI RISP StackPointer81HTCON * TimerControlControl88H 8F 8E 8D 8C 8B 8A 89 88 TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0TH0 TimerHigh 08CHTH1 TimerHigh 18DH TL0 Timer 8AH* SFRs are bit addressable. – Reserved bits.. Reset value depends on reset source.Low 0 TL1 Timer Low 1 8BHTMO DTimer Mode89HGATE C/^T M1 M0 GATE C/^T M1 M0译文：描述AT89C51是美国ATMEL公司生产的低电压，高性能CMOS8位单片机，片内含4Kbytes的快速可擦写的只读程序存储器（PEROM）和128 bytes 的随机存取数据存储器（RAM），器件采用ATMEL公司的高密度、非易失性存储技术生产，兼容标准MCS-51产品指令系统，片内置通用8位中央处理器（CPU）和flish存储单元，功能强大AT89C51单片机可为您提供许多高性价比的应用场合，可灵活应用于各种控制领域。

自动化专业单片机相关外文文献英文文献外文翻译中英对照

使用本科生毕业论文V外文翻译）译文名称：MCS -51系列单片机地功能和结构专业：自动化班次：学员：指导教员：评阅人：完成时间：2018年11月30日Structure and function of the MCS-51 seriesStructure and function of the MCS-51 series one-chip computer is a name of a piece of on e-chip computer series which In tel Compa ny produces. This compa ny in troduced 8 top-grade on e-chip computers of MCS-51 series in 1980 after introducing 8 one-chip computers of MCS-48 series in 1976. It belong to a lot of kinds this line of on e-chip computer the chips have,such as 8051,8031, 8751, 80C51BH, 80C31BH,etc., their basic composition, basic performance and in structi on system are all the same. 8051 daily represe ntatives-51 serial on e-chip computers b5E2RGbCAPAn one-chip computer system is made up of several following parts: ( 1> One microprocessor of 8 (CPU>. ( 2> At slice data memory RAM (128B/256B>,it use not depositting not can reading /data that write, such as result not middle of operati on, final result and data wan ted to show, etc. ( 3> Procedure memory ROM/EPROM (4KB/8KB >, is used to preserve the procedure , some initial data and form in slice. But does not take ROM/EPROM within some on e-chip computers, such as 8031 , 8032, 80C ,etc.. (4> Four 8 run side by side I/O in terface P0 four P3, each mouth can use as introduction , may use as exporting too. ( 5> Two timer / counter, each timer / coun ter may set up and count in the way, used to count to the exter nal in cide nt, can set up into a timing way too, and can according to count or result of timing realize the control of the computer. ( 6> Five cut off cutting off the control system of the source . ( 7> One all duplexing serial I/O mouth of UART (uni versal asynchronous receiver/tra nsmitter (UART> >, is it realize on e-chip computer or on e-chip computer and serial com muni catio n of computer to use for. ( 8> Stretch oscillator and clock produce circuit, quartz crystal finely tune electric capacity n eed outer. Allow oscillati on freque ncy as 12 megahertas now at most. Every the above-me nti oned part was joined through the in side data bus .Among them, CPU is a core of the one-chip computer, it is the control of the computer and comma nd cen tre, made up of such parts as arithmeticunit and使用controller , etc.. The arithmetic unit can carry on 8 persons of arithmetic operation and unit ALU of logic operation while including one, the 1 storing device temporarilies of 8, stori ng device 2 temporarily, 8's accumulatio n device ACC, register B and procedure stateregister PSW, etc. Pers on who accumulate ACC count by 2 in put ends en tered of check ing etc. temporarily as one operation often, come from person who store 1 operation is it is it make operation to go on to count temporarily , operation result and loopback ACC withanother one. In addition, ACC is often regarded as the transfer station of data tran smissi on on 8051 in side . The same as gen eral microprocessor, it is the busiest register. Help rememberi ng that agree ing with A expresses in the order. The con troller in cludes the procedure coun ter , the order is depositted, the order decipher, the oscillator and timing circuit, etc. The procedure counter is made up of coun ter of 8 for two, amounts to 16. Itis a byte address coun ter of the procedure in fact, the content is the next IA that will carried out in PC. The content which cha nges it can cha nge the directi on that the procedure carries out . Shake the circuit in 8051 one-chip computers, only need outer quartz crystal and freque ncy to fin ely tune the electric capacity, its freque ncy range is its12MHZ of 1.2MHZ. This pulse signal, as 8051 basic beats of working, namely the minimum unit of time. 8051 is the same as other computers, the work in harmony under the control of the basic beat, just like an orchestra accord ing to the beat play that is comma nded&nqFDPw There are ROM (procedure memory , can only read > and RAM in 8051 slices (data memory, can is it can write > two to read, they have each in depe ndent memory address space, dispose way to be the same with gen eral memory of computer. Procedure 8051 memory and 8751 slice procedure memory capacity 4KB, address begin from 0000H, used for preserving the procedure and form con sta nt. Data 8051- 8751 8031 of memory data memory 128B, address false 00FH, use for middle result to deposit operation, the data are stored temporarily and the data are buffered etc.. In RAM of this 128B,使用there is unit of 32 byteses that can be appo in ted as the job register, this and gen eral microprocessor is differe nt, 8051 slice RAM and job register rank one formation the same to arrange the location. It is not very the same that the memory of MCS-51 series one-chip computer and general computer disposes the way in additi on. Gen eral computer for first address space, ROM and RAM can arrange in differe nt space with in the range of this address at will, n amely the addresses of ROM and RAM, with distributing different address space ina formation. While visiting the memory, corresponding and only an address Memory unit, canROM, it can be RAM too, and by visiting the order similarly. This kind of memory structure is called the structure of Princeton. 8051 memories are divided into procedure memory space and data memory space on the physics structure, there are four memory spaces in all: The procedure stores in one and data memory space outside data memory and one in procedure memory space and one outside one, the structure forms of this kind of procedure device and data memory separated form data memory, called Harvard structure. But use the an gle from users, 8051 memory address space is divided into three kin ds: (1> In the slice, arrange blocks of FFFFH , 0000H of locati on , in unison outside the slice (use 16 addresses>. (2> The data memory address space outside one of 64KB, the address is arran ged from 0000H 64KB FFFFH (with 16 addresses> too to the location. (3> Data memory address space of 256B (use 8 addresses>. Three above-mentioned memory space addresses overlap, for distinguishing and designing the order symbol of different data transmission in the instruction system of 8051: CPU visit slice, ROM order spend MOVC , visit block RAM order uses MOVX outside the slice, RAM order uses MOV to visit in slice. DXDiTa9E3d8051 one-chip computer have four 8 walk abreast I/O port, call P0, P1, P2 and P3. Each port is 8 accurate two-way mouths, accounts for 32 pins altogether. Every one I/O line can be used as introduction and exported in depe nden tly. Each port in cludes a latch (n amely special fun cti on register >,使用one exports the driver and a introduction buffer . Make data can latch when outputting, data can buffer when making introduction , but four function of passway these self-same. Expa nd among the system of memory outside hav ing slice, four port these may serve as accurate two-way mouth of I/O in com mon use. Expand among the system of memory outside having slice, P2 mouth see high 8 address off= P0 mouth is a two-way bus, send the in troduct ion of 8 low addresses and data / export in timesharingr crpuDGiTThe circuit of 8051 on e-chip computers and four I/O ports is very ingenious in design. Familiar with I/O port logical circuit, not only help to use ports correctly and rati on ally, and will in spire to desig ning the peripheral logical circuit of on e-chip computer to some exte nt. Load ability and in terface of port have certa in requireme nt, because output grade, P0 of mouth and P1 end output, P3 of mouth grade differe nt at structure, so,the load ability and in terface of its door dema nd to have nothing in com mon with each other. P0 mouth is differe nt from other mouths, its output grade draws the resistance supremly. When using it as the mouth in com mon use to use, output grade is it leak circuit to turn on, is it is it urge NMOS draw the resistance on taking to be outer with it while in putt ing to go out to fail. When being used as in troductio n, should write "1" to a latch first. Every one with P0 mouth can drive 8 Model LS TTL load to export. P1 mouth is an accurate two-way mouth too, used as I/O in com mon use. Different from P0 mouth output of circuit its, draw load resistance link with power on in side have. In fact, the resista nce is that two effects are in charge of FET and together: One FET is in charge of load, its resistance is regular. Another one can is it lead to work with close at two state, make its Preside nt resista nce value cha nge approximate 0 or group value heavy two situation very. When it is 0 that the resistance is approximate , can draw the pin to the high level fast。

外文翻译---51系列单片机的结构和功能

外文翻译---51系列单片机的结构和功能外文资料翻译英文原文：Structure and function of the MCS-51 series Structure and function of the MCS-51 series one-chip computer MCS-51 is a name of a piece of one-chip computer series which Intel Company produces. This company introduced 8 top-grade one-chip computers of MCS-51 series in 1980 after introducing 8 one-chip computers of MCS-48 series in 1976. It belong to a lot of kinds this line of one-chip computer the chips have such as 8051, 8031, 8751, 80C51BH, 80C31BH,etc., their basic composition, basic performance and instruction system are all the same. 8051 daily representatives- 51 serial one-chip computers .An one-chip computer system is made up of several following parts: (1) One microprocessor of 8 (CPU). (2) At slice data memory RAM (128B/256B),it use not depositing not can reading /data that write, such as result not middle of operation, final result and data wanted to show, etc. (3) Procedure memory ROM/EPROM (4KB/8KB ), is used to preserve the procedure , some initial data and form in slice. But does not take ROM/EPROM within some one-chip computers, such as 8031 , 8032, 80C ,etc.. (4) Four 8 run side by side I/O interface P0 four P3, each mouth can use as introduction, may use as exporting too. (5) Two timer / counter, each timer / counter may set up and count in the way, used to count to the external incident, can set up into a timing way too, and can according to count or result of timing realize the control of the computer. (6) Five cut off cutting off the control (universal asynchronous receiver/transmitter (UART) ), is it realize one-chip computer or one-chip computer and serial communication of computer to use for. (8) Stretch oscillator and clock produce circuit, quartz crystal finely tune electric capacity need outer. Allow oscillation frequency as 12 megahertz now at most. Every the above-mentioned part was joined through the inside data bus .Among them, CPU is a core of the one-chip computer, it is the control of the computer and command center, made up of such parts as arithmetic unit and controller , etc.. The arithmetic unit can carry on 8 persons of arithmetic operation and unit ALU of logic operation while including one, the 1 storing devices temporarily of 8, storing device 2 temporarily, 8's accumulation device ACC, register B and procedure state register PSW, etc. Person who accumulate ACC count by 2 input ends entered of checking etc. temporarily as one operation often, come from person who store 1 operation is it is it make operation to go on to count temporarily , operation result and loop back ACC with another one. In addition, ACC is often regarded as the transfer station of data transmission on 8051 inside. The same as general microprocessor, it is the busiest register. Help remembering that agreeing with a expresses in the order. The controller includes the procedure counter, the order is deposited, theorder decipher , the oscillator and timing circuit, etc. The procedure counter is made up of counter of 8 for two, amounts to 16. It is a byte address counter of the procedure in fact, the content is the next IA that will carried out in PC. The content which changes it can change the direction that the procedure carries out. Shake the circuit in 8051 one-chip computers, only need outer quartz crystal and frequency to finely tune the electric capacity, its frequency range is its 12MHZ of 1.2MHZ. This pulse signal, as 8051 basic beats of working, namely the minimum unit of time. 8051 is the same as other computers, the work in harmony under the control of the basic beat, just like an orchestra according to the beat play that is commanded.There are ROM (procedure memory , can only read) and RAM in 8051 slices (data memory, can is it can write) two to read, they have each independent memory address space, dispose way to be the same with general memory of computer. Procedure 8051 memory and 8751 slice procedure memory capacity 4KB, address begin from 0000H, used for preserving the procedure and form constant. Data 8051- 8751 8031 of memory data memory 128B, address false 00FH, use for middle result to deposit operation, the data are stored temporarily and the data are buffered etc.. In RAM of this 128B, there is unit of 32 bytes that can be appointed as the job register, this and general microprocessor is different, 8051 slice RAM and job register rank one formation the same to arrange the location. It is not very the same that the memory of MCS-51 series one-chip computer and general computer disposes the way in addition. General computer for first address space, ROM and RAM can arrange in different space within the range of this address at will, namely the addresses of ROM and RAM, with distributing different address space in a formation. While visiting the memory, corresponding and only an address Memory unit, can ROM, it can be RAM too, and by visiting the order similarly. This kind of memory structure is called the structure of Princeton. 8051 memories are divided into procedure memory space and data memory space on the physics structure, there are four memory spaces in all: The procedure stores in one and data memory space outside data memory and one in procedure memory space and one outside one, the structure forms of this kind of procedure device and data memory separated form data memory, called Harvard structure. But use the angle from users, 8051 memory address space is divided into three kinds: (1) In the slice, arrange blocks of FFFFH, 0000H of location, in unison outside the slice (use 16 addresses). (2) The data memory address space outside one of 64KB, the address is arranged from 0000H 64KB FFFFH (with 16 addresses) too to the location. (3) Data memory address space of 256B (use 8 addresses). Three above-mentioned memory space addresses overlap, for distinguishing and designing the order symbol of different data transmission in the instruction system of 8051: CPU visit slice, ROM order spend MOVC , visit block RAM order uses MOVX outside the slice, RAM order uses MOV to visit in slice.8051 one-chip computer have four 8 walk abreast I/O port, call P0, P1, P2 and P3. Each port is 8 accurate two-way mouths, accounts for 32 pins altogether.Every one I/O line can be used as introduction and exported independently. Each port includes a latch (namely special function register), one exports the driver and a introduction buffer. Make data can latch when outputting, data can buffer when making introduction , but four function of way these self-same. Expand among the system of memory outside having slice, four ports these may serve as accurate two-way mouth of I/O in common use. Expand among the system of memory outside having slice, P2 mouth see high 8 address off; P0 mouth is a two-way bus, send the introduction of 8 low addresses and data / export in timesharingOutput grade, P3 of mouth, P1 of P1, connect with inside have load resistance of drawing, every one of they can drive 4 Model LS TTL load to output. As while inputting the mouth, any TTL or NMOS circuit can drive P1 of 8051 one-chip computers as P3 mouth in a normal way. Because draw resistance on output grade of them have, can open a way collector too or drain-source resistance is it urge to open a way, do not need to have the resistance of drawing auto. Mouths are all accurate two-way mouths too. When the conduct is input, must write the corresponding port latch with 1 first. As to 80C51 one-chip computer, port can only offer millimeter of output electric currents, is it output mouth go when urging one ordinary basing of transistor to regard as, should contact a resistance among the port and transistor base, in order to the electricity while restraining the high level from exporting P1~P3 Being restored to the throne is the operation of initializing of an one-chip computer. Its main function is to turn PC into 0000H initially, make the one-chip computer begin to hold the conduct procedure from unit 0000H. Except that the ones that enter the system are initialized normally, as because procedure operate it make mistakes or operate there aren't mistake, in order to extricate oneself from a predicament , need to be pressed and restored to the throne the key restarting too. It is an input end which is restored to the throne the signal in 8051 China RST pin. Restore to the throne signal high level effective, should sustain 24 shake cycle (namely 2 machine cycles) the above its effective times. If 6 of frequency of utilization brilliant to shake, restore to the throne signal duration should exceed 4 delicate to finish restoring to the throne and operating. Produce the logic picture of circuit which is restored to the throne the signal:Restore to the throne the circuit and include two parts outside in the chip entirely. Outside that circuit produce to restore to the throne signal (RST) hand over to Schmitt's trigger, restore to the throne circuit sample to output, Schmitt of trigger constantly in each S5P2, machine of cycle in having one more, then just got and restored to the throne and operated the necessary signal inside. Restore to the throne resistance of circuit generally, electric capacity parameter suitable for 6 brilliant to shake, can is it restore to the throne signal high level duration greater than 2 machine cycles to guarantee. Being restored to the throne in the circuit is simple, its function is very important. Pieces of one-chip computer system could normal running, should first check it can restore to the throne not succeeding. Checking and can pop one's head and monitor the pin with theoscillograph tentatively, push and is restored to the throne the key, the wave form that observes and has enough range is exported (instantaneous), can also through is it restore to the throne circuit group holding value carry on the experiment to change.中文译文：51系列单片机的结构和功能51系列单片机是英特尔公司生产的具有一定结构和功能的单片机产品。

51单片机中的英文缩写全称(整理)

51单片机中的英文缩写全称(整理) 51单片机中的英文缩写全称(整理)单片机（Microcontroller）是一种集成了处理器、内存、输入/输出设备以及时钟等功能的微型计算机系统。

在单片机领域中，英文缩写广泛应用，方便人们对各种电子元器件、芯片和技术进行简洁明了的表达。

本文将整理51单片机中常见的英文缩写全称，方便读者了解和使用。

一、基本概念与组成1. MCU - Microcontroller Unit（单片机单元）：指一种完整、独立的微型计算机系统，由中央处理器（CPU）、内存（RAM、ROM）、输入/输出（I/O）接口和时钟等组件组成。

2. CPU - Central Processing Unit（中央处理器）：执行单片机数据处理、逻辑控制和运算等核心功能的部件。

3. RAM - Random Access Memory（随机存取存储器）：用于临时存储程序和数据的存储器，读写速度快但容量较小。

4. ROM - Read-Only Memory（只读存储器）：存储固定程序和数据，无法进行写操作。

5. I/O - Input/Output（输入/输出）：与单片机外部设备进行数据交互的接口。

6. Clock - 时钟：提供单片机工作所需的时序信号，控制指令执行和数据传输的节奏。

二、核心技术与模块1. ISP - In-System Programming（系统编程）：通过特定的下载器将程序和数据下载到单片机内部，实现在线编程。

2. UART - Universal Asynchronous Receiver/Transmitter（通用异步收发器）：用于实现串行通信的接口。

3. ADC - Analog-to-Digital Converter（模数转换器）：将模拟信号转换为相应的数字量。

4. PWM - Pulse Width Modulation（脉宽调制）：通过改变信号的脉宽来控制电气或电子设备的输出功率。

(完整word版)51单片机外文翻译

Structure and function of the MCS-51 seriesStructure and function of the MCS—51 series one-chip computer is a name of a piece of one-chip computer series which Intel Company produces。

This company introduced 8 top—grade one-chip computers of MCS-51 series in 1980 after introducing 8 one-chip computers of MCS—48 series in 1976. It belong to a lot of kinds this line of one—chip computer the chips have,such as 8051， 8031， 8751,80C51BH， 80C31BH,etc。

， their basic composition, basic performance and instruction system are all the same。

8051 daily representatives- 51 serial one—chip computers .An one-chip computer system is made up of several following parts：（ 1) One microprocessor of 8 （CPU)。

（ 2） At slice data memory RAM （128B/256B),it use not depositting not can reading /data that write, such as result not middle of operation, final result and data wanted to show， etc。

电子科学与技术外文翻译外文文献英文文献 51系列单片机的结构和功能

外文出处：Structure and function of(用外文写)the MCS-51 series附件2：外文原文Structure and function of the MCS-51 series Structure and function of the MCS-51 series one-chip computer MCS-51 is a name of a piece of one-chip computer series which Intel Company produces. This company introduced 8 top-grade one-chip computers of MCS-51 series in 1980 after introducing 8 one-chip computers of MCS-48 series in 1976. It belong to a lot of kinds this line of one-chip computer the chips have,such as 8051, 8031, 8751, 80C51BH, 80C31BH,etc., their basic composition, basic performance and instruction system are all the same. 8051 daily representatives- 51 serial one-chip computers .Early MCU 8-bit or all of the four. One of the most successful is the INTEL 8031, because the performance of a simple and reliable access to a lot of good praise. Then developed in 8031 out of MCS51 MCU Systems. SCM systems based on this system until now is still widely used. With the increased requirements of industrial control field, began a 16-bit microcontroller, because the cost is not satisfactory but have not been very widely used. After 90 years with the great development of consumer electronics, microcontroller technology has been a huge increase. With INTEL i960 series, especially the later series of widely used ARM, 32-bit microcontroller quickly replace high-end 16-bit MCU status and enter the mainstream market. The traditional 8-bit microcontroller performance have been the rapid increase capacity increase compared to 80 the number of times. Currently, high-end 32-bit microcontroller clocked over 300MHz, the performance catching the mid-90's dedicated processor, while the average model prices fall to one U.S. dollars, the most high-end [1] model only 10 dollars.Modern SCM systems are no longer only in the development and use of bare metal environment, a large number of proprietary embedded operating system is widely used in the full range of SCM. The handheld computers and cell phones as the core processing of high-end microcontroller can even use a dedicated Windows andLinux operating systems.More than a dedicated MCU processor suitable for embedded systems, so it was up to the application. In fact the number of SCM is the world's largest computer. Modern human life used in almost every piece of electronic and mechanical products will be integrated single chip.Phone, telephone, calculator, home appliances, electronic toys, handheld computers and computer accessories such as a mouse with a 1-2 in both the Department of SCM. Personal computer will have a large number of SCM in the work. General car with more than 40 SCM, complex industrial control systems may even have hundreds of SCM in the same time work! SCM is not only far exceeds the number of PC and other computing the sum, or even more than the number of human beings.An one-chip computer system is made up of several following parts: ( 1) One microprocessor of 8 (CPU). ( 2) At slice data memory RAM (128B/256B),it use not depositting not can reading /data that write, such as result not middle of operation, final result and data wanted to show, etc. ( 3) Procedure memory ROM/EPROM (4KB/8KB ), is used to preserve the procedure , some initial data and form in slice. But does not take ROM/EPROM within some one-chip computers, such as 8031 , 8032, 80C ,etc.. ( 4) Four 8 run side by side I/O interface P0 four P3, each mouth can use as introduction , may use as exporting too. ( 5) Two timer / counter, each timer / counter may set up and count in the way, used to count to the external incident, can set up into a timing way too, and can according to count or result of timing realize the control of the computer. ( 6) Five cut off cutting off the control system of the source . ( 7) One all duplexing serial I/O mouth of UART (universal asynchronous receiver/transmitter (UART) ), is it realize one-chip computer or one-chip computer and serial communication of computer to use for. ( 8) Stretch oscillator and clock produce circuit, quartz crystal finely tune electric capacity need outer. Allow oscillation frequency as 12 megahertas now at most. Every the above-mentioned part was joined through the inside data bus .Among them, CPU is a core of the one-chip computer, it is the control of the computer and command centre, made up of such parts as arithmetic unit and controller , etc.. The arithmetic unit can carry on 8 persons of arithmetic operation and unit ALU of logic operation while including one, the 1 storing device temporarilies of 8, storing device 2 temporarily, 8's accumulation device ACC, register B and procedure state register PSW, etc. Person who accumulate ACC count by 2 input ends entered ofchecking etc. temporarily as one operation often, come from person who store 1 operation is it is it make operation to go on to count temporarily , operation result and loopback ACC with another one. In addition, ACC is often regarded as the transfer station of data transmission on 8051 inside . The same as general microprocessor, it is the busiest register. Help remembering that agreeing with A expresses in the order. The controller includes the procedure counter , the order is depositted, the order decipher, the oscillator and timing circuit, etc. The procedure counter is made up of counter of 8 for two, amounts to 16. It is a byte address counter of the procedure in fact, the content is the next IA that will carried out in PC. The content which changes it can change the direction that the procedure carries out . Shake the circuit in 8051 one-chip computers, only need outer quartz crystal and frequency to finely tune the electric capacity, its frequency range is its 12MHZ of 1.2MHZ. This pulse signal, as 8051 basic beats of working, namely the minimum unit of time. 8051 is the same as other computers, the work in harmony under the control of the basic beat, just like an orchestra according to the beat play that is commanded.There are ROM (procedure memory , can only read ) and RAM in 8051 slices (data memory, can is it can write ) two to read, they have each independent memory address space, dispose way to be the same with general memory of computer. Procedure 8051 memory and 8751 slice procedure memory capacity 4KB, address begin from 0000H, used for preserving the procedure and form constant. Data 8051- 8751 8031 of memory data memory 128B, address false 00FH, use for middle result to deposit operation, the data are stored temporarily and the data are buffered etc.. In RAM of this 128B, there is unit of 32 byteses that can be appointed as the job register, this and general microprocessor is different, 8051 slice RAM and job register rank one formation the same to arrange the location. It is not very the same that the memory of MCS-51 series one-chip computer and general computer disposes the way in addition. General computer for first address space, ROM and RAM can arrange in different space within the range of this address at will, namely the addresses of ROM and RAM, with distributing different address space in a formation. While visiting the memory, corresponding and only an address Memory unit, can ROM, it can be RAM too, and by visiting the order similarly. This kind of memory structure is called the structure of Princeton. 8051 memories are divided into procedure memory space and data memory space on the physics structure, there are four memory spaces in all: The procedurestores in one and data memory space outside data memory and one in procedure memory space and one outside one, the structure forms of this kind of procedure device and data memory separated form data memory, called Harvard structure. But use the angle from users, 8051 memory address space is divided into three kinds: (1) In the slice, arrange blocks of FFFFH , 0000H of location , in unison outside the slice (use 16 addresses). (2) The data memory address space outside one of 64KB, the address is arranged from 0000H 64KB FFFFH (with 16 addresses ) too to the location. (3) Data memory address space of 256B (use 8 addresses). Three above-mentioned memory space addresses overlap, for distinguishing and designing the order symbol of different data transmission in the instruction system of 8051: CPU visit slice, ROM order spend MOVC , visit block RAM order uses MOVX outside the slice, RAM order uses MOV to visit in slice.8051 one-chip computer have four 8 walk abreast I/O port, call P0, P1, P2 and P3. Each port is 8 accurate two-way mouths, accounts for 32 pins altogether. Every one I/O line can be used as introduction and exported independently. Each port includes a latch (namely special function register ), one exports the driver and a introduction buffer . Make data can latch when outputting, data can buffer when making introduction , but four function of passway these self-same. Expand among the system of memory outside having slice, four port these may serve as accurate two-way mouth of I/O in common use. Expand among the system of memory outside having slice, P2 mouth see high 8 address off; P0 mouth is a two-way bus, send the introduction of 8 low addresses and data / export in timesharingOutput grade , P3 of mouth , P1 of P1 , connect with inside have load resistance of drawing , every one of they can drive 4 Model LS TTL load to output. As while inputting the mouth, any TTL or NMOS circuit can drive P1 of 8051 one-chip computers as P3 mouth in a normal way . Because draw resistance on output grade of them have, can open a way collector too or drain-source resistance is it urge to open a way, do not need to have the resistance of drawing outerly . Mouths are all accurate two-way mouths too. When the conduct is input, must write the corresponding port latch with 1 first . As to 80C51 one-chip computer, port can only offer milliampere of output electric currents, is it output mouth go when urging one ordinary basing of transistor to regard as, should contact a resistance among the port and transistor base , in order to the electricity while restraining the high level from exporting P1~P3 Beingrestored to the throne is the operation of initializing of an one-chip computer. Its main function is to turn PC into 0000H initially , make the one-chip computer begin to hold the conduct procedure from unit 0000H. Except that the ones that enter the system are initialized normally,as because procedure operate it make mistakes or operate there aren't mistake, in order to extricate oneself from a predicament , need to be pressed and restored to the throne the key restarting too. It is an input end which is restored to the throne the signal in 8051 China RST pin. Restore to the throne signal high level effective , should sustain 24 shake cycle (namely 2 machine cycles ) the above its effective times. If 6 of frequency of utilization brilliant to shake, restore to the throne signal duration should exceed 4 delicate to finish restoring to the throne and operating. Produce the logic picture of circuit which is restored to the throne the signal: Restore to the throne the circuit and include two parts outside in the chip entirely. Outside that circuit produce to restore to the throne signal (RST ) hand over to Schmitt's trigger, restore to the throne circuit sample to output , Schmitt of trigger constantly in each S5P2 , machine of cycle in having one more , then just got and restored to the throne and operated the necessary signal insidly. Restore to the throne resistance of circuit generally, electric capacity parameter suitable for 6 brilliant to shake, can is it restore to the throne signal high level duration greater than 2 machine cycles to guarantee. Being restored to the throne in the circuit is simple, its function is very important. Pieces of one-chip computer system could normal running,should first check it can restore to the throne not succeeding. Checking and can pop one's head and monitor the pin with the oscillograph tentatively, push and is restored to the throne the key, the wave form that observes and has enough range is exported (instantaneous), can also through is it restore to the throne circuit group holding value carry on the experiment to change.附件1：外文资料翻译译文51系列单片机的结构和功能51系列单片机是英特尔公司生产的具有一定结构和功能的单片机产品。

51单片机缩写的英文全称及中文名称

单片机缩写的英文全称及中文名称PC = programmer counter //程序计数器counter 计算器, 计数器, 计算者, 柜台, 筹码['kauntə]ACC = accumulate [ə'kju:mjuleit //累加器: 积累: 积聚PSW = programmer status word //程序状态字status'steitəs, 'stæ-]n. 地位；状态；情形；重要身分SP = stack point //堆栈指针stack[stæk n. 堆；堆叠vt. 使堆叠；把…堆积起来vi. 堆积，堆叠DPTR = data point register //数据指针寄存器'redʒistə寄存器IP = interrupt priority //中断优先级[,intə'rʌpt 中断[prai'ɔrəti] 优先；优先权；[数] 优先次序；优先考虑的事IE = interrupt enable // 中断使能i'neibl]使能够，使成为可能；授予权利或方法TMOD = timer mode // 定时器方式(定时器/计数器控制寄存器) ['taimə定时器，计时器mode [məud模式，方式ALE = alter (变更,可能是)['ɔ:ltə]PSEN = programmer saving enable //程序存储器使能(选择外部程序存储器的意思) EA = enable all(允许所有中断)完整应该是enable all interruptPROG = programme (程序)SFR = special funtion register //特殊功能寄存器TCON = timer control //定时器控制PCON = power control //电源控制MSB = most significant bit//最高有效位[sig'nifikənt有效的；有意义的LSB = last significant bit//最低有效位CY = carry //进位（标志）['kæri]AC = assistant carry //辅助进位[ə'sistənt n. 助手，助理，助教adj. 辅助的，助理的；有帮助的OV = overflow //溢出[,əuvə'fləu, 'əuvəfləu ORG = originally[ə'ridʒənəli //起始来源DB = define [di'fain]定义byte [bait] //字节定义EQU = equal //等于['i:kwəl]DW = define word //字定义 E = enable //使能OE = output enable //输出使能RD = read //读WR = write //写中断部分：INT0 = interrupt 0 //中断0 INT1 = interrupt 1//中断1T0 = timer 0 //定时器0 T1 = timer 1 //定时器1TF1 = timer1 flag //定时器1 标志(其实是定时器1中断标志位) [flæɡvi. 标记；衰退；枯萎vt. 标记；插旗n. 标志；旗子IE1 = interrupt exterior //(外部中断请求,可能是) ik'stiəriə]外部的IT1 = interrupt touch //(外部中断触发方式,可能是)ES = enable serial //串行使能['siəriəl, 'si:r- adj. 连续的；连载的；分期偿还的n. 电视连续剧；[图情] 期刊；连载小说serial communication [计]串行通信serial port [计]串行端口；序列埠serial interface [计]串联接口ET = enable timer //定时器使能PS = priority serial //串口优先级EX = enable exterior //外部使能(中断)[ik'stiəriə] adj. 外部的；表面的；外在的n. 外部；表面；外型；外貌PX = priority exterior //外部中断优先级PT = priority timer //定时器优先级寄存器部分:SFR:special funtion register //特殊功能寄存器(片内RAM 80H~FFH)ACC:accumulate //累加器SP:stack point //堆栈指针PSW:programmer status word //程序状态字IE:interrupt enable // 中断使能DPL,DPH:DPTR(data point register //数据指针寄存器)的低8位和高8位IP:interrupt priority //中断优先级PCON:power control //电源控制SCON:serial control //串行口控制TCON:timer control //定时器控制SBUF:serial buffer //串行数据缓冲['bʌfə] n. [计] 缓冲区；缓冲器，[车辆] 减震器vt. 缓冲TMOD:timer mode //定时器方式PSW:CY:carry (psw.7) //进位（标志）AC:auxiliary carry (psw.6) //辅助进位F0: (psw.5) //用户自定义标志位OV:overflow (psw.2) //溢出RS1,RS0:register select (psw.4,psw.3)//工作寄存器组选择位[si'lekt]挑选P:parity (psw.0) //奇偶校验位['pæriti. 平价；同等；相等IE:EA:Enable All Interrupt /CPU开/关中断控制位ET1:Enable Timer //定时器2溢出中断允许位ES:Enable Serial Port //串行口中断允许位EX:Enable External //外部中断1的中断允许位IP:PS:Priority Serial //串口优先级PT:Priority Timer //定时器优先级PX:Priority External //外部中断优先级[ik'stə:nəl] adj. 外部的；表面的；[药] 外用的；外国的；外面的n. 外部；外观；外面SCON:RI:Receive Interrupt //串行口接收中断请求标志位TI:Transmit Interrupt //串行口发送中断请求标志位[trænz'mit, træns-, trɑ:n-] vt. 传输；传播；发射；传达；遗传vi. 传输；发射信号TCON:TF1:Timer1 Overflow Flag //定时器1溢出中断请求标志TR1:Timer1 Run //定时器1启动控制位IE1:Interrupt Edge //外部中断1请求标志位[edʒ]IT1:Interrupt Type //外部中断1触发方式选择位8051引脚:RST:RESET (9)//复位，重启P3:RXD:Received eXchange [iks'tʃeindʒ Data (10,p3.0)//接收串行数据eXchange n. 交换；交流；交易所；兑换vt. 交换；交易；兑换vi. 交换；交易；兑换TXD:Transmit eXchange Data (11,p3.1)//发送串行数据INT0:interrupt 0 (12,p3.2)//中断0 INT1:interrupt 1 (13,p3.3)//中断1T0:timer 0 (14,p3.4)//定时器0 T1:timer 1 (15,p3.5)//定时器1RD：ReaD (16,p3.6)//外部数据存储器(RAM)的读信号WR：WRite (17,p3.7)//外部数据存储器(RAM)的写信号XTAL2,XTAL1:External Crystal ['kristəl晶体Oscillator ['ɔsileitə振荡器(18,19) //外部晶体振荡器PSEN:Program Store [stɔ:]Enable (29) //程序存储器(ROM)使能n. 商店；储备，贮藏；仓库vt. 贮藏，储存ALE:Address Latch Enable (30) //地址锁存Latch锁存器EA：External Address Enable (31) //外部程序存储器(ROM)地址允许其它：OE:output enable //输出使能MSB = most significant bit//最高有效位[sig'nifikənt] adj. 重大的；有效的；有意义的；值得注意的；意味深长的n. 象征；有意义的事物LSB = last significant bit//最低有效位DB = define byte //字节定义ORG = originally //起始来源EQU = equal //等于DW = define word //字定义CLKOUT：Clock out,时钟输出BUSWDITH：总线宽度Vref：参考电压（带ADC的单片机中有的）参考电压（Voltage Reference）['refərəns n. 参考，参照；HSO：High Speed Output，高速输出HSI：High Speed Input：高速输入INST：Instruction，指令READY就绪，总线中的就绪信号或引脚NMI：No Mask Interruput （Input）：不可屏蔽的中断请求（输入）[mɑ:sk, mæskBHE：Bank High Enable：存储器的高位允许，如在80286系统中RAM的组织为16位的，分为高8位和低8位数据，分别的控制信号为BHE和BLE Bank n. 银行；岸；浅滩；储库vt. 将…存入银行；倾斜转弯vi. 堆积；倾斜转弯MCS-51指令（1）数据传送类指令（7种助记符）助记符英文注释功能MOV Move 对内部数据寄存器RAM和特殊功能寄存器SFR的数据进行传送MOVC Move Code 读取程序存储器数据表格的数据传送MOVX Move External RAM 对外部RAM的数据传送XCH Exchange 字节交换XCHD Exchange low-order Digit ['didʒit]低半字节交换POP Pop from Stack) 出栈PUSH Push onto ['ɔntu, -tə] Stack) 入栈（2）算术运算类指令（8种助记符）ADD Addition 加法ADDC Add with Carry 带进位加法SUBB Subtract [səb'trækt] with Borrow 带借位减法vt. 减去；扣DA Decimal ['desiməl]adj. 小数的；十进位的n. 小数Adjust [ə'dʒʌst]调整十进制调整INC Increment ['inkrimənt加1 DEC Decrement 'dekrimənt]减1MUL Multiplication、Multiply 乘法[,mʌltipli'keiʃən n. [数] 乘法；增加['mʌltiplai vt. 乘；使增加；使繁殖；使相乘vi. 乘；繁殖；增加adv. 多样地；复合地adj. 多层的；多样的DIV Division[di'viʒən n. [数] 除法；部门；分割；师（军队）；赛区、Divide 除法di'vaid vt. 划分；除；分开；使产生分歧vi. 分开；意见分歧n. [地理] 分水岭，分水线(3)逻辑运算类指令（10种助记符）ANL And Logic 逻辑与'lɔdʒik] n. 逻辑；逻辑学；逻辑性adj. 逻辑的ORL OR Logic 逻辑或CLR Clear kliə]清零XRL Exclusive-OR Logic 逻辑异或[ik'sklu:siv] adj. 独有的；排外的；专一的n. 独家新闻；独家经营的项目；排外者CPL Complement 取反'kɔmplimənt] n. 补语；余角；补足物vt. 补足，补助RL Rotate left 循环左移[rəu'teit, 'rəut-, 'rəuteit vi.旋转；循环vt. 使旋转；使转动；使轮流adj. [植] 辐状的RLC Rotate Left throught the Carry flag 带进位循环左移RR Rotate Right 循环右移RRC Rotate Right throught the Carry flag 带进位循环右移SWAP Swap 低4位与高4位交换[swɔp, swɔ:p n. 交换；交换之物vt. 与...交换；以...作交换vi. 交换；交易(4)控制转移类指令（17种助记符）ACALL Absolute subroutine Call 子程序绝对调用'æbsəlju:t, ,æbsə'lju:t adj. 绝对的；完全的；专制的n. 绝对；绝对事物'sʌbru:,ti:n, ,sʌbru:'ti:n] n. [计] 子程序LCALL Long subroutine Call 子程序长调用RET Return from subroutine 子程序返回RETI Return from Interruption 中断返回SJMP Short Jump 短转移JMP Jump Indirect 间接跳越[,indi'rekt, -dai-] adj. 间接的；迂回的；非直截了当的AJMP Absolute Jump 绝对转移LJMP Long Jump 长转移CJNE Compare and Jump if Not Equal 比较不相等则转移kəm'pεə] vt. 比较；对照；比喻为vi. 比较；相比n. 比较DJNZ Decrement and Jump if Not Zero 减１后不为０则转移JZ Jump if Zero 结果为０则转移JNZ Jump if Not Zero 结果不为０则转移JC Jump if the Carry flag is set 有进位则转移JNC Jump if Not Carry 无进位则转移JB Jump if the Bit is set) B位为１则转移JNB Jump if the Bit is Not set B位为０则转移JBC Jump if the Bit is set and Clear the bit 位为１则转移，并清除该位NOP No Operation 空操作[,ɔpə'reiʃən] n. 操作；经营；[外科] 手术；[数][计] 运算（5）位操作指令（1种助记符）SETB Set Bit 置位伪指令助记符英文注释功能ORG OriginDB Define ByteDW Define WordEQU EqualDATA DataXDATA External DataBIT BitEND End51外部引脚缩写英文解释中文解释RST （9）Reset 复位信号引脚[,ri:'set, 'ri:set vi. 重置；清零vt. 重置；重新设定；重新组合n. 重新设定；重新组合；重排版RxD (10--P3.0) Receive Data 串口接收端TxD (11--P3.1) Transmit Data 串口发送端INT0(————) （12--P3.2）Interrupt0 外部中断0信号输入引脚INT1(————) （13--P3.3）Interrupt1 外部中断1信号输入引脚T0 (14--P3.4) Timer0 定时/计数器0输入信号引脚T1 (15--P3.5) Timer1 定时/计数器1输入信号引脚LSB = last significant bit//最低有效位significant [sig'nifikənt有效的WR(———) (16--P3.6) write写信号引脚RD(———) (17--P3.7) read 读信号引脚PSEN(—————) （29）programmer saving enable 外部程序存储器读选通信号ALE （30）Address Latch Enable 地址锁存允许信号EA(———) (31) enable 外部ROM选择信号51内部寄存器SFR special funtion register 特殊功能寄存器ACC accumulate 累加器A PSW programmer status word 程序状态字CY (PSW.7) carry 进位标志位AC (PSW.6) assistant carry 辅助进位标志位ə'sistənt] n. 助手，助理，助教adj. 辅助的，助理的；有帮助的OE = output enable //输出使能OV (PSW.2) overflow 溢出标志位[,əuvə'fləu, 'əuvəfləu]PC programmer counter 程序计数器DPTR data point register 数据指针寄存器SP stack point 堆栈指针TCON timer control 定时器控制寄存器TF1（TCON.7）Timer1 flag T1中断标志位TR1（TCON.6）Timer1 Run T1运行控制位TF0 （TCON.5）Timer0 flag T0中断标志位TR0 （TCON.4）Timer0 Run T0运行控制位IE1 （TCON.3） Interrupt1 exterior 外部中断1中断标志位ik'stiəriə adj. 外部的；表面的；外在的n. 外部；表面；外型；外貌MSB = most significant bit//最高有效位IT1 （TCON.2）Interrupt1 touch 外部中断1 触发方式选择位IE0 （TCON.1）Interrupt0 exterior 外部中断0中断标志位IT0 （TCON.0）Interrupt0 touch 0-电平触发1-下降沿触发IE （A8H）interrupt enable 中断允许寄存器EA (IE.7) enable all interrupt 中断总允许位ES (IE.4) enable serial 串行口中断允许位['siəriəl, 'si:r-] adj. 连续的；连载的；分期偿还的n.电视连续剧；[图情] 期刊；连载小说ET0 （IE.1）enable timer 0 T0中断允许位ET1（IE.3）enable timer 1 T1中断允许位EX1 （IE.2）enable exterior 1 外部中断1中断允许位EX0 （IE.0）enable exterior 0 外部中断0中断允许位IP （B8H）interrupt priority 中断优先级寄存器PS (IP.4) priority serial 串口优先级标志位PT1 (IP.3) priority timer 1 定时器1优先级标志位PX1 (IP.2) priority exterior 1 外部中断1优先级标志位PT0 (IP.1) priority timer 0 定时器0优先级标志位PX0 (IP.0) priority exterior 0 外部中断0优先级标志位PCON (87H) power control 电源控制和波特率选择TMOD （89H）timer mode 定时器方式控制寄存器。

MCS-51系列单片机中英文资料对照外文翻译文献综述教学文稿

精品文档MCS-51系列单片机中英文资料对照外文翻译文献综述Structure and function of the MCS-51 seriesStructure and function of the MCS-51 series one-chip computer MCS-51 is a name of a piece of one-chip computer series which Intel Company produces. This company introduced 8 top-grade one-chip computers of MCS-51 series in 1980 after introducing 8 one-chip computers of MCS-48 series in 1976. It belong to a lot of kinds this line of one-chip computer the chips have, such as 8051, 8031, 8751, 80C51BH, 80C31BH,etc., their basic composition, basic performance and instruction system are all the same.8051 daily representatives-51 serial one-chip computers.A one-chip computer system is made up of several following parts: (1) One microprocessor of 8 (CPU). ( 2) At slice data memory RAM (128B/256B),it use not depositing not can reading /data that write, such as result not middle of operation, final result and data wanted to show, etc. (3)Procedure memory ROM/EPROM (4KB/8KB ), is used to preserve the procedure , some initial data and form in slice. But does not take ROM/EPROM within some one-chip computers, such as 8031, 8032.(4) Four 8 run side by side I/O interface P0 four P3, each mouth can use as introduction , may use as exporting too. (5) Two timer / counter, each timer / counter may set up and count in the way, used to count to the external incident, can set up into a timing way too, and can according to count or result of timing realize the control of the computer. (6) Five cut off cutting off the control system of the source. (7) One all duplex serial I/O mouth of UART (universal asynchronous receiver/transmitter (UART) ), is it realize one-chip computer or one-chip computer and serial communication of computer to use for. (8) Stretch oscillator and clock produce circuit, quartz crystal finely tune electric capacity need outer. Allow oscillation frequency as 12 megahertz now at most. Every the above-mentioned part was joined through the inside data bus .Among them, CPU is a core of the one-chip computer, it is the control of the computer and command centre, made up of such parts as arithmetic unit and controller , etc.. The arithmetic unit can carry on 8 persons of arithmetic operation and unit ALU of logic operation while including one, the 1 storing device temporaries of 8, storing device 2 temporarily, 8's accumulation device ACC, register B and procedure state register PSW, etc. Person who accumulate ACC count by 2 input ends entered of checking etc. temporarily as one operation often, come from person who store 1 operation is it is it make operation to go on to counttemporarily , operation result and loop back ACC with another one. In addition, ACC is often regarded as the transfer station of data transmission on 8051 inside. The same as general microprocessor, it is the busiest register. Help remembering that agreeing with a express in the order. The controller includes the procedure counter, the order is deposited, the order deciphering, the oscillator and timing circuit, etc. The procedure counter is made up of counter of 8 for two, amounts to 16. It is a byte address counter of the procedure in fact, the content is the next IA that will carried out in PC. The content which changes it can change the direction that the procedure carries out. Shake the circuit in 8051 one-chip computers, only need outer quartz crystal and frequency to finely tune the electric capacity, its frequency range is its 12MHZ of 1.2MHZ. This pulse signal, as 8051 basic beats of working, namely the minimum unit of time. 8051 is the same as other computers, the work in harmony under the control of the basic beat, just like an orchestra according to the beat play that is commanded.There are ROM (procedure memory , can only read ) and RAM in 8051 slices (data memory, can is it can write ) two to read, they have each independent memory address space, dispose way to be the same with general memory of computer. Procedure 8051 memory and 8751 slice procedure memory capacity 4KB, address begin from 0000H, used for preserving the procedure and form constant. Data 8051- 8751 8031 of memory data memory 128B, address false 00FH, using for middle result to deposit operation, the data are stored temporarily and the data are buffered. In RAMof this 128B, there is unit of 32 bytes that can be appointed as the job register, this and general microprocessor is different, 8051 slice RAM and job register rank one formation the same to arrange the location. It is not very the same that the memory of MCS-51 series one-chip computer and general computer disposes the way in addition. General computer for first address space, ROM and RAM can arrange in different space within the range of this address at will, namely the addresses of ROM and RAM, with distributing different address space in a formation. While visiting the memory, corresponding and only an address Memory unit, can ROM, it can be RAM too, and by visiting the order similarly. This kind of memory structure is called the structure of Princeton. 8051 memories are divided into procedure memory space and data memory space on the physics structure, there are four memory spaces in all: The procedure stores in one and data memory space outside data memory and one in procedure memory space and one outside one, the structure forms of this kind of procedure device and data memory separated form data memory, called Harvard structure. But use the angle from users, 8051 memory address space is divided into three kinds: (1) In the slice, arrange blocks of FFFFH, 0000H of location, in unison outside the slice (use 16 addresses). (2) The data memory address space outside one of 64KB, the address is arranged from 0000H 64KB FFFFH (with 16 addresses) too to the location. (3) Data memory address space of 256B (use 8 addresses). Three above-mentioned memory space addresses overlap, for distinguishing and designing the order symbol of different datatransmission in the instruction system of 8051: CPU visit slice, ROM order spend MOVC , visit block RAM order uses MOVX outside the slice, RAM order uses MOV to visit in slice.8051 one-chip computer have four 8 walk abreast I/O ports, call P0, P1, P2 and P3. Each port is 8 accurate two-way mouths, accounts for 32 pins altogether. Every one I/O line can be used as introduction and exported independently. Each port includes a latch (namely special function register), one exports the driver and a introduction buffer. Make data can latch when outputting, data can buffer when making introduction, but four function of pass away these self-same. Expand among the system of memory outside having slice, four ports these may serve as accurate two-way mouth of I/O in common use. Expand among the system of memory outside having slice, P2 mouth see high 8 address off; P0 mouth is a two-way bus, send the introduction of 8 low addresses and data / export in timesharing The circuit of 8051 one-chip computers and four I/O ports is very ingenious in design. Familiar with I/O port logical circuit, not only help to use port correctly and rationally, and will inspire to designing the peripheral logical circuit of one-chip computer to some extent. Load ability and interface of port have certain requirement, because output grade, P0 of mouth and P1 end output, P3 of mouth grade different at structure, so, the load ability and interface of its door demand to have nothing in common with each other. P0 mouth is different from other mouth, its output grade draws the resistance supremely. When using it as the mouth in common use,output grade is it leak circuit to turn on, is it urge NMOS draw the resistance on taking to be outer with it while inputting to go out to fail. When being used as introduction, should write"1" to a latch first. Every one with P0 mouth can drive 8 Model LS TTL load to export. P1 mouth is an accurate two-way mouth too, used as I/O in common use. Different from P0 mouth output of circuit its, draw load resistance link with power on inside have. In fact, the resistance is that two effects are in charge of FET and together: One FET is in charge of load, its resistance is regular. Another one can is it lead to work with close at two state, make its President resistance value change approximate 0 or group value heavy two situation very. When it is 0 that the resistance is approximate, can draw the pin to the high level fast; when resistance value is very large, P1 mouth high electricity at ordinary times, can is it draw electric current load to offer outwards, draw electric current load to offer outwards, draw the resistance on needn't answer and thinking. Here when the port is used as introduction, must write into 1 to the corresponding latch first too, make FET end relatively about 20,000 ohms because of load resistance in scene and because 40,000 ohms, will not exert an influence on the data that are input. The structure of P2 some mouth is similar to P0 mouth, there are MUX switches. Is it similar to mouth partly to urge, but mouth large a conversion controls some than P1.P3 mouth one multi-functional port, mouth getting many than P1 it have "3 doors and 4 buffers". Two parts there, make her besides accurate two-way function with P1 mouth just, can also use the second function of every pin, "and" door 3functions one switch in fact, it determines to be to output data of latch to output second signal of function. Act as W=At 1 o'clock, output Q end signal; act as Q=At 1 o'clock, can output W line signal. At the time of programming, it is that the first function is still the second function but needn't have software that set up P3 mouth in advance .It hardware not inside is the automatic to have two function outputted when CPU carries on SFR and seeks the location to visit to P3 mouth/at not lasting lining, there are inside hardware latch Qs=1. The operation principle of P3 mouth is similar to P1 mouth.Output grade, P3 of mouth, P1 of P1, connect with inside have load resistance of drawing, every one of they can drive 4 Model LS TTL load to output. As while inputting the mouth, any TTL or NMOS circuit can drive P1 of 8051 one-chip computers as P3 mouth in a normal way. Because draw resistance on output grade of them have, can open a way collector too or drain-source resistance is it urge to open a way, do not need to have the resistance of drawing outer. Mouths are all accurate two-way mouths too. When the conduct is input, must write the corresponding port latch with 1 first. As to 80C51 one-chip computer, port can only offer milliampere of output electric currents, is it output mouth go when urging one ordinary basing of transistor to regard as, should contact a resistance among the port and transistor base, in order to the electricity while restraining the high level from exporting P1~P3 Being restored to the throne is the operation of initializing of an one-chip computer. Its main function is to turn PC into0000H initially, make the one-chip computer begin to hold the conduct procedure from unit 0000H. Except that the ones that enter the system are initialized normally, as because procedure operate it make mistakes or operate there aren't mistake, in order to extricate oneself from a predicament , need to be pressed and restored to the throne the key restarting too. It is an input end which is restored to the throne the signal in 8051 China RST pin. Restore to the throne signal high level effective, should sustain 24 shake cycle (namely 2 machine cycles) the above its effective times. If 6 of frequency of utilization brilliant to shake, restore to the throne signal duration should exceed 4 delicate to finish restoring to the throne and operating. Produce the logic picture of circuit which is restored to the throne the signal: restore to the throne the circuit and include two parts outside in the chip entirely. Outside that circuit produce to restore to the throne signal (RST) hand over to Schmitt's trigger, restore to the throne circuit sample to output , Schmitt of trigger constantly in each S5P2 , machine of cycle in having one more , then just got and restored to the throne and operated the necessary signal inside. Restore to the throne resistance of circuit generally, electric capacity parameter suitable for 6 brilliant to shake, can is it restore to the throne signal high level duration greater than 2 machine cycles to guarantee. Being restored to the throne in the circuit is simple, its function is very important. Pieces of one-chip computer system could normal running, should first check it can restore to the throne not succeeding. Checking and can pop one's head and monitor the pin with the oscilloscope tentatively,push and is restored to the throne the key, the wave form that observes and has enough range is exported (instantaneous), can also through is it restore to the throne circuit group holding value carry on the experiment to change.MCS-51系列单片机的功能和结构MSC-51系列单片机具有一个单芯片电脑的结构和功能，它是英特尔公司的系列产品的名称。

系列单片机中英文资料对照外文翻译文献综述

MCS-51系列单片机中英文资料对照外文翻译文献综述Structure and function of the MCS-51 seriesStructure and function of the MCS-51 series one-chip computer MCS-51 is a name of a piece of one-chip computer series which Intel Company produces. This company introduced 8 top-grade one-chip computers of MCS-51 series in 1980 after introducing 8 one-chip computers of MCS-48 series in 1976. It belong to a lot of kinds this line of one-chip computer the chips have, such as 8051, 8031, 8751, 80C51BH, 80C31BH,etc., their basic composition, basic performance and instruction system are all the same.8051 daily representatives-51 serial one-chip computers.A one-chip computer system is made up of several following parts: (1) One microprocessor of 8 (CPU). ( 2) At slice data memory RAM (128B/256B),it use not depositing not can reading /data that write, such as result not middle of operation, final result and data wanted to show, etc. (3)Procedure memory ROM/EPROM (4KB/8KB ), is used to preserve the procedure , some initial data and form in slice. But does not take ROM/EPROM within some one-chip computers, such as 8031, 8032.(4) Four 8 run side by side I/O interface P0 four P3, each mouth can use as introduction , may use as exporting too. (5) Two timer / counter, each timer / counter may set up and count in the way, used to count to the external incident, can set up into a timing way too, and can according to count or result of timing realize the control of the computer. (6) Five cut off cutting off the control system of the source. (7) One all duplex serial I/O mouth of UART (universal asynchronous receiver/transmitter (UART) ), is it realize one-chip computer or one-chip computer and serial communication of computer to use for. (8) Stretch oscillator and clock produce circuit, quartz crystal finely tune electric capacity need outer. Allow oscillation frequency as 12 megahertz now at most. Every the above-mentioned part was joined through the inside data bus .Among them, CPU is a core of the one-chip computer, it is the control of the computer and command centre, made up of such parts as arithmetic unit and controller , etc.. The arithmetic unit can carry on 8 persons of arithmetic operation and unit ALU of logic operation while including one, the 1 storing device temporaries of 8, storing device 2 temporarily, 8's accumulation device ACC, register B and procedure state register PSW, etc. Person who accumulate ACC count by 2 input ends entered of checking etc. temporarily as one operation often, come from person who store 1 operation is it is it make operation to go on to counttemporarily , operation result and loop back ACC with another one. In addition, ACC is often regarded as the transfer station of data transmission on 8051 inside. The same as general microprocessor, it is the busiest register. Help remembering that agreeing with a express in the order. The controller includes the procedure counter, the order is deposited, the order deciphering, the oscillator and timing circuit, etc. The procedure counter is made up of counter of 8 for two, amounts to 16. It is a byte address counter of the procedure in fact, the content is the next IA that will carried out in PC. The content which changes it can change the direction that the procedure carries out. Shake the circuit in 8051 one-chip computers, only need outer quartz crystal and frequency to finely tune the electric capacity, its frequency range is its 12MHZ of 1.2MHZ. This pulse signal, as 8051 basic beats of working, namely the minimum unit of time. 8051 is the same as other computers, the work in harmony under the control of the basic beat, just like an orchestra according to the beat play that is commanded.There are ROM (procedure memory , can only read ) and RAM in 8051 slices (data memory, can is it can write ) two to read, they have each independent memory address space, dispose way to be the same with general memory of computer. Procedure 8051 memory and 8751 slice procedure memory capacity 4KB, address begin from 0000H, used for preserving the procedure and form constant. Data 8051- 8751 8031 of memory data memory 128B, address false 00FH, using for middle result to deposit operation, the data are stored temporarily and the data are buffered. In RAMof this 128B, there is unit of 32 bytes that can be appointed as the job register, this and general microprocessor is different, 8051 slice RAM and job register rank one formation the same to arrange the location. It is not very the same that the memory of MCS-51 series one-chip computer and general computer disposes the way in addition. General computer for first address space, ROM and RAM can arrange in different space within the range of this address at will, namely the addresses of ROM and RAM, with distributing different address space in a formation. While visiting the memory, corresponding and only an address Memory unit, can ROM, it can be RAM too, and by visiting the order similarly. This kind of memory structure is called the structure of Princeton. 8051 memories are divided into procedure memory space and data memory space on the physics structure, there are four memory spaces in all: The procedure stores in one and data memory space outside data memory and one in procedure memory space and one outside one, the structure forms of this kind of procedure device and data memory separated form data memory, called Harvard structure. But use the angle from users, 8051 memory address space is divided into three kinds: (1) In the slice, arrange blocks of FFFFH, 0000H of location, in unison outside the slice (use 16 addresses). (2) The data memory address space outside one of 64KB, the address is arranged from 0000H 64KB FFFFH (with 16 addresses) too to the location. (3) Data memory address space of 256B (use 8 addresses). Three above-mentioned memory space addresses overlap, for distinguishing and designing the order symbol of different datatransmission in the instruction system of 8051: CPU visit slice, ROM order spend MOVC , visit block RAM order uses MOVX outside the slice, RAM order uses MOV to visit in slice.8051 one-chip computer have four 8 walk abreast I/O ports, call P0, P1, P2 and P3. Each port is 8 accurate two-way mouths, accounts for 32 pins altogether. Every one I/O line can be used as introduction and exported independently. Each port includes a latch (namely special function register), one exports the driver and a introduction buffer. Make data can latch when outputting, data can buffer when making introduction, but four function of pass away these self-same. Expand among the system of memory outside having slice, four ports these may serve as accurate two-way mouth of I/O in common use. Expand among the system of memory outside having slice, P2 mouth see high 8 address off; P0 mouth is a two-way bus, send the introduction of 8 low addresses and data / export in timesharing The circuit of 8051 one-chip computers and four I/O ports is very ingenious in design. Familiar with I/O port logical circuit, not only help to use port correctly and rationally, and will inspire to designing the peripheral logical circuit of one-chip computer to some extent. Load ability and interface of port have certain requirement, because output grade, P0 of mouth and P1 end output, P3 of mouth grade different at structure, so, the load ability and interface of its door demand to have nothing in common with each other. P0 mouth is different from other mouth, its output grade draws the resistance supremely. When using it as the mouth in common use,output grade is it leak circuit to turn on, is it urge NMOS draw the resistance on taking to be outer with it while inputting to go out to fail. When being used as introduction, should write"1" to a latch first. Every one with P0 mouth can drive 8 Model LS TTL load to export. P1 mouth is an accurate two-way mouth too, used as I/O in common use. Different from P0 mouth output of circuit its, draw load resistance link with power on inside have. In fact, the resistance is that two effects are in charge of FET and together: One FET is in charge of load, its resistance is regular. Another one can is it lead to work with close at two state, make its President resistance value change approximate 0 or group value heavy two situation very. When it is 0 that the resistance is approximate, can draw the pin to the high level fast; when resistance value is very large, P1 mouth high electricity at ordinary times, can is it draw electric current load to offer outwards, draw electric current load to offer outwards, draw the resistance on needn't answer and thinking. Here when the port is used as introduction, must write into 1 to the corresponding latch first too, make FET end relatively about 20,000 ohms because of load resistance in scene and because 40,000 ohms, will not exert an influence on the data that are input. The structure of P2 some mouth is similar to P0 mouth, there are MUX switches. Is it similar to mouth partly to urge, but mouth large a conversion controls some than P1.P3 mouth one multi-functional port, mouth getting many than P1 it have "3 doors and 4 buffers". Two parts there, make her besides accurate two-way function with P1 mouth just, can also use the second function of every pin, "and" door 3functions one switch in fact, it determines to be to output data of latch to output second signal of function. Act as W=At 1 o'clock, output Q end signal; act as Q=At 1 o'clock, can output W line signal. At the time of programming, it is that the first function is still the second function but needn't have software that set up P3 mouth in advance .It hardware not inside is the automatic to have two function outputted when CPU carries on SFR and seeks the location to visit to P3 mouth/at not lasting lining, there are inside hardware latch Qs=1. The operation principle of P3 mouth is similar to P1 mouth.Output grade, P3 of mouth, P1 of P1, connect with inside have load resistance of drawing, every one of they can drive 4 Model LS TTL load to output. As while inputting the mouth, any TTL or NMOS circuit can drive P1 of 8051 one-chip computers as P3 mouth in a normal way. Because draw resistance on output grade of them have, can open a way collector too or drain-source resistance is it urge to open a way, do not need to have the resistance of drawing outer. Mouths are all accurate two-way mouths too. When the conduct is input, must write the corresponding port latch with 1 first. As to 80C51 one-chip computer, port can only offer milliampere of output electric currents, is it output mouth go when urging one ordinary basing of transistor to regard as, should contact a resistance among the port and transistor base, in order to the electricity while restraining the high level from exporting P1~P3 Being restored to the throne is the operation of initializing of an one-chip computer. Its main function is to turn PC into0000H initially, make the one-chip computer begin to hold the conduct procedure from unit 0000H. Except that the ones that enter the system are initialized normally, as because procedure operate it make mistakes or operate there aren't mistake, in order to extricate oneself from a predicament , need to be pressed and restored to the throne the key restarting too. It is an input end which is restored to the throne the signal in 8051 China RST pin. Restore to the throne signal high level effective, should sustain 24 shake cycle (namely 2 machine cycles) the above its effective times. If 6 of frequency of utilization brilliant to shake, restore to the throne signal duration should exceed 4 delicate to finish restoring to the throne and operating. Produce the logic picture of circuit which is restored to the throne the signal: restore to the throne the circuit and include two parts outside in the chip entirely. Outside that circuit produce to restore to the throne signal (RST) hand over to Schmitt's trigger, restore to the throne circuit sample to output , Schmitt of trigger constantly in each S5P2 , machine of cycle in having one more , then just got and restored to the throne and operated the necessary signal inside. Restore to the throne resistance of circuit generally, electric capacity parameter suitable for 6 brilliant to shake, can is it restore to the throne signal high level duration greater than 2 machine cycles to guarantee. Being restored to the throne in the circuit is simple, its function is very important. Pieces of one-chip computer system could normal running, should first check it can restore to the throne not succeeding. Checking and can pop one's head and monitor the pin with the oscilloscope tentatively,push and is restored to the throne the key, the wave form that observes and has enough range is exported (instantaneous), can also through is it restore to the throne circuit group holding value carry on the experiment to change.MCS-51系列单片机的功能和结构MSC-51系列单片机具有一个单芯片电脑的结构和功能，它是英特尔公司的系列产品的名称。

51单片机中英对照(详细)

51单片机专用寄存器中英文对照SFR Special Function Registers 专用寄存器、特殊功能寄存器Acc Accmulator 累加器PSW Program Status Word 程序状态字CY Carry 进位；AC Acid Carry 辅助进位；F0 Flag 标志（旗帜）0RS1 Register 1 寄存器（控制位）1；OV Over 溢出；P Parity 奇偶标志SP Stack Pointer 堆栈指针DPTR Data Pointer 数据指针P0~P3 Port 0~3 端口0~3SBUF Serial Data Buffer 串行数据缓冲器TH0 Timer High 定时器（计数初值）高8位TL0 Timer Low 定时器（计数初值）低8位TMOD Timer Mode 定时器模式GATE 门；M1M0 Mode 1、2 模式（方式）控制；TCON Timer Control 定时器控制TF Timer Flag 定时器（溢出）标志；TR Timer Run 定时器运行；IE Interrupt Enable 中断允许；IT Interrupt Trigger 中断触发SCON Serial Control 串行口控制SM Serial Mode 串行模式；REN Receive Enable （串行）接收允许；TB8 Transfer Bit 8 发送的第8位；RB8 Receive Bit 8 接收的第8位TI Transfer Interrupt 传送中断； RI Receive Interrupt 接收中断PCON Power Control 电源控制IE Interrupt Enable 中断允许EA Enable All 总允许；ES Enable Serial 允许串行（中断）；ET1 Enable Timer 1 允许定时器1（中断）；EX1 Enable eXternal 允许外部（中断）1IP Interrupt Priority 中断优先级PC Program Counter 程序计数器51单片机引脚中英文对照AD0~AD7 Address and Data 地址/数据线ALE Address Latch Enable 地址锁存允许PSEN Program （Memroy）Store Enable 程序（存储器）选通允许RST Reset 复位TXD Transmitted eXternal Data 外部数据输出线RXD Receive eXternal Data 外部数据输入线INT0 Interrupt 0 外中断0INT1 Interrupt 1 外中断1T0 Timer 0 定时器/计数器（输入端）0T1 Timer 1 定时器/计数器（输入端）1WR Wright 写（控制）RD Read 读（控制）EA External Access （Enable）外部存储器（允许）汇编语言助记符中英文对照direct 直接rel Relation 相对MOV Move 传送（移动）MOVX Move eXternal 外部传送MOVC Move Code 代码传送PUSH 推入（入栈）POP 弹出（出栈）XCH eXCHange 交换XCHD eXCHange Digit 低半字节交换SWAP 交换ADD Addition 加ADDC Addition with Carry 带进位位加SUBB Sub with Borrow带借位位减MUL Multiply 乘DIV Divide 除INC Incrememt 增量DEC Decrement 减量DA A Deicmal Adjusment 十进制调整ANL And Logic 与逻辑ORL OR Logic 或逻辑XRL 异或逻辑RL Rolate Left 循环左移RLC Rolate Left with Carry 带进位位循环左移RR Rolate Right 循环右移RRC Rolate Right with Carry 带进位位循环右移CPL Complement 取反（求补）CLR Clear 清除（零）LJMP Long Jump 长跳转AJMP Absolute Jump 绝对跳转SJMP Short Jump 短跳转JZ Jump if Acc equal Zero 如果ACC等于0，跳转JNZ Jump if Acc Not equal Zero 如果ACC不等于0，跳转CJNE Compare and Jump if Not Equal 比较，不等则转DJNZ Decrement and Jump if Not Zero 减1不等于零则转LCALL Long Call 长调用ACALL Absolute Call 绝对调用RET Return 返回RETI Return from Interrupt 中断返回NOP No Operation 空操作SETB Set Bit 置位JC Jump if Carry 如果CY=1，跳转JNC Jump if No Carry 如果CY不等于1（即等于0），跳转JB Jump if Bit 如果位等于1，跳转JNB Jump if No Bit 如果位不等于1（即等于0），跳转JBC Jump if Bit and Clear 如果位等于1，跳转并清0其他B Binary 二进制D Decimal 十进制H Hex 十六进制BCD Binary Coded Decimal 二进制编码十进制ASCII American Code for Information Interchange 信息内部交换美国码ROM Read Only Memrory 只读存储器PROM Programmable Read Only Memory 可编程序只读存储器EPROM Erasable Programmable Read Only Memory 可擦写可编程序只读存储器EEPROM Electrically Erasable Programmable Read Only Memory 电可擦写可编程序只读存储器RAM Random Access Memory 随机存储器SRAM Static Random Access Memory 静态随机存储器DRAM Dynamic RAM 动态随机存储器Flash Memory 闪烁存储器OE Out Enable 输出允许WE Wright Enable 写允许CE Chip Enable 芯片允许CS Chip Select 芯片选择KEY 键DISPLAY 显示D/A Digit to Analog 数/模转换A/D Analog to Digit 模/数转换CLK Clock 时钟ASYNC Asynchronous Data Communication 异步通信Baud rate 波特率UART Universal Asynchronous Receiver/Transmitter 异步接收/发送器51外部引脚缩写英文解释中文解释RST （9）Reset 复位信号引脚RxD (10--P3.0) Receive Data 串口接收端TxD (11--P3.1) Transmit Data 串口发送端INT0 （12--P3.2）Interrupt0 外部中断0信号输入引脚INT1 （13--P3.3）Interrupt1 外部中断1信号输入引脚T0 (14--P3.4) Timer0 定时/计数器0输入信号引脚T1 (15--P3.5) Timer1 定时/计数器1输入信号引脚WR (16--P3.6) write 写信号引脚RD (17--P3.7) read 读信号引脚PSEN （29）progammer saving enable 外部程序存储器读选通信号ALE （30）Address Latch Enable 地址锁存允许信号EA (31) enable 外部ROM选择信号51内部寄存器SFR special funtion register 特殊功能寄存器ACC accumulate 累加器APSW progammer status word 程序状态字CY (PSW.7) carry 进位标志位AC (PSW.6) assistant carry 辅助进位标志位OV (PSW.2) overflow 溢出标志位PC progammer counter 程序计数器DPTR data point register 数据指针寄存器SP stack point 堆栈指针TCON timer control 定时器控制寄存器TF1 （TCON.7）Timer1 flag T1中断标志位TR1 （TCON.6）Timer1 Run T1运行控制位TF0 （TCON.5）Timer0 flag T0中断标志位TR0 （TCON.4）Timer0 Run T0运行控制位IE1 （TCON.3）Interrupt1 exterior 外部中断1中断标志位IT1 （TCON.2）Interrupt1 touch 外部中断1 触发方式选择位IE0 （TCON.1）Interrupt0 exterior 外部中断0中断标志位IT0 （TCON.0）Interrupt0 touch 0-电平触发1-下降沿触发IE （A8H）interrupt enable 中断允许寄存器EA (IE.7) enable all interrupt 中断总允许位ES (IE.4) enable serial 串行口中断允许位ET1 （IE.3）enable timer 1 T1中断允许位EX1 （IE.2）enable exterior 1 外部中断1中断允许位ET0 （IE.1）enable timer 0 T0中断允许位EX0 （IE.0）enable exterior 0 外部中断0中断允许位IP （B8H）interrupt priority 中断优先级寄存器PS (IP.4) priority serial 串口优先级标志位PT1 (IP.3) priority timer 1 定时器1优先级标志位PX1 (IP.2) priority exterior 1 外部中断1优先级标志位PT0 (IP.1) priority timer 0 定时器0优先级标志位PX0 (IP.0) priority exterior 0 外部中断0优先级标志位PCON (87H) power control 电源控制和波特率选择TMOD （89H）timer mode 定时器方式控制寄存器MSB = most significant bit/ /最高有效位LSB = last significant bit/ /最低有效位OE = output enable / / 输出使。

51单片机缩写的英文全称及中文名称

单片机缩写的英文全称及中文名称PC = programmer counter 地位；状态；情形；重要身分SP = stack point 堆；堆叠 vt. 使堆叠；把…堆积起来 vi. 堆积，堆叠DPTR = data point register 助手，助理，助教adj. 辅助的，助理的；有帮助的OV = overflow 标记；衰退；枯萎vt. 标记；插旗n. 标志；旗子IE1 = interrupt exterior 连续的；连载的；分期偿还的n. 电视连续剧；[图情] 期刊；连载小说serial communication [计]串行通信serial port [计]串行端口；序列埠serial interface [计]串联接口ET = enable timer 外部的；表面的；外在的n. 外部；表面；外型；外貌PX = priority exterior [计] 缓冲区；缓冲器，[车辆] 减震器vt. 缓冲TMOD:timer mode 平价；同等；相等IE:EA:Enable All Interrupt /CPU开/关中断控制位 ET1:Enable Timer 外部的；表面的；[药] 外用的；外国的；外面的n. 外部；外观；外面SCON:RI:Receive Interrupt 传输；传播；发射；传达；遗传vi. 传输；发射信号TCON:TF1:Timer1 Overflow Flag 交换；交流；交易所；兑换vt. 交换；交易；兑换vi. 交换；交易；兑换TXD:Transmit eXchange Data (11,商店；储备，贮藏；仓库vt. 贮藏，储存ALE:Address Latch Enable (30) 重大的；有效的；有意义的；值得注意的；意味深长的n. 象征；有意义的事物LSB = last significant bit参考，参照；HSO：High Speed Output，高速输出 HSI：High Speed Input：高速输入INST：Instruction，指令 READY就绪，总线中的就绪信号或引脚NMI：No Mask Interruput （Input）：不可屏蔽的中断请求（输入）[mɑ:sk, mæskBHE：Bank High Enable：存储器的高位允许，如在80286系统中RAM的组织为16位的，分为高8位和低8位数据，分别的控制信号为BHE和BLE Bank n. 银行；岸；浅滩；储库vt. 将…存入银行；倾斜转弯vi. 堆积；倾斜转弯MCS-51指令（1）数据传送类指令（7种助记符）助记符英文注释功能MOV Move 对内部数据寄存器RAM和特殊功能寄存器SFR的数据进行传送MOVC Move Code 读取程序存储器数据表格的数据传送MOVX Move External RAM 对外部RAM的数据传送XCH Exchange 字节交换XCHD Exchange low-order Digit ['didʒit]低半字节交换POP Pop from Stack) 出栈 PUSH Push onto ['ɔntu, -tə] Stack) 入栈（2）算术运算类指令（8种助记符）ADD Addition 加法 ADDC Add withCarry 带进位加法SUBB Subtract [səb'trækt] with Borrow 带借位减法vt. 减去；扣DA Decimal ['desiməl]adj. 小数的；十进位的n. 小数Adjust [ə'dʒʌst]调整十进制调整INC Increment ['inkrimənt加1DEC Decrement 'dekrimənt]减1MUL Multiplication、Multiply 乘法[,mʌltipli'keiʃən n. [数] 乘法；增加['mʌltiplai vt. 乘；使增加；使繁殖；使相乘vi. 乘；繁殖；增加adv. 多样地；复合地adj. 多层的；多样的DIV Division[di'viʒən n. [数] 除法；部门；分割；师（军队）；赛区、Divide 除法di'vaid vt. 划分；除；分开；使产生分歧vi. 分开；意见分歧n. [地理] 分水岭，分水线(3)逻辑运算类指令（10种助记符）ANL And Logic 逻辑与'lɔdʒik] n. 逻辑；逻辑学；逻辑性adj. 逻辑的ORL OR Logic 逻辑或CLR Clear kliə]清零XRL Exclusive-OR Logic 逻辑异或[ik'sklu:siv] adj. 独有的；排外的；专一的n. 独家新闻；独家经营的项目；排外者CPL Complement 取反'kɔmplimənt] n. 补语；余角；补足物vt. 补足，补助RL Rotate left 循环左移[rəu'teit, 'rəut-, 'rəuteit vi. 旋转；循环vt. 使旋转；使转动；使轮流adj. [植] 辐状的RLC Rotate Left throught the Carry flag 带进位循环左移RR Rotate Right 循环右移RRC Rotate Right throught the Carry flag 带进位循环右移SWAP Swap 低4位与高4位交换[swɔp, swɔ:p n. 交换；交换之物vt. 与...交换；以...作交换vi. 交换；交易(4)控制转移类指令（17种助记符）ACALL Absolute subroutine Call 子程序绝对调用'æbsəlju:t, ,æbsə'lju:t adj. 绝对的；完全的；专制的n. 绝对；绝对事物'sʌbru:,ti:n, ,sʌbru:'ti:n] n. [计] 子程序LCALL Long subroutineCall 子程序长调用 RET Return from subroutine 子程序返回RETI Return from Interruption 中断返回SJMP Short Jump 短转移JMP Jump Indirect 间接跳越[,indi'rekt, -dai-] adj. 间接的；迂回的；非直截了当的AJMP Absolute Jump 绝对转移 LJMP Long Jump 长转移CJNE Compare and Jump if Not Equal 比较不相等则转移kəm'pεə] vt. 比较；对照；比喻为vi. 比较；相比n. 比较DJNZ Decrement and Jump if Not Zero 减１后不为０则转移JZ Jump if Zero 结果为０则转移 JNZ Jump if NotZero 结果不为０则转移JC Jump if the Carry flag is set 有进位则转移JNC Jump if Not Carry 无进位则转移JB Jump if the Bit is set) B位为１则转移JNB Jump if the Bit is Not set B位为０则转移JBC Jump if the Bit is set and Clear the bit 位为１则转移，并清除该位NOP No Operation 空操作[,ɔpə'reiʃən] n. 操作；经营；[外科] 手术；[数][计] 运算（5）位操作指令（1种助记符）SETB Set Bit 置位伪指令助记符英文注释功能ORG OriginDB Define ByteDW Define WordEQU EqualDATA DataXDATA External DataBIT BitEND End51外部引脚缩写英文解释中文解释RST （9） Reset 复位信号引脚[,ri:'set, 'ri:set vi. 重置；清零vt. 重置；重新设定；重新组合n. 重新设定；重新组合；重排版RxD Receive Data 串口接收端TxD Transmit Data 串口发送端INT0(————) （）Interrupt0 外部中断0信号输入引脚INT1(————) （）Interrupt1 外部中断1信号输入引脚T0 Timer0 定时/计数器0输入信号引脚T1 Timer1 定时/计数器1输入信号引脚LSB = last significant bit助手，助理，助教adj. 辅助的，助理的；有帮助的OE = output enable 外部的；表面的；外在的n. 外部；表面；外型；外貌MSB = most significant bit连续的；连载的；分期偿还的n.电视连续剧；[图情] 期刊；连载小说ET0 （）enable timer 0 T0中断允许位ET1（）enable timer 1 T1中断允许位EX1 （）enable exterior 1 外部中断1中断允许位EX0 （）enable exterior 0 外部中断0中断允许位IP （B8H）interrupt priority 中断优先级寄存器PS priority serial 串口优先级标志位PT1 priority timer 1 定时器1优先级标志位PX1 priority exterior 1 外部中断1优先级标志位PT0 priority timer 0 定时器0优先级标志位PX0 priority exterior 0 外部中断0优先级标志位PCON (87H) power control 电源控制和波特率选择TMOD （89H）timer mode 定时器方式控制寄存器。

51单片机论文英语文翻译

英文原文DescriptionThe AT89C51 is a low-power, high-performance CMOS 8-bit microcomputer with 4K bytes of Flash Programmable and Erasable Read Only Memory (PEROM) and 128 bytes RAM. The device is manufactured using Atmel’s high density nonvolatile memory technology and is compatible with the industry standard MCS-51™ instruction set and pinout. The chip combines a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89C51 is a powerful microcomputer which provides a highly flexible and cost effective solution to many embedded control applications.Features:• Compatible with MCS-51™ Products• 4K Bytes of In-System Reprogrammable Flash Memory• Endurance: 1,000 Write/Erase Cycles• Fully Static Operation: 0 Hz to 24 MHz• Three-Level Program Memory Lock• 128 x 8-Bit Internal RAM• 32 Programmable I/O Lines• Two 16-Bit Timer/Counters• Six Interrupt Sources• Programmable Serial Channel• Low Power Idle and Power Down ModesThe AT89C51 provides the following standard features: 4K bytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bit timer/counters, a five vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator and clock circuitry. In addition, the AT89C51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt system to continue functioning. The Power Down Mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset.Block DiagramVCC Supply voltage.GND Ground.Port 0Port 0 is an 8-bit open drain bidirectional I/O port. As an output port each pin can sink eight TTL inputs. When is are written to port 0 pins, the pins can be used as high impedance inputs.Port 0 may also be configured to be the multiplexed loworder address/data bus during accesses to external program and data memory. In this mode P0 has internal pullups.Port 0 also receives the code bytes during Flash programming, and outputs the code bytes during program verification. External pullups are required during program verification.Port 1Port 1 is an 8-bit bidirectional I/O port with internal pullups. The Port 1 output buffers cansink/source four TTL inputs. When 1s are written to Port 1 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pullups.Port 1 also receives the low-order address bytes during Flash programming and verification.Port 2Port 2 is an 8-bit bidirectional I/O port with internal pullups. The Port 2 output buffers cansink/source four TTL inputs. When 1s are written to Port 2 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (I IL) because of the internal pullups.Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @ DPTR). In this application it uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register.Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.Port 3Port 3 is an 8-bit bidirectional I/O port with internal pullups. The Port 3 output buffers cansink/source four TTL inputs. When 1s are written to Port 3 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pullups.Port 3 also serves the functions of various special features of the AT89C51 as listed below:Port 3 also receivessome control signals forFlash programming andverification.RSTReset input. A high onthis pin for two machinecycles while the oscillator isrunning resets the device.ALE/PROGAddress Latch Enable output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming.In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory.If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.PSENProgram Store Enable is the read strobe to external program memory.When the AT89C51 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory.EA/VPPExternal Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset.EA should be strapped to VCC for internal program executions.This pin also receives the 12-volt programming enable voltage(VPP) during Flash programming, for parts that require 12-volt VPP.XTAL1Input to the inverting oscillator amplifier and input to the internal clock operating circuit.XTAL2Output from the inverting oscillator amplifier.Oscillator CharacteristicsXTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in Figure 1. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 2. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed.Idle ModeIn idle mode, the CPU puts itself to sleep while all the onchip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset.It should be noted that when idle is terminated by a hard ware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin orto external memory.Power Down ModeIn the power down mode the oscillator is stopped, and the instruction that invokes power down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the power down mode is terminated. The only exit from power down is a hardware reset. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize.Program Memory Lock BitsOn the chip are three lock bits which can be left unprogrammed (U) or can be programmed (P) to obtain the additional features listed in the table below:If the device is powered up without a reset, the latch initializes to a random value, and holds that valueuntil reset is activated. It is necessary that the latched value of EA be in agreement with the current logic level at that pin in order for the device to function properly.Programming the Flash：The AT89C51 is normally shipped with the on-chip Flash memory array in the erased state (that is, contents = FFH) and ready to be programmed.The programming interface accepts either a high-voltage (12-volt) or a low-voltage (VCC) program enable signal.The low voltage programming mode provides a convenient way to program the AT89C51 inside the user’s system, while the high-voltage programming mode is compatible with conventional third party Flash or EPROM programmers.The AT89C51 is shipped with either the high-voltage or low-voltage programming mode enabled.program any nonblank byte in the on-chip Flash Programmable and Erasable Read Only Memory, the entire memory must be erased using the Chip Erase Mode.Programming Algorithm:Before programming the AT89C51, the address, data and control signals should be set up according to the Flash programming mode table and Figures 3 and 4. To program the AT89C51, take the following steps.1. Input the desired memory location on the address lines.2. Input the appropriate data byte on the data lines.3. Activate the correct combination of control signals.4. Raise EA/VPP to 12V for the high-voltage programming mode.5. Pulse ALE/PROG once to program a byte in the Flash array or the lock bits. The byte-write cycle is self-timed and typically takes no more than 1.5 ms. Repeat steps 1 through 5, changing the address and data for the entire array or until the end of the object file is reached.Data Polling: The AT89C51 features Data Polling to indicate the end of a write cycle. During a write cycle, an attempted read of the last byte written will result in the complement of the written datum on PO.7. Once the write cycle has been completed, true data are valid on all outputs, and the next cycle may begin. Data Polling may begin any time after a write cycle has been initiated.Ready/Busy: The progress of byte programming can also be monitored by the RDY/BSY output signal. P3.4 is pulled low after ALE goes high during programming to indicate BUSY. P3.4 is pulled high again when programming is done to indicate READY.Program Verify: If lock bits LB1 and LB2 have not been programmed, the programmed code data can be read back via the address and data lines for verification. The lock bits cannot be verified directly. Verification of the lock bits is achieved by observing that their features are enabled.Chip Erase: T he entire Flash Programmable and Erasable Read Only Memory array is erasedelectrically by using the proper combination of control signals and by holding ALE/PROG low for 10 ms. The code array is written with all “1”s. The chip erase operation must be executed before the code memory can be re-programmed.Reading the Signature Bytes: The signature bytes are read by the same procedure as a normal verification of locations 030H, 031H, and 032H, except that P3.6 and P3.7 must be pulled to a logic low. The values returned are as follows.(030H) = 1EH indicates manufactured by Atmel(031H) = 51H indicates 89C51(032H) = FFH indicates 12V programming(032H) = 05H indicates 5V programmingProgramming InterfaceEvery code byte in the Flash array can be written and the entire array can be erased by using the appropriate combination of control signals. The write operation cycle is selftimed and once initiated,will automatically time itself to completion.Figure 3. Programming the Flash Figure 4. Verifying the FlashFlash Programming and Verification CharacteristicsNote: 1. Only used in 12-volt programming mode.Flash Programming and Verification Waveforms - High Voltage Mode (VPP = 12V)Flash Programming and Verification Waveforms - Low Voltage Mode (VPP = 5V)Absolute Maximum Ratings*Operating Temperature.................................. -55°C to +125°CStorage Temperature ..................................... -65°C to +150°CVoltage on Any Pinwith Respect to Ground .....................................-1.0V to +7.0VMaximum Operating Voltage............................................. 6.6VDC Output Current...................................................... 15.0 mADC CharacteristicsMaximum IOL per port pin: 10 mAMaximum IOL per 8-bit port: Port 0: 26 mAPorts 1, 2, 3: 15 mAMaximum total IOL for all output pins: 71 mA2. Minimum VCC for Power Down is 2V.AC Characteristics(Under Operating Conditions; Load Capacitance for Port 0, ALE/PROG, and PSEN = 100 pF; Load Capacitance for all other outputs = 80 pF)External Program Memory Read CycleExternal Data Memory Read CycleExternal Data Memory Write CycleExternal Clock Drive WaveformsShift Register Mode Timing WaveformsAC Testing Input/Output Waveforms(1)Note: 1. AC Inputs during testing are driven at VCC - 0.5V for a logic 1 and 0.45V for a logic 0. Timing measurements are made at VIH min. for a logic 1 and VIL max. for a logic 0.Float Waveforms(1)Note: 1. For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to float when 100 mV change from the loaded VOH/VOL level occurs.Ordering Information– Reserved bits.. Reset value depends on reset source.描述AT89C51是美国ATMEL公司生产的低电压，高性能CMOS8位单片机，片内含4Kbytes的快速可擦写的只读程序存储器（PEROM）和128 bytes 的随机存取数据存储器（RAM），器件采用ATMEL公司的高密度、非易失性存储技术生产，兼容标准MCS-51产品指令系统，片内置通用8位中央处理器（CPU）和flish存储单元，功能强大AT89C51单片机可为您提供许多高性价比的应用场合，可灵活应用于各种控制领域。

单片机外文翻译外文文献英文文献中英对照基于C51兼容微(宝典)

附录A 英文原文Design of PWM Controller in a MCS-51 Compatible MCUAuthor . Yue-Li Hu Wei Wang Microelectronic Research Development Center CampusP.O.B.221 149 Yanchang Rd Shanghai 200072 China Introduction PWM technology is a kind of voltage regulation method by controlling the switchfrequency of DC power with fixed voltage to modify the two-end voltage of load. Thistechnology can be used for a variety of applications including motor control temperaturecontrol and pressure control and so on. In the motor control system shown as Fig. 1 throughadjusting the duty cycle of power switch the speed of motor can be controlled. As shown inFig. 2 under the control of PWM signal the average of voltage that controls the speed ofmotor changes with Duty-cycle D t1/T in this Figure thus the motor speed can beincreased when motor power turn on decreased when power turn off.Fig.1: The Relationship between Voltage of Armature and Fig.2 Architecture of PWM Module Therefore the motor speed can be controlled with regularly adjusting the time of turn-onand turn-off. There are three methods could achieve the adjustment of duty cycle: 1 Adjustfrequency with fixed pulse-width. 2 Adjust both frequency and pulse-width. 3 Adjustpulse-width with fixed frequency. Generally there are four methods to generate the PWM signals as the following: 1Generated by the device composed of separate logic components. This method is the originalmethod which now has been discarded. 2 Generated by software. This method need CPU tocontinuously operate instructions to control I/O pins for generating PWM output signals sothat CPU can not do anything other. Therefore the method also has been discarded gradually.3 Generated by ASIC. The ASIC makes a decrease of CPU burden and steady workgenerally has several functions such as over-current protection dead-time adjustment and soon. Then the method has been widely used in many kinds of occasion now. 4 Generated byPWM function module of MCU. Through embedding PWM function module in MCU andinitializing the function PWM pins of MCU can also automatically generate PWM outsignals without CPU controlling only when need to change duty-cycle. It is the method thatwill be implemented in this paper. In this paper we propose a PWM module embedded in a 8051 microcontroller. ThePWM module can support PWM pulse signals by initializing the control register andduty-cycle register with three methods just mentioned above to adjust the duty cycle andseveral operation modes to add flexibility for user. The following section explains the architecture of the PWM module and the architecturesof basic functional blocks. Section3 describes two operation modes. Experimental andsimulation results verifying proper system operation are also shown in that section.Depending on mode of operation the PWM module creates one or more pulse-widthmodulated signals whose duty ratios can be independently adjusted. Implementation of PWM module in MCU Overview of the PWM module A block diagram of PWM module is shown in Fig.3. It is clearly from the diagram thatthe whole module is composed of two sections: PWM signal generator and dead-timegenerator with channel select logic. The PWM function can be started by the user throughimplementing some instructions for initializing the PWM module. In particular the followingpower and motion control applications are supported: DC Motor Uninterruptablel Power Supply UPSThe PWM module also has the following features: Two PWM signal outputs with complementary or independent operation Hardware dead-time generators for complementary mode Duty cycle updates are configurable to be immediated or synchronized to the PWM Fig.3 Architecture of PWM Module Details of the architecture PMW generator The architecture of the 2-output PWM generator shownin Fig.4 is based on a 16-bitresolution counter which creates a pulse-width modulated signal. The system is synthesizedby a system clock signal whose frequency can be divided by 4 times or 12 times throughsetting the value of T3M for PWM0 or T4M for PWM1 in the special register PWMCON asshown in Fig.4. To PWM0 generator the clock to 16-bit counter will be pre-divided by 4times by default when T3M is set to zero. And the clock will be divided by 12 times whenT3M is set to 1. This is also true for PWM1. The other bits in PWMCON are explained indetail in Table 1. Fig .4 Bit Mapping of PWMCON Table 1: The Bit Definition in PWMCONChannel-select logic The follow Fig. 5 shows the channel-select logic which is useful in ComplementaryMode. From this diagram it is clear to know that signal CP and CPWM control the source ofPWMH and PWML. And the details about the two control signals will be discussed in thesection 3 and the architecture of dead-time generator will also be discussed in section 5 forthe continuity of Complementary Mode. Fig. 5 Diagram of Channel-select LogicOperation Mode and Simulation Results The design has two operation modes: Independent Mode and Complimentary Mode. Bysetting the corresponding bit CPWM in register PWMCON shown in Fig.6 user can select oneof the two operation modes. When CPWM is set to zero PWM module will work inIndependent Mode whereas PWM module will work in Complimentary Mode. In thefollowing of this section the two operation mode will be explained respectively in detail andthe simulation results of the PWM module from the Synoposys VCS EDA platform whichverify the design will also be shown.Independent PWM Output Mode An Independent PWM Output mode is useful for driving loads such as the one shown inFigure 6. A particular PWM output is in the Independent Output mode when thecorresponding CP bit in the PWMCON register is set to zero.In this case two-channel PWMoutputs are independent of each other. The signal on pin PWM0/PWMH is from PWM0generator and the signal on pin PWM1/PWML is from PWM0 generator. The separate case isachieved by the channel-select logic shown in Fig. 6. The PWM I/O pins are set toindependent mode by default upon advice reset. The dead-time generator is disabled in theIndependent mode. The simulation result is shown in Figure 6 as the following Fig.6 Tr4 andtr3 are run bits to PWM0 and PWM1 respectively. Actually from this diagram Pin P15/P14 of MCU is used for PWMH/ PWML or normal I/O alternatively. Fig6 the Waveform of PWM Outputs in Independent ModeComplementary PWM Output Mode The Complementary Output mode is used to drive inverter loads similar to the oneshown in Figure 7. This inverter topology is typical for DC applications. In ComplementaryOutput Mode the pair of PWM outputs cannot be active simultaneously. The PWM channeland output pin pair are internally configured through channel-select logic as shown in Figure7.A dead-time may be optionally inserted during device switching where both outputs areinactive for a short period. Fig 7 : Typical Load for Complementary PWM Outputs The Complementary mode is selected for PWM I/O pin pair by setting the appropriateCPWM bit in PWMCON. In this case PSEL is in effect. PWMH and PWML will come fromPWM0 generator when PSEL is set to zero when the signals from PWM1 generator is uselesswhereas PWMH and PWML will come from PWM1 generator when PSEL is set to 1 whenthe signals from PWM0 generator is useless. In the process of producing the PWM outputs inComplementary Mode the dead-time will be inserted to be discussed in the following section.Dead-time Control Dead-time generation is automatically enabled when PWM I/O pin pair is operating inthe Complementary Output mode. Because the power output devices cannotswitchinstantaneously some amount of time must be provided between the turn-off event of onePWM output in a complementary pair and the turn-on event of the other transistor. The2-output PWM module has one programmable dead-time with 8-bitregister.Thecomplementary output pair for the PWM module has an 8-bit down counter that is used toproduce the dead-time insertion. As shown in Figure 8 the dead time unit has a rising andfalling edge detector connected to PWM signal from one of PWM generator. The dead timesis loaded into the timer on the detected PWM edge event. Depending on whether the edge isrising or falling one of the transitions on the complementary outputs is delayed until the timercounts down to zero. A timing diagram indicating the dead time insertion for the pair of PWMoutputs is shown in Figure 8a. Fig 8a Dead-time Unit Block Diagram Fig. 8b the Waveforms of PWM Outputs in Complementary ModeConclusions In this paper we have designed PWM module based on an 8-bit MCU compatible with8051 family. The design can generate 2-channel programmable periodic PWM signals withtwo operation mode Independent Mode and Complementary Mode in which dead-time willbe inserted. The simulation results on the EDA platform have proven its correctness andusefulness. 附录B 汉语翻译基于C51 兼容微处理器单片机的PWM 控制器设计Yue-Li Hu Wei Wa 单片机研究与开发中心Campus P.O.B.221 149Yanchang Rd Shanghai 200072 China 导言PWM 技术，是一种电压调节方法，通过控制具有固定电压的直流电源的开关频率来调整两端负荷电压。

单片机毕业设计(论文)外文资料翻译---51系列单片机的结构和功能

毕业设计(论文)外文资料翻译系：电光系专业：电子科学与技术姓名：学号： 080403136外文出处：Structure and function of(用外文写)the MCS-51 series 附件： 1.外文资料翻译译文；2.外文原文。

指导教师评语：签名：年月日注：请将该封面与附件装订成册。

附件1：外文资料翻译译文51系列单片机的结构和功能51系列单片机是英特尔公司生产的具有一定结构和功能的单片机产品。

这家公司在1976年引入8位MCS - 48系列单片机后，于1980年又推出了8位高档的MCS - 51系列单片机。

它包含很多种这类型的单片机，如8051，8031，8751，80C51BH，80C31BH等，它们的基本组成，基本性能和指令系统都是一样的。

一般情况习惯用8051来代表51系列单片机。

早期的单片机都是8位或4位的。

其中最成功的是INTEL的8031，因为简单可靠而性能不错获得了很大的好评。

此后在8031上发展出了MCS51系列单片机系统。

基于这一系统的单片机系统直到现在还在广泛使用。

随着工业控制领域要求的提高，开始出现了16位单片机，但因为性价比不理想并未得到很广泛的应用。

90年代后随着消费电子产品大发展，单片机技术得到了巨大提高。

随着INTEL i960系列特别是后来的ARM系列的广泛应用，32位单片机迅速取代16位单片机的高端地位，并且进入主流市场。

而传统的8位单片机的性能也得到了飞速提高，处理能力比起80年代提高了数百倍。

目前，高端的32位单片机主频已经超过300MHz，性能直追90年代中期的专用处理器，而普通的型号出厂价格跌落至1美元，最高端的型号也只有10美元。

当代单片机系统已经不再只在裸机环境下开发和使用，大量专用的嵌入式操作系统被广泛应用在全系列的单片机上。

而在作为掌上电脑和手机核心处理的高端单片机甚至可以直接使用专用的Windows和Linux操作系统。

单片机比专用处理器更适合应用于嵌入式系统，因此它得到了最多的应用。

51单片机英文缩写全称(整理最全)

MCS-51指令英语全简称（1）数据传送类指令（7种助记符）助记符英文注释功能MOV Move 对内部数据寄存器RAM和特殊功能寄存器SFR的数据进行传送MOVC Move Code 读取程序存储器数据表格的数据传送MOVX Move External RAM 对外部RAM的数据传送XCH Exchange 字节交换XCHD Exchange low-order Digit 低半字节交换PUSH Push onto Stack) 入栈POP Pop from Stack) 出栈（2）算术运算类指令（8种助记符）ADD Addition 加法ADDC Add with Carry 带进位加法SUBB Subtract with Borrow 带借位减法DA Decimal Adjust 十进制调整INC Increment 加1DEC Decrement 减1MUL Multiplication、Multiply 乘法DIV Division、Divide 除法(3)逻辑运算类指令（10种助记符）ANL And Logic 逻辑与ORL OR Logic 逻辑或XRL Exclusive-OR Logic 逻辑异或CLR Clear 清零CPL Complement 取反RL Rotate left 循环左移RLC Rotate Left throught the Carry flag 带进位循环左移RR Rotate Right 循环右移RRC Rotate Right throught the Carry flag 带进位循环右移SWAP Swap 低4位与高4位交换(4)控制转移类指令（17种助记符）ACALL Absolute subroutine Call 子程序绝对调用LCALL Long subroutine Call 子程序长调用RET Return from subroutine 子程序返回RETI Return from Interruption 中断返回JMP Jump Indirect 跳转指令SJMP Short Jump 短转移AJMP Absolute Jump 绝对转移LJMP Long Jump 长转移CJNE Compare and Jump if Not Equal 比较不相等则转移DJNZ Decrement and Jump if Not Zero 减１后不为０则转移JZ Jump if Zero 结果为０则转移JNZ Jump if Not Zero 结果不为０则转移JC Jump if the Carry flag is set 有进位则转移JNC Jump if Not Carry 无进位则转移JB Jump if the Bit is set) B 位为１则转移JNB Jump if the Bit is Not set B 位为０则转移JBC Jump if the Bit is set and Clear the bit 位为１则转移，并清除该位NOP No Operation 空操作（5）位操作指令（1种助记符）SETB Set Bit 置位伪指令助记符英文注释功能ORG Origin 起始地址DB Define Byte 定义字节DW Define Word 定义字义EQU Equal 赋值（右赋左）等于DATA Data 数据赋值（右赋左）XDATA External Data 外部数据赋值（右赋左）BIT Bit 位地址赋值END End 汇编结束DS Define storage 定义存储空间51外部引脚缩写英文解释中文解释RST （9）Reset 复位信号引脚RxD (10--P3.0) Receive Data 串口接收端TxD (11--P3.1) Transmit Data 串口发送端INT0(————)（12--P3.2）Interrupt0 外部中断0信号输入引脚INT1(————) （13--P3.3）Interrupt1 外部中断1信号输入引脚T0 (14--P3.4) Timer0 定时/计数器0输入信号引脚T1 (15--P3.5) Timer1 定时/计数器1输入信号引脚WR(———) (16--P3.6) write 存储器的写信号写信号引脚RD(———) (17--P3.7) read 读信号引脚PSEN(—————) （29）progammer saving enable 外部程序存储器读选通信号ALE （30）Address Latch Enable 地址锁存允许信号EA(———) (31) enable 外部ROM选择信号51内部寄存器SFR special funtion register 特殊功能寄存器ACC accumulate 累加器APSW progammer status word 程序状态字CY (PSW.7) carry 进位标志位AC (PSW.6) assistant carry 辅助进位标志位OV (PSW.2) overflow 溢出标志位PC progammer counter 程序计数器DPTR data point register 数据指针寄存器SP stack point 堆栈指针TCON timer control 定时器控制寄存器TF1 （TCON.7）Timer1 flag T1中断标志位TR1 （TCON.6）Timer1 Run T1运行控制位TF0 （TCON.5）Timer0 flag T0中断标志位TR0 （TCON.4）Timer0 Run T0运行控制位IE1 （TCON.3）Interrupt1 exterior 外部中断1中断标志位IT1 （TCON.2）Interrupt1 touch 外部中断1 触发方式选择位IE0 （TCON.1）Interrupt0 exterior 外部中断0中断标志位IT0 （TCON.0）Interrupt0 touch 0-电平触发1-下降沿触发IE （A8H）interrupt enable 中断允许寄存器EA (IE.7) enable all interrupt 中断总允许位ES (IE.4) enable serial 串行口中断允许位ET1 （IE.3）enable timer 1 T1中断允许位EX1 （IE.2）enable exterior 1 外部中断1中断允许位ET0 （IE.1）enable timer 0 T0中断允许位EX0 （IE.0）enable exterior 0 外部中断0中断允许位IP （B8H）interrupt priority 中断优先级寄存器PS (IP.4) priority serial 串口优先级标志位PT1 (IP.3) priority timer 1 定时器1优先级标志位PX1 (IP.2) priority exterior 1 外部中断1优先级标志位PT0 (IP.1) priority timer 0 定时器0优先级标志位PX0 (IP.0) priority exterior 0 外部中断0优先级标志位PCON (87H) power control 电源控制和波特率选择TMOD （89H）timer mode 定时器方式控制寄存器MSB = most significant bit//最高有效位LSB = last significant bit//最低有效位OE = output enable //输出使能PROG progamme 程序XTAL:External Crystal Oscillator,外部晶体振荡器CLKOUT：Clock out,时钟输出BUSWDITH：总线宽度Vref：参考电压（带ADC的单片机中有的）RESET：复位，重启ACH：？？HSO：High Speed Output，高速输出HSI：High Speed Input：高速输入INST：Instruction，指令READY：就绪，总线中的就绪信号或引脚NMI：No Mask Interruput （Input）：不可屏蔽的中断请求（输入）RXD：Receive Data ，接收串行数据，单片机中有UART/USART功能的串行数据输入引脚TXD：Transmit Data，发送串行数据，单片机中有UART/USART功能的串行数据输出引脚BHE：Bank High Enable：存储器的高位允许，如在80286系统中RAM的组织为16位的，分为高8位和低8位数据，分别的控制信号为BHE和BLEALE：Address Latch Enable，地址信号锁定允许，这在早期Intel总线结构中是必不可少的信号，常和锁存器使用来分离地址/数据复用端口的地址和数据信。

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51单片机简介描述AT89C51是一个低电压，高性能CMOS8位单片机带有4K字节的可反复擦写的程序存储器（PENROM）。

和128字节的存取数据存储器（RAM），这种器件采用ATMEL公司的高密度、不容易丢失存储技术生产，并且能够与MCS-51系列的单片机兼容。

片内含有8位中央处理器和闪烁存储单元，有较强的功能的AT89C51单片机能够被应用到控制领域中。

功能特性AT89C51提供以下的功能标准：4K字节闪烁存储器，128字节随机存取数据存储器，32个I/O口，2个16位定时/计数器，1个5向量两级中断结构，1个串行通信口，片内震荡器和时钟电路。

另外，AT89C51还可以进行0HZ的静态逻辑操作，并支持两种软件的节电模式。

闲散方式停止中央处理器的工作，能够允许随机存取数据存储器、定时/计数器、串行通信口及中断系统继续工作。

掉电方式保存随机存取数据存储器中的内容，但震荡器停止工作并禁止其它所有部件的工作直到下一个复位。

引脚描述VCC：电源电压GND：地P0口：P0口是一组8位漏极开路双向I/O口，即地址/数据总线复用口。

作为输出口时，每一个管脚都能够驱动8个TTL电路。

当“1”被写入P0口时，每个管脚都能够作为高阻抗输入端。

P0口还能够在访问外部数据存储器或程序存储器时，转换地址和数据总线复用，并在这时激活内部的上拉电阻。

P0口在闪烁编程时，P0口接收指令，在程序校验时，输出指令，需要接电阻。

P1口：沈阳航空工业学院电子工程系毕业设计（外文翻译）- 2 - P1口一个带内部上拉电阻的8位双向I/O口，P1的输出缓冲级可驱动4个TTL电路。

对端口写“1”，通过内部的电阻把端口拉到高电平，此时可作为输入口。

因为内部有电阻，某个引脚被外部信号拉低时输出一个电流。

闪烁编程时和程序校验时，P1口接收低8位地址。

P2口：P2口是一个内部带有上拉电阻的8位双向I/O口，P2的输出缓冲级可驱动4个TTL电路。

对端口写“1”，通过内部的电阻把端口拉到高电平，此时，可作为输入口。

因为内部有电阻，某个引脚被外部信号拉低时会输出一个电流。

在访问外部程序存储器或16位地址的外部数据存储器时，P2口送出高8位地址数据。

在访问8位地址的外部数据存储器时，P2口线上的内容在整个运行期间不变。

闪烁编程或校验时，P2口接收高位地址和其它控制信号。

P3口：P3口是一组带有内部电阻的8位双向I/O口，P3口输出缓冲故可驱动4个TTL 电路。

对P3口写如“1”时，它们被内部电阻拉到高电平并可作为输入端时，被外部拉低的P3口将用电阻输出电流。

P3口除了作为一般的I/O口外，更重要的用途是它的第二功能，如下表所示：P3RST：复位输入。

当震荡器工作时，RET引脚出现两个机器周期以上的高电平将使单片机复位。

ALE/PROG：当访问外部程序存储器或数据存储器时，ALE输出脉冲用于锁存地址的低8位字节。

即使不访问外部存储器，ALE以时钟震荡频率的1/16输出固定的正脉冲信号，因此它可对输出时钟或用于定时目的。

要注意的是：每当访问外部数据存储器时将跳过一个ALE脉冲时，闪烁存储器编程时，这个引脚还用于输入编程脉冲。

如果必要，可对特殊寄存器区中的8EH单元的D0位置禁止ALE操作。

这个位置后只有一条MOVX和MOVC指令ALE才会被应用。

此外，这个引脚会微弱拉高，单片机执行外部程序时，应设置ALE无效。

PSEN：程序储存允许输出是外部程序存储器的读选通信号，当AT89C51由外部程序存储器读取指令时，每个机器周期两次PSEN 有效，即输出两个脉冲。

在此期间，当访问外部数据存储器时，这两次有效的PSEN 信号不出现。

EA/VPP：外部访问允许。

欲使中央处理器仅访问外部程序存储器，EA端必须保持低电平。

需要注意的是：如果加密位LBI被编程，复位时内部会锁存EA端状态。

如EA端为高电平，CPU则执行内部程序存储器中的指令。

闪烁存储器编程时，该引脚加上+12V 的编程允许电压VPP，当然这必须是该器件是使用12V编程电压VPP。

XTAL1：震荡器反相放大器及内部时钟发生器的输入端。

XTAL2：震荡器反相放大器的输出端。

时钟震荡器AT89C51中有一个用于构成内部震荡器的高增益反相放大器，引脚XTAL1和XTAL2分别是该放大器的输入端和输出端。

这个放大器与作为反馈元件的片外石英晶体或陶瓷谐振器一起构成自然震荡器。

外接石英晶体及电容C1，C2接在放大器的反馈回路中构成并联震荡电路。

对外接电容C1，C2虽然没有十分严格的要求，但电容容量的大小会轻微影响震荡频率的高低、震荡器工作的稳定性、起振的难易程序沈阳航空工业学院电子工程系毕业设计（外文翻译）- 4 - 及温度稳定性。

如果使用石英晶体，我们推荐电容使用30PF±10PF ，而如果使用陶瓷振荡器建议选择40PF±10PF 。

用户也可以采用外部时钟。

采用外部时钟的电路如图示。

这种情况下，外部时钟脉冲接到XTAL1端，即内部时钟发生器的输入端，XTAL2则悬空。

由于外部时钟信号是通过一个2分频触发器后作为内部时钟信号的，所以对外部时钟信号的占空比没有特殊要求，但最小高电平持续时间和最大的低电平持续时间应符合产品技术条件的要求。

内部振荡电路外部振荡电路闲散节电模式AT89C51有两种可用软件编程的省电模式，它们是闲散模式和掉电工作模式。

这两种方式是控制专用寄存器PCON 中的PD 和IDL 位来实现的。

PD 是掉电模式，当PD=1时，激活掉电工作模式，单片机进入掉电工作状态。

IDL 是闲散等待方式，当IDL=1，激活闲散工作状态，单片机进入睡眠状态。

如需要同时进入两种工作模式，即PD 和IDL 同时为1，则先激活掉电模式。

在闲散工作模式状态，中央处理器CPU 保持睡眠状态，而所有片内的外设仍保持激活状态，这种方式由软件产生。

此时，片内随机存取数据存储器和所有特殊功能寄存器的内容保持不变。

闲散模式可由任何允许的中断请求或硬件复位终止。

终止闲散工作模式的方法有两种，一是任何一条被允许中断的事件被激活，IDL 被硬件清除，即刻终止闲散工作模式。

程序会首先影响中断，进入中断服务程序，执行完中断服务程序，并紧随RETI 指令后，下一条要执行的指令就是使单片机进入闲散工作模式，那条指令后面的一条指令。

二是通过硬件复位也可将闲散工作模式终止。

需要注意的是：当由硬件复位来终止闲散工作模式时，中央处理器CPU通常是从激活空闲模式那条指令的下一条开始继续执行程序的，要完成内部复位操作，硬件复位脉冲要保持两个机器周期有效，在这种情况下，内部禁止中央处理器CPU访问片内RAM，而允许访问其他端口，为了避免可能对端口产生的意外写入：激活闲散模式的那条指令后面的一条指令不应是一条对端口或外部存储器的写入指令。

掉电模式在掉电模式下，振荡器停止工作，进入掉电模式的指令是最后一条被执行的指令，片内RAM和特殊功能寄存器的内容在中指掉电模式前被冻结。

退出掉电模式的唯一方法是硬件复位，复位后将从新定义全部特殊功能寄存器但不改变RAM中的内容，在VCC恢复到正常工作电平前，复位应无效切必须保持一定时间以使振荡器从新启动并稳定工作。

闲散和掉电模式外部引脚状态。

程序存储器的加密AT89C51可使用对芯片上的三个加密位LB1，LB2，LB3进行编程（P）或不编程（U）得到如下表所示的功能：沈阳航空工业学院电子工程系毕业设计（外文翻译）- 6 - 当LB1被编程时，在复位期间，EA端的电平被锁存，如果单片机上电后一直没有复位，锁存起来的初始值是一个不确定数，这个不确定数会一直保存到真正复位位置。

为了使单片机正常工作，被锁存的EA电平与这个引脚当前辑电平一致。

机密位只能通过整片擦除的方法清除。

DescriptionThe AT89C51 is a low-power, high-performance CMOS 8-bit microcomputer with 4K bytes of Flash programmable and erasable read only memory (PEROM). The device is manufactured using Atmel’s high-density nonvolatile memory technology and is compatible with the industry-standard MCS-51 instruction set and pinout. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89C51 is a powerful microcomputer which provides a highly-flexible and cost-effective solution to many embedded control applications. Function characteristicThe AT89C51 provides the following standard features: 4K bytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bit timer/counters, a five vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator and clock circuitry. In addition, the AT89C51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt system to continue functioning. The Power-down Mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset.Pin DescriptionVCC：Supply voltage.GND：Ground.Port 0：Port 0 is an 8-bit open-drain bi-directional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as highimpedance inputs.Port 0 may also be configured to be the multiplexed loworder address/data bus during accesses to external program and data memory. In this mode P0 has internal pullups.Port 0 also receives the code bytes during Flash programming,and outputs the code bytes during programverification. External pullups are required during programverification.沈阳航空工业学院电子工程系毕业设计（外文翻译）- 8 - Port 1Port 1 is an 8-bit bi-directional I/O port with internal pullups.The Port 1 output buffers can sink/source four TTL inputs.When 1s are written to Port 1 pins they are pulled high by the internal pullups and can be used as inputs. As inputs,Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pullups.Port 1 also receives the low-order address bytes during Flash programming and verification. Port 2Port 2 is an 8-bit bi-directional I/O port with internal pullups.The Port 2 output buffers can sink/source four TTL inputs.When 1s are written to Port 2 pins they are pulled high by the internal pullups and can be used as inputs. As inputs,Port 2 pins that are externally being pulled low will source current, because of the internal pullups.Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses. In this application, it uses strong internal pullupswhen emitting 1s. During accesses to external data memory that use 8-bit addresses, Port 2 emits the contents of the P2 Special Function Register.Port 2 also receives the high-order address bits and some control signals during Flash programming and verification. Port 3Port 3 is an 8-bit bi-directional I/O port with internal pullups.The Port 3 output buffers can sink/source four TTL inputs.When 1s are written to Port 3 pins they are pulled high by the internal pullups and can be used as inputs. As inputs,Port 3 pins that are externally being pulled low will source current (IIL) because of the pullups.Port 3 also serves the functions of variousspecial features of the AT89C51 as listed below:Port 3 also receives some control signals for Flash programming and verification.RSTReset input. A high on this pin for two machine cycles while the oscillator is running resets the device.ALE/PROGAddress Latch Enable output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming.In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory.If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.PSENProgram Store Enable is the read strobe to external program memory.When the AT89C51 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory.EA/VPPExternal Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset.EA should be strapped to VCC for internal program executions.This pin also receives the 12-volt programming enable voltage(VPP) during Flash programming, for parts that require12-volt VPP.XTAL1Input to the inverting oscillator amplifier and input to the internal clock operating circuit.沈阳航空工业学院电子工程系毕业设计（外文翻译）- 10 - XTAL2Output from the inverting oscillator amplifier.Oscillator CharacteristicsXTAL1 and XTAL2 are the input and output, respectively,of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in Figure 1.Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 2.There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimumand maximum voltage high and low time specifications must be observed.Figure 1. Oscillator Connections Figure 2. External Clock Drive ConfigurationIdle ModeIn idle mode, the CPU puts itself to sleep while all the onchip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset.It should be noted that when idle is terminated by a hard ware reset, the device normally resumes program execution,from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event,but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory.Power-down ModeIn the power-down mode, the oscillator is stopped, and the instruction that invokes power-down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the power-down mode is terminated. The only exit from power-down is a hardware reset. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operatinglevel and must be held active long enough to allow the oscillator to restart and stabilize.Program Memory Lock BitsOn the chip are three lock bits which can be left unprogrammed (U) or can beprogrammed (P) to obtain the additional features listed in the table below.When lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during reset. If the device is powered up without a reset, the latch initializes to a random value, and holds that value until reset is activated. It is necessary that the latched value of EA be in agreement with the current logic level at that pin in order for the device to function properly.。

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