基于单片机的锁相环频率合成器设计

摘要

在现代电子技术的设计与开发过程中，特别是在通信、雷达、航空、航天以及仪器仪表等领域,都需要进一步提高一系列高精度、高稳定度的频率源的频率精度。这样，一般的振荡器已经无法满足各种应用的发展要求，而晶体振荡器的性能虽然比较好,但其频率单一，或只能在极小的范围内进行微调。

锁相环是一个相位误差控制系统。它比较输入信号和振荡器输出信号之间的相位差，从而产生误差控制信号来调整振荡器的频率，以达到与输入信号同频同相。

本课题给出一种以单片集成PLL芯片74HC4046为核心，并通过AT89C51 单片机对74HC4046进行控制来实现锁相频率合成器的设计方法，设计一个由单片机、定时计数器及单片集成锁相环路组成的可编程控制频率合成器。本文在介绍了74HC4046芯片的内部功能结构的基础上，探讨了锁相频率合成器的基本原理和工作特性,给出了74HC4046的锁相频率合成器的硬件电路结构和软件程序设计方法。该设计经仿真测试证明,锁相效果良好,结构精简，性能可靠。

关键词:74HC4046； AT89C51；频率合成器

Abstract

In the design and development process of modern electronic technology, especially in communication, radar, aviation, aerospace, instrumentation and other fields, are needed to further improve the precision offrequency frequency source is a series of high precision, high stability. In this way, the oscillator has beenunable to meet the development requirements of various applications, while the performance of crystaloscillator is good, but the single frequency, or only in the context of minimal fine-tuning.

Phase locked loop is a phase error control system. It compares the input signal and the output signal of the oscillator phase difference, thereby generating an error control signal to adjust the frequency of the oscillator, in order to achieve thesame frequency and phase with the signal input.

This topic is to design a composed of single-chip, timing counter and monolithic integrated PLL Programmable control frequency synthesizer, so the design process will involve a phase locked loop, frequency synthesizer and the microcontroller knowledge. This paper presents a monolithic integrated PLL chip 74HC4046 as the core, and through the AT89C51 MCU to control 74HC4046 to realize the design method of PLL frequency synthesizer. In this paper the basicfunctional structure of chip of 74HC4046, discusses the basic principle and working characteristics of PLL frequency synthesizer, the hardware structure andsoftware design method of PLL Frequency Synthesizer Based on 74HC4046 is given. The design of the simulation test, the lock-in effect is good, simple structure, reliable performance.

Key words:74HC4046; AT89C51; frequency synthesizer

目录

摘要 ......................................................................................................................................... I Abstract ...................................................................................................................................... II 1绪论 .. (1)

1.1 设计背景及意义 (3)

1.2 锁相环频率合成器综述 (3)

2基于单片机的锁相环频率合成器方案设计与论证 (4)

2.1 课题研究的内容与要求 (4)

2.2 方案的设计与选择 (4)

2.3 设计原理 (5)

2.3.1 锁相环基本原理 (6)

2.3.2 锁相频率合成器的基本原理 (8)

3 基于单片机的锁相环频率合成器设计方案 (10)

3.1 硬件系统的设计 (10)

3.1.1 74HC4046 (10)

3.1.2 CD4522 (15)

3.1.3 LCD1602 (16)

3.1.4 AT89C51单片机 (18)

3.2 软件系统设计 (22)

3.2.1 软件系统主程序流程图 (22)

3.2.2 键盘扫描流程图 (23)

3.2.3 脉冲计数流程图 (24)

4 电路仿真 (25)

4.1 仿真软件介绍 (25)

4.1.1 proteus (25)

4.1.2 Keil编译软件 (26)

4.2 硬件电路仿真 (27)

4.2.1 锁相环模块 (27)

4.2.2 4522分频器模块 (28)

4.2.3 单片机模块 (29)

4.2.4 显示及按键模块 (30)

结论 (31)

致谢 (32)

参考文献 (33)

附录 (34)

附录A High Speed Digital Hybrid PLL Frequency Synthesizer (34)

Abstract (34)

INTRODUCTION (34)

DH-PLL synthesizer (35)

Simulation results and discussion (36)

Conclusion (37)