DRAM内存颗粒测试简介

Multiple temperature tested (e.g. 88‟C, 25‟C, -10‟C) Long test time at low speed Patterns cover all cell arrays No Stressful condition High parallel test count, low cost Both MBT and TBT does NOT test DC (Ando Oven)
2.
Functional Test (Core Test)

3.
Speed Test

DC Test
VCC
DC Test Method: a) ISVM: I Source V Measure
VCC
b)
VSIM V Source I Measure
DC Test – Open Short
Purpose:
Socket issue Socket Pogo Pin defect
DC Test – Open Short
O/S Test Condition:
PMU
> 1.5V
Typical 0.65V < 0.2V Fail Open Pass Fail Short force 100uA force 0.65 V Measure sense 100uA Vdd=0
• Check connection between pins and test fixture
• Check if pin to pin is short in IC package • Check if pin to wafer pad has open in IC package • Check if protection diodes work on die • It is a quick electrical check to determine if it is safe to apply power • Also called Continuity Test
DC Test – Leakage
ILIH/ILIL: Input Leakage High/Low
• To verify input buffers offer a high resistance • No preconditioning pattern applied
ILOH/ILOL: Output Leakage High/Low
Failure Rate
BI
New product Mature product
Operation Time Infant Mortality Normal Life Worn out
Bath Curve
DRAM Burn-in (TBT)
TBT is for long time test patterns
• To verify tri-state output buffers offer a high resistance in off state • Test requires preconditioning pattern • Performed only on three-state outputs and bi-directional pins
DRAM Advantest Test
1.
DC Test

Open/Short test Leakage test IDD test Different parameter & Pattern for each function To check DRAM can operate functionally Timing test @ different speed grade
Backend
DRAM Burn-in (MBT)
MBT is to stress IC and screen out early failures

High Temperature Stress (125degC) High Voltage Stress Stressful Pattern
DC Test – Open Short
Failure Mode:
a) Wafer Problem
Defect of diode Wire touched
Core Circuit
Defective diode
b) Assembly Problem
Wire bonding Solder ball
c) Contact Problem
ISVM
Procedure
Other=0 Vss=0
•Ground all pins ( including VDD) •Using PMU force –100 uA, one pin at a time •Measure voltage •Fail open test if the voltage is less than –1.5 V •Fail short test if the voltage is greater than –0.2 V
IC Test Methodology
PPS Power Supply * DUT = Device Under Test
IC Tester
Driver
Input
DUT*
Comparator Output
Testing of a DUT: 1. To connect PPS, Driver, Comparator & GND. 2. To apply power to DUT. 3. To input data to DUT (Address, Control Command, Data) 4. To compare output with “expect value” and judge PASS/FAIL
•Apply VDDmax (2.0V) •Pre-condition all input pins to logic „0‟ (Low voltage) •Using PMU force VDDMAX to tested pin •Wait for 1 to 5 msec •Measure current of tested pin •Fail IIH test if the current is greater than +1.5 uA
Vss=0
DC Test – Output Leakage Low
Test Condition:
Introduction to DRAM Testing
--- DRAM inside team --- 2015.May
Agenda

Basis of Testing Typical DRAM Testing Flow Burn-in DC Test (Open/Short, Leakage, IDD) Functional Test & Test Pattern Speed Test
DC Test – Leakage
Purpose:
• Verify resistance of pin to VDD/VSS is high enough
• Verify resistance of pin to pins is high enough • Identify process problem in CMOS device
Core Test
Speed Test
• Speed & AC Timing Test • Full Speed (DDR3 @1600MHz and above), Advantest T5503 + 256DUT HiFix
• Marking Ball Scan Visual Inspection Baking Vacuum Pack
Test Condition:
PMU
Pass < –1.5 uA Fail 0V force “0” OFF VDDmax ILIL all input pins = 2.3V
-10nA
Measure ON
VLSI Core
“1”
Procedure
Vss=0
•Apply VDDmax (2.0V) •Pre-condition all input pins to logic „1‟ (high voltage) •Using PMU (Parametric Measure Unit) force Ground to tested pin •Wait for 1 to 5 msec •Measure current of tested pin •Fail IIL test if the current is less than –1.5 uA
DC Test – Open Short
O/S Test Condition:
PMU
> –0.2 V
Fail Short force -100uA force -0.65 V Measure sense -100uA Vdd=0
Typical -0.65V Pass <–1.5 V Fail Open
ISVMProcedureOther=0 Vss=0
•Ground all pins ( including VDD) •Using PMU force 100 uA, one pin at a time •Measure voltage •Fail open test if the voltage is greater than 1.5 V •Fail short test if the voltage is less than 0.2 V