SiC MOSFET 双脉冲测试装置
2015__SiC双脉冲测试IEEE
Evaluation of Switching Performance of SiC Devices in PWM Inverter-Fed Induction Motor DrivesZheyu Zhang,Student Member,IEEE,Fred Wang,Fellow,IEEE,Leon M.Tolbert,Fellow,IEEE, Benjamin J.Blalock,Senior Member,IEEE,and Daniel J.Costinett,Member,IEEEAbstract—Double pulse test(DPT)is a widely accepted method to evaluate the switching characteristics of semiconductor switches, including SiC devices.However,the observed switching perfor-mance of SiC devices in a PWM inverter for induction motor drives is almost always worse than the DPT characterization,with slower switching speed,more switching losses,and more serious parasitic ringing.This paper systematically investigates the factors that limit the SiC switching performance from both the motor side and in-verter side,including the load characteristics of induction motor and power cable,two more phase legs for the three-phase PWM inverter in comparison with the DPT,and the parasitic capacitive coupling effect between power devices and heat sink.Based on a three-phase PWM inverter with1200V SiC MOSFETs,test re-sults show that the induction motor,especially with a relatively long power cable,will significantly impact the switching performance, leading to a switching time increase by a factor of2,switching loss increase up to30%in comparison with that yielded from DPT, and serious parasitic ringing with1.5μs duration,which is more than50times of the corresponding switching time.In addition,the interactions among the three phase legs cannot be ignored unless the decoupling capacitors are mounted close to each phase leg to support the dc bus voltage during switching transients.Also,the coupling capacitance due to the heat sink equivalently increases the junction capacitance of power devices;however,its influence on the switching behavior in the motor drives is small considering the relatively large capacitance of the motor load.Index Terms—Motor drives,SiC devices,switching performance.I.I NTRODUCTIONA DJUSTABLE speed drive systems are undergoing sig-nificant changes with the application of wide-bandgap semiconductor devices,such as silicon carbide(SiC),due to their increased junction operating temperature,low specific on-resistance,and high switching speed capability.Among these benefits,the fast switching plays a key role in reducing switch-ing losses,shortening dead time for a phase leg,and increasing switching frequency capability.As a result,a SiC motor driveManuscript received August7,2014;accepted November3,2014.Date of publication December4,2014;date of current version May22,2015.This work was supported in part by the II-VI Foundation,by the Engineering Re-search Center Shared Facilities supported by the Engineering Research Center Program of the National Science Foundation and DOE under NSF Award EEC-1041877,and by the CURENT Industry Partnership Program.Recommended for publication by Associate Editor A.Mertens.The authors are with the Department of Electrical Engineering and Computer Science,University of Tennessee,Knoxville,TN37996 USA(e-mail:zzhang31@;fred.wang@;tolbert@; bblalock@;daniel.costinett@).Color versions of one or more of thefigures in this paper are available online at .Digital Object Identifier10.1109/TPEL.2014.2375827inverter can provide lower loss,higher efficiency,and smaller size in comparison with their silicon(Si)counterparts[1]–[8]. To fully utilize the potential advantages of SiC devices,care-ful attention must be given to their high switching speed per-formance.Nowadays,the widely accepted method to assess the switching performance of power devices is the double pulse test (DPT)[9]–[11].However,due to the intrinsic characteristics of SiC devices,such as small junction capacitance,small specific on-resistance,and high di/dt and dv/dt during fast switching transients,their switching behavior becomes more susceptible to parasitics and noise of the application circuit,compared with slower Si devices.Thus,the simple and layout optimized dou-ble pulse tester with an optimally designed load inductor may not sufficiently represent a more complex configuration of ac-tual converters and loads.The DPT-based design will lead to an overestimation of the switching performance,and ultimately an inadequate design of the power converter.Previously reported works observed that in a SiC-based cur-rent source rectifier,the turn-off energy was increased by a factor of5,with three times longer current fall time compared with the test result of DPT under the same operating conditions [12].Similarly,in a SiC-based voltage source inverter,due to the increased overshoot current and slower turn-off time,the total switching energies were increased by a factor of1.5to1.8[13]. Also,in adjustable speed drive applications,the test results indi-cate that the efficiency of the Si PWM inverter will decrease due to the use of long power cables[14].However,there has been few works investigating the mechanisms causing the aforemen-tioned difference in switching performance between the double pulse tester and power converters,especially for SiC devices. This paper systematically evaluates the switching perfor-mance of a SiC-based PWM inverter for induction motor drives (IMD).As shown in Fig.1,there are three primary differ-ences between the configuration of a three-phase PWM in-verter and a double pulse tester:different inductive loads,two more phase legs for inverter,and cooling systems(e.g.,heat sink).First,this paper compares the high-frequency impedances of an induction motor plus power cable and the optimally designed inductor employed in a double pulse tester.The resulting switching behavior differences are analyzed.Sec-ond,the impact of the other two phase legs on the switch-ing performance of the phase leg under test is described for the three-phase PWM inverter.Third,the parasitic capacitive coupling effect between power devices and heat sink,and its influence on the switching performance,is discussed for motor drives.Andfinally,for experimental verification,the switching performance of1200V SiC MOSFETs is evaluated0885-8993©2014IEEE.Personal use is permitted,but republication/redistribution requires IEEE permission.See /publications standards/publications/rights/index.html for more information.Fig.1.Configuration comparison between the double pulse tester and three-phase PWM inverter-fed IMD:(a)DPT circuit;and (b)three-phase PWM inverter-fedIMD.Fig.2.Typical switching current/voltage waveforms.under pulse test and continuous operating condition in a three-phase PWM inverter connected to an induction motor.II.I MPACT OF I NDUCTIVE L OADS ON S WITCHING P ERFORMANCEAs can be observed in Fig.1(a),the load inductor of the DPT circuit is paralleled with the upper switch,assuming the lower switch is selected as the device under test (DUT).During the switching transient,the upper switch stays OFF,and can be modeled as a conducting diode when the switching current is commutating (i.e.,current rise subinterval t cr during turn-on transient and current fall subinterval t cf during turn-off transient in Fig.2)or an output capacitance,while the switching voltage is changing (i.e.,voltage fall subinterval t v f during turn-on tran-sient and voltage rise subinterval t v r during turn-off transient in Fig.2).Thus,the DPT circuit can be redrawn as Fig.3,where Z L represents the inductive load impedance.If Z L is much greater than the equivalent impedance of the upper switch during the switching transient,then the impact of inductive load on the switching performance can be neglected;otherwise,Z L must be taken into consideration.For the specific analysis of the comparisons between DPT load inductor and induction motor load,four 115-μH inductors in series are employed to form a DPT load inductor,which is a typical way of designingDPTFig.3.Simplified DPT circuit.load inductor with small parasitic capacitance;a 7.5-kW induc-tion motor and 2-m power cable are selected to represent of the motor load,since it is a proper load in terms of power rat-ing for the SiC devices under evaluation (CREE CMF20120D 1200-V/24-A SiC MOSFETs).In addition,for the higher power rating induction motor with longer power cable in many practi-cal applications,the associated impedance Z L at high frequency becomes lower [15].Thus,the motor load selected in our study case indicates a conservative impact of induction motor on the switching performance.Then,the generality of the following analysis is not lost.A.Impact of Induction Motor on Switching Performance As illustrated in Fig.3,during the switching current com-mutation subinterval,the impedance of the upper switch is ex-tremely small since it can be considered as a voltage source.During the switching voltage change subinterval,the impedance of the upper switch depends on the output capacitance of the device.Normally,the equivalent impedance of the upper switch is also small in the switching-related frequency range that is determined by the switching speed [9].Typically,the frequency range is several megahertz to tens of megahertz for SiC devices considering switching intervals of tens of nanoseconds.ZHANG et al.:EV ALUATION OF SWITCHING PERFORMANCE OF SIC DEVICES IN PWM INVERTER-FED INDUCTION MOTOR DRIVES5703Fig.4.Impedance and circuit model of inductive loads:(a)Impedance of inductive loads versus C o ss of SiC device;and(b)circuit model of inductiveloads.Fig.5.Impact of parasitics of induction motor on switching current:(a)Turn-on transient;and(b)turn-off transient.In the typical DPT,the load inductor during a switching tran-sient can be approximated as a current source.Ideally,due to the infinite impedance of the current source during this dy-namic process,the load inductor has no impact on theswitching Fig.6.Impedance of induction motor with2-m cable versus induction motor. behavior of the DUT.Practically,the load inductor of the DPT is optimally designed so that its parasitics,such as equivalent parallel capacitance,are very small[10],making the load in-ductor impedance much larger than the upper switch equivalent impedance at frequencies of interest with respect to the switch-ing transition.Therefore,the load inductor has little effect on the switching performance in the DPT.However,in adjustable speed drive systems,the parasitics of the induction motor cause its high-frequency impedance to be significantly decreased,as shown in Fig.4(a).Measured using the Agilent4294A impedance analyzer,the impedance of the DPT load inductor is greater than the induction motor equivalent impedance above200kHz,although the DPT load inductance is smaller than the induction motor inductance.In addition,the measured induction motor impedance in our exam-ple system is even smaller than the equivalent impedance of the SiC device used in this case(CREE CMF20120D SiC MOS-FET)below11.5MHz.Note the device equivalent impedance is mainly determined by its output capacitance and the CREE de-vice has an output capacitance of120pF[16].On the contrary,5704IEEE TRANSACTIONS ON POWER ELECTRONICS,VOL.30,NO.10,OCTOBER2015above700kHz,the DPT load impedance is greater than the de-vice’s impedance due to its output capacitance.Consequently, the induction motor will play a significant role in the switch-ing behavior of the DUT due to the small motor impedance at high frequencies.Also,it is important to note that SiC has smaller output capacitance than its Si counterpart,resulting in higher equivalent impedance and making the SiC switch-ing behavior more susceptible to the parasitics of the induction motor.Based on the measured impedance,circuit models of the DPT load inductor and motor load are built,as shown in Fig.4(b) following the methods in[15],[17]–[19].Each parameter in the circuit model has physical meaning and significance.L d refers to the stator winding leakage inductance;R e represents the high-frequency iron loss of the stator winding;L t,C t,and R t are introduced to capture the second resonance in the mo-tor impedance characteristics,according to[17],that may be caused by the skin effect and turn-to-turn capacitance of the stator windings.As can be observed in Fig.4(a),thefitted curves of the inductive load impedance based on the circuit models can represent the critical characteristics of the motor and DPT impedances.During the switching transient,the large inductance L d can be modeled as a current source,as shown in Fig5.It is the series resonant network formed by L t,C t, and R t that affects the switching pared with the DPT load inductor with extremely small parasitic capaci-tance C t(1.2%C oss of SiC MOSFET under evaluation)and large damping resistance R t(625Ω),the parasitic capacitance C t of the induction motor is six times that of C oss of the SiC MOSFETs,and its corresponding damping resistance R t(10Ω)is relatively small.Therefore,in the time domain,consid-ering the high dv/dt drain-source voltage of the upper switch V ds H across the RLC series resonant network,the induction motor with large C t and small R t causes more serious para-sitic ringing with longer duration.This parasitic ringing causes additional resonant current toflow in the switching commuta-tion loop.Also,the switching performance of the lower switch is affected.Unlike the typical high frequency parasitic ringing (typically tens of megahertz)due to the resonance between the power loop inductance and C oss of power devices,the ringing caused by parasitics of the induction motor has relatively low frequency with5.4MHz in our case study[see Fig.4(a)].Also, this lower frequency ringing will be observed in the drain current of the lower switch during the turn-on transient and drain current of the upper switch during the turn-off transient,as illustrated in Fig.5.B.Impact of Induction Motor With Power Cableon Switching PerformanceInduction motor drive systems fed with a power cable are widely used in many industrial applications.It is,therefore, necessary to evaluate the impact of an induction motor with a power cable on the switching performance.Fig.6dis-plays the impedance comparison between the induction motor and the induction motor with2-m power cable.The impedances of the induction motor and the induction motor plus powercable Fig.7.Equivalent circuit of three-phase PWM inverter considering the parasitics.are identical below100kHz but significant differences occur at high frequency.Especially above10MHz,the impedance of the induction motor with power cable is smaller than that of the induction motor only,and is even comparable to the impedance of the SiC MOSFET’s C oss.Based on the aforementioned anal-ysis in the frequency domain,more serious impact on switching performance can be expected of the induction motor with power cable.Also,since the cable length in practical applications is generally much longer than the2m length used in our case study,more attention must be paid to the power cable’s impact. In the time domain,due to the complicated model of power ca-ble with distributed LC networks,it is difficult to illustrate the precise relationship between the power cable and the switching behavior based on a high-order circuit model.In summary,the capacitive coupling among the conductors of the power cable extends the charging/discharging subinterval during switching transients,leading to lower dv/dt,longer switching time,and larger switching losses.III.I MPACT OF P HASE L EGS AND H EAT S INKON S WITCHING P ERFORMANCEA.Interaction of Phase Legs on Switching PerformanceAs can be observed in Fig.1,as compared to double pulse tester consisting of only one phase leg,a three-phase PWM inverter has two additional phase legs.Thus,additional device and interconnection parasitics will be involved in the circuit. Assuming the upper switches of phases B and C are in on-state, while their lower switches are in off-state during the switching transients of the phase A devices,Fig.7displays the equivalent circuit of a three-phase PWM inverter considering the parasitics, where the upper switches of phases B and C are represented by their on-state resistance R ds(o n),and the junction capacitance C oss represents the lower switches of phases B and C.Also, L p(i n)is the power loop parasitic inductance within each phase leg,while L p(e x t)is the parasitic inductance distributed in theZHANG et al.:EV ALUATION OF SWITCHING PERFORMANCE OF SIC DEVICES IN PWM INVERTER-FED INDUCTION MOTOR DRIVES5705Fig.8.Connection structures of inductive loads according to different sections of space vectormodulation.Fig.9.Uniform equivalent circuit considering constant dc bus voltage thanks to decouplingcapacitors.Fig.10.Uniform equivalent circuit considering capacitive coupling effect induced by heat sink.dc bus.Z LA ,Z LB ,and Z LC are the impedances of the inductive load of each phase.As can be observed in Fig.7,the equivalent inductive load consists of parasitic inductance,on-state resistance,and three-phase inductive loads.Considering the relatively small para-sitic inductance (i.e.,L p (i n )/L p (e x t ))and the small R ds (on)of SiC devices in comparison with the impedance of inductive loads (Z LB /Z LC ),the impact of parasitics induced by the upper switches of phases B and C on the inductive loads can be neg-ligible.In addition,the potentials at nodes B and C will almost stay constant during the switching transient of the phase-A DUT due to the existence of ceramic capacitors with small equiva-lent series inductance utilized as decoupling capacitors mounted close to each phase-leg in practical applications.Therefore,for the lower switches of phases B and C,the voltages across C oss have little variation so that the switching performance of the DUT is hardly affected by the lower switches of phases B andC.Fig.11.SiC-based three-phase PWM inverter.In addition to the parasitics induced by phases B and C,the ON/OFF states of switches in the other phase leg alter the con-nection structure of inductive loads with respect to the phase leg under test.Therefore,different from a fixed inductive load po-sition within the DPT,the tested device in a three-phase PWM inverter during the commutation interval will see different com-binations of the inductive loads.According to the ON/OFF states of the phases B and C switches,based on the space vector modu-lation scheme,there are three connection structures of inductive loads with respect to phase A during a switching transient,as shown in Fig.8.Fortunately,as previously mentioned,the dc bus voltage during the switching transient stays nearly constant thanks to the decoupling capacitors close to each phase leg.Hence,according to circuit theory,the dc bus voltage source is shorted during the dynamic process analysis.Assuming the impedances of inductive loads for all phases are identical and de-noted by Z L ,three different circuits in Fig.8can be simplified as a uniform equivalent circuit,as shown in Fig.9.Consequently,different connection structures due to the switching states of phases B and C have little effect on the switching performance of phase A devices in practical applications.B.Impact of Heat Sink on Switching Performance in Motor DrivesIn a three-phase PWM inverter,SiC devices are attached to a heat sink for thermal ually,a thin layer of insulating material is used to separate the SiC devices from the electrically conductive heat sink.Thus,a parasitic capacitance is5706IEEE TRANSACTIONS ON POWER ELECTRONICS,VOL.30,NO.10,OCTOBER2015Fig.12.Different inductive loads:(a)DPT load inductor;and(b)7.5-kW induction motor with2-m power cable.formed between the drain base plate of the SiC devices and the common heat sink plate[13].In the end,this capacitance C H S is paralleled with devices,which equivalently increases their effective C oss.However,in an IMD for our study,in addition to the coupling capacitance between devices and heat sink,the parasitics of the induction motor is paralleled with devices as well,as shown in pared with the motor parasitic capacitance C t[764pF in Fig.4(b)],the coupling capacitance (39.75pF based on our test setup)is only5.2%of C t.Therefore, the capacitive coupling effect is insignificant when evaluating the switching performance of SiC MOSFETs in an IMD with relatively large capacitive parasitics.IV.E XPERIMENTAL V ERIFICATIONA.Hardware SetupTo evaluate the influence of the aforementioned impact fac-tors in Sections II and III,a three-phase PWM inverter test circuit was designed to satisfy the following requirements: 1)sufficientflexibility such that the three-phase PWM inverter can be evolved from a layout optimized double pulse tester;2)during this design evolution,the layout associated with the DUT must remain consistent;and3)a common heat sink is used for all power devices.Fig.11displays a three-phase PWM in-verter with1200-V CMF20120D SiC MOSFETs,including one uniform mother board,six gate drive daughter boards integrated with devices,and one common heat sink.Hence,a DPT con-figuration can be achieved by means of merely connecting the gate drive boards of phase A with the mother board.In addition, a three-phase PWM inverter can be assembled with all six gate drive boards of three phase-legs mounted to the mother board. Also,using the lower switch of phase A as the DUT,it can be observed that the layouts of both the power and gate loop for the DUT under either DPT configuration or inverter circuit are nearly the same.Fig.12displays two types of inductive loads:DPT load in-ductor and a7.5kW induction motor with a2-m power cable for evaluation of the difference in switching performance for double pulse tester and motor drive conditions.Note that the DPT load inductor consists of four small inductors in series is to minimize parasitics.For the fast transient measurement,the following equipment is used to detect the switching waveforms:adigital Fig.13.Test circuits for evaluation of switching performance with different inductive loads.oscilloscope(Tektronix DPO401)with frequency bandwidth of 1GHz and maximum sampling rate of5GS/s,two THDP0200 high voltage differential probes with frequency bandwidth of 200MHz for drain-source voltage measurement of the upper and lower switches in a phase leg,and two TCP0030A current probes with frequency bandwidth of120MHz for drain current measurement of the upper and lower switches in a phase leg.B.Methodology for Experimental VerificationA four-step verification procedure has been devised,that starts with the double pulse tester and ends with the three-phase PWM inverter-fed IMD.Each step will now be described.1)Evaluation of the impact of different inductive loads onthe switching performance.Here the gate drive boards of phase A are connected with the mother board to form a DPT circuit,and the switching performance of the phaseA lower switch is tested with the optimally designed loadinductor,7.5kW induction motor,and7.5kW induction motor plus2-m power cable.As shown in Fig.13,the switching performance differences in this step are only attributed to the inductive loads.For simplicity,PL-DPT, PL-IM,and PL-IM-PC refer to the test circuits with DPT load inductor,induction motor,and induction motor plus power cable,respectively.2)Evaluation of the interaction of phase legs on switchingperformance.The gate drive boards of phases B and C are added to the mother board to establish a three-phaseZHANG et al.:EV ALUATION OF SWITCHING PERFORMANCE OF SIC DEVICES IN PWM INVERTER-FED INDUCTION MOTOR DRIVES5707Fig.14.Test circuits for evaluation of the impact of phase legs and heat sink on the switching performance:(a)3Φ-IM-1;(b)3Φ-IM-2;(c)3Φ-IM-3;and (d)3Φ-IM-HS-1.inverter,and the switching performance of the DUT is tested by turning ON the upper switches of phases B and C,as shown in Fig.14(a).Hence,compared with the switching behavior of the DUT with the induction motor in step1(i.e.,PL-IM),the impact of parasitics induced by phases B and C can be identified.Then,ac-cording to the modulation scheme,the switches of phasesB andC are controlled in different ON/OFF states dur-ing the switching transient of the DUT,as shown in Fig.14(b)and(c),to evaluate the impact of different inductive load connection structures on switching perfor-mance.For simplicity,3Φ-IM-1,3Φ-IM-2,and3Φ-IM-3 indicate the test circuits as shown in Fig.14(a),(b),and(c), respectively.3)Evaluation of the impact of the heat sink on switchingperformance.A common heat sink is attached with all the power devices in the three-phase inverter,and the switching behavior of the DUT is tested by controlling the upper switches of phases B and C to be on,as shown in Fig.14(d).Thus,in comparison with the switching per-formance of the DUT with the same ON/OFF states of the switches of phases B and C in step2(i.e.,3Φ-IM-1),the capacitive coupling effect induced by the heat sink can be identified.For simplicity,3Φ-IM-HS-1represents the test circuits in Fig.14(d).4)Evaluation of the impact of the induction motor rotationon the switching performance.The switching behaviors in the previous three steps are evaluated based on pulse test,which means that the motor is not rotating,although certain pulse currentsflow through the stator windings.In step4,the switching performance of the DUT is tested when the induction motor is rotating.Based on the same hardware setup as in step3,the difference of the switching performance under the motor running test and pulse test can be evaluated.Also note that the junction temperature variation of the DUT under the continuous operating con-dition will become another factor that impacts the switch-ing behavior.In this test,the low switching frequency of 5kHz and small ac RMS current of11A are selected to minimize active power loss.Also,the heat sink with forced air cooling is utilized for thermal management.Thus,the junction temperature rise of the DUT under no load operating condition for1to2min is insignificant.C.Experimental ResultsFig.15shows the comparison waveforms with three different inductive loads under the operating condition of600V/10A with 5-Ωgate resistance.As can be observed from the overall switch-ing waveforms during both turn-on and turn-off transients,there is a5.4MHz frequency ringing in the switching current with the5708IEEE TRANSACTIONS ON POWER ELECTRONICS,VOL.30,NO.10,OCTOBER2015Fig.15.Impact of different inductive loads on switching performance: (a)Turn-on transient;and(b)turn-off transient.induction motor,which corresponds to the resonance frequency created by the parasitics of the induction motor(see Fig.4). In addition,as predicted,during a turn-on transient,this low frequency ringing current is found from the drain current of the lower switch;while during a turn-off transient,itflows through the upper one.Also note that the ringing duration is up to1.5μs, which is much longer than the tens of nanoseconds’switching time,as shown in the zoomed-in switching waveforms.Further-more,as compared to the switching behavior with the DPT load inductor,the parasitics of the induction motor cause the turn-on and turn-off switching time to increase from26to29ns and32 to38ns,respectively.The total energy loss slightly increases as well.After inserting a2-m power cable between the inverter and motor,the switching performance becomes even worse:Switch-ing time increases up to42%during turn-on,and doubles during turn-off;an additional32%of energy loss is dissipated during the switching transient.More test results with different load currents and gate resis-tances are shown in Fig.16.In order to clearly demonstrate the impact of different inductive loads on the switching perfor-mance,the switching time t sw and energy loss E sw with induc-tion motor and motor plus power cable are normalized based on results with DPT load inductor,which are listed in Tables I and II.These results show that under different loadcurrents parison of t sw and E sw among different inductive loads under different I L and R g:(a)t sw dependence on I L;(b)t sw dependence on R g;(c)E sw dependence on I L;and(d)E sw dependence on R g.TABLE It sw AND E sw VERSUS I L U NDER DPT W ITH V D C OF600V AND R G OF5ΩI L(A)5101520t O N(ns)24262933t O F F(ns)51322928E s w(μJ)135200286398。
rohm p02sct3040kr-evk-001 sic mosfet for to-247-4l
TO-247-4LHalf-Bridge Evaluation Board Operation ManualNotice ＜High Voltage Safety Precautions＞◇ Read all safety precautions before usePlease note that this document covers only the SiC MOSFET for TO-247-4L evaluation board (P02SCT3040KR-EVK-001) and its functions. For additional information, please refer to the product specification.To ensure safe operation, please carefully read all precautions before handling the evaluation boardDepending on the configuration of the board and voltages used,Potentially lethal voltages may be generated.Therefore, please make sure to read and observe all safety precautions described inthe red box below.This evaluation board is intended for use only in research and development facilities and should by handled only by qualified personnel familiar with all safety and operating procedures.We recommend carrying out operation in a safe environment that includes the use of high voltage signage at all entrances, safety interlocks, and protective glasses.User’s GuideSiC MOSFET 评估板TO-247-4L 半桥评估板 使用说明书在SiC MOSFET 等功率元器件的评估中，一般会涉及到高电压和大电流，因此要求恰当地构建其评估环境。
ROHM P04SCT4018KE-EVK-001 第4代SiC MOSFET半桥评估板双脉冲测试模
2022. Sep65UG040E Rev.001 Double Pulse Test Simulation with P04SCT4018KE-EVK-001 Simulation Model<Getting Started>Table of Contents•Outlines•Simulation Circuit•Simulation Settings •Component List•PCB Pattern Parasitic Inductors •Analytical ToolsPlease visit ROHM Solution Simulator page•Hands-On User’s Manual Link•Tutorial Short Videos availableHow to use ROHM Solution Simulator(https:///solution-simulator)2022. Sep65UG040E Rev.001Figure 1. P04SCT4018KE-EVK-001This simulation circuit provides the double pulse test simulation environment of P04SCT4018KE-EVK-001, ROHM’s 4th Generation SiC MOSFET Half Bridge Evaluation Board“. The simulation circuit is composed of the detailed simulation model with the circuit board parasitic inductance to achieve higher switching waveform simulation accuracy.Features•Double pulse test circuit (High-side switching)•4th generation SiC MOSFET SCT4018KE + gate driver IC BM61S41RFV-C.•Device equivalent circuit model of the components are used for simulation accuracy. •Parasitic inductors of PCB patterns are modelled and applied to the simulation circuit.•Vgs, VDC, snubber circuit constants, etc. can be modified.•Approx. simulation elapsed time is 2min30s.Applications•By simulating and verifying the operating conditions and circuit constants of drive circuits, etc., the workload of hardware evaluation can be reduced.•By extracting the parasitic L of the pattern from the PCB layout and adding it to the circuit for simulation, it is possible to improve the problem before prototyping.•Simulation with the EVK detailed model may help to analyze the cause of noise surge surges observed in the hardware evaluation.Double Pulse Test Simulation with P04SCT4018KE-EVK-001 Simulation Model <Outlines>Note) For more details of P04SCT4018KE-EVK-001, please refer to the following documents.4th Generation SiC MOSFET Evaluation Board Product Specifications.pdf4th Generation SiC MOSFET Evaluation Board User’s Manual.pdf2022. Sep65UG040E Rev.001ParametersDescriptionsDefaultSimulationSetting RangeVDC DC Voltage 800 V HS_VCC2, LS_VCC2Gate drive positive voltage18 V 0 to 25 V HS_VEE, LS_VEE Gate drive negative voltage0 V 0 to 4 VTjQ51, Q151 Device Junction Temperature 25 °C HS_VPULSEHigh-side pulse period 10 μs Fixed High-side pulse width4.9 μsLS_VPULSE “L” (DC)Table 1. Parameter SettingsFigure 2. Simulation CircuitDouble Pulse Test Simulation with P04SCT4018KE-EVK-001 Simulation Model <Simulation Circuit>VDCD53VS1C66U2Q51C65HS_VPULSED54D57D58R74R75R76C302C303R307R308C301L1C64ep2q3ep2q4i2q1U102LS_VPULSEVS2HS_VCC2HS_VEEC59LVDD153R173D154C164LS_VCC2LS_VEEC159Q151C165D157D158R174R175R176i2q2C51C151P04SCT4018KE-EVK-001Simulation ModelLP2LLSVCC2LHSVCC2LP1LP3LP4R55R56LP5LP6LP7LP8LP9LP10R73LP11LP12LP13LP14C166LP15R155R156LP16LP17LP18LP19LP20LP21LP22LP23LP24LP25LP26LP27LP28LP29R321LP30LP31LP322022. Sep65UG040E Rev.001 Double Pulse Test Simulation with P04SCT4018KE-EVK-001 Simulation Model<Simulation Settings>Figure 3. Simplified Gate Drive Circuit (common for high-side and low-side)Figure 4. SiC MOSFET Vgs VoltageSiC MOSFETGate voltageSiC MOSFETDS voltageGDICGND2 voltage VEE = 2VVCC2 = 18VGDICVCC2 voltage1.Gate drive voltage VgsFigure 3 shows a simplified gate driver circuit, and Figure 4 shows an example of the Vgs waveform. The voltage source VEE gives the voltage of the DS pin of the SiC MOSFET with respect to the VEE2 voltage of the gate driver IC. The voltage source VCC2 gives the supply voltage VCC of the gate driver IC with respect to the DS pinvoltage. As a result, the gate voltage Vgs of the SiC MOSFET is VCC for 'H' voltage and (-VEE) for 'L' voltage. Set HS_VCC and HS_VEE for the high-side circuit, and LS_VCC and LS_VEE for the low-side circuit, respectively.2.Gate Drive Pulse timingVoltage source ‘HS_VPULSE’ generate the gate drive pulse timing. The period T = 5μs and the pulse width = 2.5μs. The actual gate drive pulse output is at the ‘out’ pin of BM61S41RFV-C, the gate driver IC.VgsVCC2=18VVEE=2V+++GDICSiCMOSFETSVCC2GATEVEE22022. Sep65UG040E Rev.001Double Pulse Test Simulation with P04SCT4018KE-EVK-001 Simulation Model <Simulation Settings>ing Property EditorTo open the Property Editor, right-click on a component and select "Properties" from the pull-down menu. Figure 5 shows an example of the Property Editor. You can browse the parameters of the component from the Property Editor.Components shown in blue have “tunable" parameters, and you can change the parameters in the white text box in the Property Editor. Apply the values within the displayed tolerance range.Figure 5. Property Editor Examples(a) Capacitor (b) Inductor2.‘USE_INITIAL_VOLTAGE’ and ‘USE_INITIAL_CURRENT’The capacitor property 'USE_INITIAL_VOLTAGE' and the inductor property 'USE_INITIAL_CURRENT' are used to improve the convergence of thesimulation and speed up the simulation. Initial voltage or initial current value will be applied to the component as the initial condition. It will improve simulation convergence.When changing simulation parameters, the initial voltage and the initial current should be revised.Table 2 shows the recommendation of the initial voltage and the initial current.Symbol Initial Voltage Recommendation C64, C164(-HS_VEE), (-LS_VEE)C66, C166(HS_VEE+HS_VCC2), (LS_VEE+LS_VCC2)C59, C159HS_VEE, LS_VEEC65, C165VDC C302, C303(VDC/2)C301VDCTable 2. Initial Voltage Recommendation2022. Sep65UG040E Rev.001Note) We have not been able to confirm operation with all combinations. Please read the disclaimer carefully.Symbol Part Number DeviceQ51, Q151SCT4018KE 4G-SiC MOSFET, 1200V, 18mohm D53, D54, D153, D154RB160VAM-60Schottky Barrier Diode D57, D58, D157, D158RFN1LAM7SSuper Fast Recovery DiodeU2, U102BM61S41RFV-C 1ch Gate Driver Providing Galvanic IsolationTable 4. Power Device / Gate Driver IC Component ListDouble Pulse Test Simulation with P04SCT4018KE-EVK-001 Simulation Model <Component List>SymbolR value [ohm]Tun-able CommentsR55, R155 3.3✓Gate resistorsR56, R1560✓R73, R173 4.7k R74, R75, R76, R174, R175, R17610✓RCD Snubber resistors R307, R3081M C Snubber resistors R3210.1mShunt resistorTable 6. Resistor Component ListPart Number of Q51 and Q151 are selectable from the property editor.The list of the part number is shown below.To change the MOSFET, see instruction ‘How to change MOSFET model’or refer to the hands-on manual from the link on Page 1.Symbol Part Number Features Q51, Q151SCT4018KE*1200V, 18mohm SCT4036KE1200V, 36mohm* Default device1. Right-click on the device2. Select “Properties”3. Pull down “SpiceLib Part”4. Select the productHow to change MOSFET Model1234Table 5. SiC MOSFET Part Number ListNote) The value is constant unless otherwise specified as ‘Tunable’.2022. Sep65UG040E Rev.001Note) We have not been able to confirm operation with all combinations. Please read the disclaimer carefully.Double Pulse Test Simulation with P04SCT4018KE-EVK-001 Simulation Model <Component List>SymbolCapacitor ValuesSimulation Settings DescriptionsC [F]ESR [ohm]ESL [H]Tun-ableInitial Voltage [V]Tun-ableUse Initial VoltageC51, C1510.1μ19.8m 0.37n 0C64, C1640.1μ19.8m 0.37n 0✓✓C66, C1660.1μ19.8m 0.37n 18✓✓C59, C159 4.7μ 3.2m 0.48n 0✓✓C65, C16533n12m0.65n✓800✓✓RCD Snubber capacitorsC302, C3030.47μ8.4m 0.65n ✓400✓✓ C Snubber capacitorsC30110μ9.9m11n✓800✓✓Table 8. Capacitor Component ListSymbolInductor ValuesSimulation SettingsDescriptionsL [H]PAR_RES [ohm]SER_RES [ohm]PAR_CAP[F]Tun-able Use Initial current= 0 OptionL1250μ51k0.132.124p✓✓DPT Inductive Load Table 7. Inductor Component ListFigure 5. Inductor ModelP1P2L SER_RESPAR_RESPAR_CAPP1P2ESLESRCFigure 6. Capacitor ModelNote) Refer to Figure 5 for the model composition.Note) The value is constant unless otherwise specified as ‘Tunable’.Note) Refer to Figure 6 for the model composition.Note) The value is constant unless otherwise specified as ‘Tunable’.2022. Sep65UG040E Rev.001Double Pulse Test Simulation with P04SCT4018KE-EVK-001 Simulation Model <PCB Pattern Parasitic Inductors>SymbolInductor ValuesSim Settings SERL [nH]SERR [mohm]Tun-able Initial Current = 0 OptionLP10.4205✓LP2 6.38231✓LP3 2.90012✓LP4 1.0325✓LP5 2.7077✓LP6 2.58315✓LP7 4.83225✓LP8 2.58310✓LP90.9365✓LP10 5.21020✓LP110.7964✓LP12 6.39032✓LP13 5.5816.5✓LP140.9816✓LP15 2.9297✓LP161.9389✓Table 9. EVK PCB Pattern Parasitic Inductor modelSymbolInductor Values Sim Settings SERL [nH]SERR [mohm]Tun-able Initial Current =0 OptionLP17 5.22026✓LP18 2.5259✓LP19 1.0695✓LP20 4.0228✓LP21 5.741133✓LP22 4.781165✓LP23 4.96717✓LP240.8563✓LP257.00028✓LP267.00028✓LP27 1.2122✓LP280.5757✓LP29 1.34721✓LP30 3.89166✓LP31 1.28768✓LP320.30616✓P1P2SERLSERR100ohmFigure 7. Parasitic L modelNote) Refer to Figure 7 for the model composition.Note) The value is constant unless otherwise specified as ‘Tunable’.Note) The inductor models are defined from the analysis of the PCB pattern design data and the accuracy is not guaranteed. LP1 through LP32 are PCB pattern inductor models.These are defined from the electro-magnetic analysis of the PCB pattern layout and applied to the simulation circuit as discrete components. Figure 7 shous the model equivalent circuit. The resister of 100 ohm in parallel is for stabilizing simulation.You can modify these inductors, for example, referring to the layout design constraints to relatively evaluate how the pattern layout would affects the switching behaviors.2022. Sep65UG040E Rev.001loss_out t =v t ×i_sense tloss_integ_out t =න0tloss_out t dt* v t : voltage difference between p1 and p2Analytical tools are used in the simulation circuit for current sensing and device loss calculation.Note) The Loss_calc component is a utility module to support power loss calculation, and does not affect the simulation results of circuit operation or performance.Double Pulse Test Simulation with P04SCT4018KE-EVK-001 Simulation Model<Analytical Tools>Figure 8. Current to Continuous QuantityFigure 9. Loss_Calc31.Current Sensing ToolThe component ‘Current to Continuous Quantity’ outputs the current flow ‘p1’ through ‘p2’ (See Figure 8.)It is used to measure the drain current of the SiC MOSFET.2.Device Loss Calculation ToolThe component ‘Loss_Calc3’ calculates the voltage difference between ‘p1’ and ‘p2’, and outputs the products of the voltagedifference and ‘i_sense’ current input as ‘loss_out’ and its integration as ‘loss_integ_out’ (See Figure 9.)NoticeROHM Customer Support System/contact/Thank you for your accessing to ROHM product informations.More detail product informations and catalogs are available, please contact us.N o t e sThe information contained herein is subject to change without notice.Before you use our Products, please contact our sales representative and verify the latest specifica-tions :Although ROHM is continuously working to improve product reliability and quality, semicon-ductors can break down and malfunction due to various factors.Therefore, in order to prevent personal injury or fire arising from failure, please take safety measures such as complying with the derating characteristics, implementing redundant and fire prevention designs, and utilizing backups and fail-safe procedures. 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ROHM shall have no responsibility whatsoever for any dispute arising out of the use of such technical information.The Products specified in this document are not designed to be radiation tolerant.For use of our Products in applications requiring a high degree of reliability (as exemplifiedbelow), please contact and consult with a ROHM representative : transportation equipment (i.e. cars, ships, trains), primary communication equipment, traffic lights, fire/crime prevention, safety equipment, medical systems, servers, solar cells, and power transmission systems.Do not use our Products in applications requiring extremely high reliability, such as aerospaceequipment, nuclear power control systems, and submarine repeaters.ROHM shall have no responsibility for any damages or injury arising from non-compliance withthe recommended usage conditions and specifications contained herein.ROHM has used reasonable care to ensur e the accuracy of the information contained in thisdocument. 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sic mosfet双脉冲测试原理
双脉冲测试是广泛应用于MOSFET和IGBT等功率开关元件特性评估的一种测试方法。
在“通过双脉冲测试评估MOSFET的反向恢复特性”中，双脉冲测试原理如下：
首先给SiC MOSFET（S2）栅极发送一个宽驱动脉冲，S2开通，此时电感L电流开始线性上升，该过程用来建立测试用电感电流。
在实际测量时可以根据具体侧测试电流指标调节脉冲的宽度。
然后，上管两端并接一个电感，就可以测试出下管的特性以及上管的反向二极管特性。
最后，在第一个脉冲信号来临之前，电感电流为0，SiC MOSFET阻断并承受直流母线电压。
直到t1时刻，器件开始导通，电感电流按照式规律变化，即随时间按线性规律增加。
式中VDS（on）—SiC MOSFET导通压降；t2时刻，开关管开始关断并换流至二极管D1，流经开关管的电流变为0，负载电感的电流经过二极管D1续流。
由于续流阶段电流回路存在一定的电阻，电流将会有一定程度的减小，但此阶段极短，而且寄生电阻量很小，因此电流减小量可以忽略，近似认为t2和t3时刻电流相等。
t3时刻，第二个脉冲信号使开关管开通，续流二极管开始关断，电感电流换流至开关管并继续按照线性规律增加。
t4时刻，开关管再次关断，电流从开关管换流至续流二极管D1，双脉冲测试结束。
sic mosfet驱动及保护电路设计
撒电机MICROMOTORS第52卷第12期2019年 12月Vol. 52. No. 12Dec. 2019SiC MOSFET 驱动及保护电路设计柳舟洲(西安微电机研究所，西安710077)摘 要：SiC MOSFET 器件具有高耐压、低导通电阻、高频等优良特性，工业应用中具有明显优势，发展快速。
本文首先阐述了 SiC MOSFET 主要特性，分析了驱动电路的特点，并给出了基于分立器件的驱动及保护电路设计。
基于CREE 公司最新第三代器件，设计了驱动电路，并通过双脉冲电路及桥臂直通电路测试验证所设计的SiC 器件门极驱动电路参数及短路保护电路参数的准确性和合理性。
关键词：SiC MOSFET ； |'1极参数；双脉冲测试；桥臂直通短路中图分类号：TP272 文献标志码：A 文章编号：1001-6848(2019)12-0070-04Design of SiC MOSFET Driver and Protect CircuitLIU Zhouzhou(Xi' an Micromotor Research Institute , Xi 1 an 710077 , China )Abstract : SiC MOSFET devices have high voltage , low on ・resistance , high frequency and other excellentcharacteristics. SiC MOSFET develops rapidly in industrial application with obvious advantages. The design of driving function circuit based on discrete devices were given. Based on the latest third generation devices ofCREEE , the driving circuit was designed. The accuracy of driving parameters and characteristics for gate driv ing circuit of SiC device were verified by double pulse circuit test and ami shoot through short circuit test. Key words : SiC MOSFET ； driving parameters ； double pulse circuit test ； arm shoot through short circuito 引言SiC （碳化硅）是一种由硅（Si ）和碳（C ）构成的宽禁带半导体材料，绝缘击穿场强是Si 的10倍，带隙 是Si 的3倍，被认为是一种超越Si 极限的功率器件用材料。
基于重新定义t_(doff)的SiC MOSFET结温估计方法
第55卷第5期2021年5月电力电子技术Power ElectronicsVol.55, No.5May 2021基于重新定义的SiC MOSFET结温估计方法郑磊，杜明星(天津理工大学，天津市复杂系统控制理论及应用重点实验室，天津300384)摘要：碳化硅（SiC)金属-氧化物半导体场效应晶体管（M0SFET)结温的精准估计是其损耗计算、寿命预测与可靠性评估的重要基础。
SiC M0SFET的结温估计常采用热敏感电参数法，该方法具有快速响应与高准确度等优点。
首先研宄了SiC MOSFET关断阶段的电气行为特性，并重新定义了关断延迟时间的区间。
其次，分析重新定义的关断延迟时间与温度的理论关系，进而证明相比于传统定义下的关断延迟时间，重新定义的关断延迟时间具有更为优良的温度特性。
最后，提出以重新定义的关断延迟时间作为热敏感电参数的SiC M0SFET结温在线估计方法。
实验结果表明，提出的方法具有较高的测量精度。
关键词：金属-氧化物半导体场效应晶体管；结温；关断延迟时间中图分类号：TN32 文献标识码：A 文章编号：1000-100X(2021)05-0153-04Junction Temperature Estimation Method of SiC MOSFETBased on RedefinedZ H E N G Lei, D U Ming-xing(T ia n jin K e y L a b o ra to ry o f C ontrol T h eo ry &A p p lic a tio n s in C o m p lic a te d S y s te m T ian jin tT ia n jin U n iv e rsity o f T e c h n o lo g y, T ia n jin300384, C h in a)Abstract：The accurate estimation of the junction temperature of silicon carbide (SiC) metal-oxide semiconductor field effect transistor (MOSFET) is an important basis for its loss calculation, life prediction and reliability evaluation. T he junction temperature estimation of SiC MOSFET commonly used thermal sensitive electrical parameter method, which has the advantages of fast response and high accuracy.Firstly, the electrical behavior characteristics of the SiC MOSFET during the turn-off phase are studied,and the turn-off delay time interval is redefined.Secondly,the theoretical relationship between redefined turn-off delay time and temperature is analyzed.Furthermore, it proves that redefined turnoff delay time has better temperature characteristics than traditionally defined turn-off delay time. Finally, an online es- timation method of junction temperature with redefined turn-off delay time as thermally sensitive electrical parameter is proposed in SiC MOSFET.Experimental results show that the proposed method has high measurement accuracy. Keywords ：metal-oxide semiconductor field effect transistor；junction temperature；turn-off delay timeFoundation Project ： Supported by National Key Research and Development Program( No.2017YFB0102500)l引言尽管SiC材料具有更加优良的热特性，但传 统封装散热的局限性及SiC材料较高的热导率和 杨氏模量，将迫使SiC MOSFETIU在运行过程中承 受更大的热应力。
抑制SiC MOSFET瞬态电压尖峰的改进驱动电路设计
创新前沿科技创新与应用Technology Innovation and Application2021年14期抑制SiC MOSFET 瞬态电压尖峰的改进驱动电路设计王文月1，牛萍娟2（1.天津工业大学电气工程与自动化学院，天津300000；2.天津工业大学电子与信息工程学院，天津300000）近些年，随着电力电子技术的发展，航空、电动汽车、新能源发电及石油钻井等领域对电力电子变换器提出更高的要求，即实现高压、高频、高功率密度[1]。
因此以SiC MOSFET 为代表的宽禁带半导体器件因其高开关速度、高开关频率及高热导率等[2-5]，受到人们广泛关注。
然而随着SiC MOSFET 开关频率及速度提高，电力电子变换器受电路中寄生参数影响加剧，关断瞬态电压尖峰更为严重。
瞬态电压的尖峰不仅危及开关管的安全，也会降低电力电子变换器的功率密度，加剧电力电子变换器电磁干扰[6-8]。
目前现有抑制电压尖峰方法大多牺牲了开关速度，从而影响SiC MOSFET 开关损耗及变换器效率等。
因此，本文在分析电压尖峰产生原理基础上，在注入栅极电流抑制电压尖峰前提下，提出了一种在栅源极增加有源箝位电路的改进驱动方法，改进后的驱动电路具有抑制尖峰效果好、开关损耗较小、控制方法简单特点。
本文首先分析瞬态电压尖峰产生原理，其次分析了改进驱动电路工作原理，最后在双脉冲测试平台验证了该改进驱动电路的实用性。
1SiC MOSFET 瞬态电压尖峰产生原理为了分析SiC MOSFET 瞬态电压尖峰产生原理，采用如图1所示测试电路，图中：V dc 直流母线电压，R 驱动电阻，C 支撑电容，L 负载电感，SiC MOSFET 及SiC 二极管D 1，考虑SiC MOSFET 关键寄生参数为：栅极驱动电阻R 1，栅极引脚封装电感L g ，源极引脚封装电感L s ，漏极引脚封装电感L d 。
为了方便分析，L g 、L s 与L d 分别为SiCMOSFET 各引脚封装电感与相连接引线电感之和。
SiC MOSFET模块结温监测研究
第19卷第3期电 源学报Vol. 19 No. 3 2021年5 月Journal of Power Supply May 2021 DOI：10.13234/j.issn.2095-2805.2021.3.169 中图分类号：T M23文献标志码：ASiC MOSFET模块结温监测研究李凌云 '何芹芹\黄德雷3(1.江苏省宿迁经贸高等职业技术学校，宿迁223600; 2.江苏科技大学电子信息学院，镇江212003;3.中国矿业大学电气与动力工程学院，徐州221116)摘要：碳化硅金属氧化物半导体场效应管SiC M O S F E T(silicon carbide metal oxide semiconductor field effect transistor)以其优异的材料特性成为一种很有前景的高功率密度和高效率器件，而结温是其设计和工作的一个重要参数，也是健康状态的重要指标。
为了状态监控的需求,提出一种受自热影响较少的基于准阈值电压的结温提取方法。
首先，从理论层面证实了阈值电压V th与温度有良好的线性关系，具有负的温度敏感度。
然后，实验观察了外部驱动电阻R〇e x t对V h的影响。
最后，结合智能驱动提出了获取准阈值电压的电路，实验结果证实了所提方法的可行性。
关键词：结温提取；碳化硅（SiC);金属氧化物半导体场效应管（M O S F E T);阈值电压Study on Junction Temperature Monitoring of SiC MOSFET ModuleLI Lingyun1,2,HE Qinqin1,HUANG Delei3(1. Suqian Economic and Trade Higher Vocational Technical School of Jiangsu, Suqian 223600, China; 2. School of Electronics and Information, Jiangsu University of Science and Technology, Zhenjiang 212003, China; 3. School of Electrical and Power Engineering, China University of Mining and Technology, Xuzhou 221116, China)Abstract： Owing t o i t s excellent material properties, silicon carbide metal oxide semiconductor field effect tra-nsistor (SiC M O S F E T) i s becoming a promising device with high power density and high efficiency. As an important design and operating parameter, junction temperature i s also an important indicator of health status. For the purpose of state monitoring,a junction temperature extraction method based on quasi-threshold voltage was proposed in this paper, which i s less affectedby self-heating. F i r s t, i t was theoretically and experimentally proved that the threshold voltage V t h showed a good linearity with temperature, and this relationship had a negative temperature s e nsitivity. Then, the effect of external drive resistor R G e x t on V t h was observed experimentally. Finally, the circuit for obtaining the quasi-threshold voltage was put forward in combination with the intelligent drive, and the feasibility of the proposed method was verified by experimental r e s u lts.Keywords: junction temperature extraction; silicon carbide (SiC); metal oxide semiconductor field effect transistor (M O S F E T); threshold voltage近年来，碳化硅SiC(silicon carbide)功率器件 以其优异的材料特性受到电力电子行业的广泛关 注。
碳化硅MOSFET并联均流的研究
碳化硅MOSFET并联均流的研究Investigation of current sharing of paralleling SiC MOSFET王珩宇1，吴新科1，郭清1，盛况1（1浙江大学电气工程学院，杭州310027）摘要：碳化硅（SiC）材料是一种新型宽禁带半导体材料。
本文对SiC MOSFET这一种新型器件的并联均流情况进行了研究，其中搭建了双脉冲测试平台来对两路器件进行测试，并利用此平台随机选取了两块SiC MOSFET 分别在静态和动态情况下观察了其均流情况，同时还在相同条件下测试了Si IGBT以进行对比。
通过实验测试与分析，本文认为目前SiC MOSFET器件的离散度较大，同时动态不均流问题在开关速度较快（比如di/dt高达20A/ns）的情况下会加重。
Abstract: SiC is a new kind of wind band gap material. This paper investigated the current sharing of paralleling SiC MOSFET. A double pulse tester was built to test two paralleling branches. With this tester, a careful experiment was performed to examine current sharing of 2 random SiC MOSFET chips statically and dynamically. For comparison, two Si IGBT chips were tested under the same circumstances. Through experiment and analysis, it was found that the uniformity of SiC MOSFET is not as good as the Si IGBT and the problem of current sharing is exacerbated when the devices switch faster (for instance, di/dt up to 20A/ns).关键词：碳化硅MOSFET 双脉冲测试并联均流Key words：SiC MOSFET, Double pulse test, Current sharing1 引言近年来，出现了许多新型宽禁带半导体材料，包括SiC、GaN等。
SiC MOSFET模块的硬并联
THE WORLD OF INVERTERS《变频器世界》May,2020 SiC MOSFET模块的硬并联Hard Paralleling for SiC MOSFET Modules英飞凌科技(中国)有限公司郑姿清(Zheng Ziqing)摘要：以对称的布板设计来实现4个6臺欧的碳化硅模块的并联，给出了实际的测量结果。
最后还通过门特卡罗分析来演绎批量器件应用在并联场合下的温度偏差。
由此可以看出碳化硅MOSFET并联使用的可行性。
关键字：碳化硅；并联；双脉冲测试Abstract:There are4pcs6mohm SiC module paralleling with symmetrical layout design and the test result is given. Fin a lly,a Monte Carlo analysis is used to demonstrate the effects on the temperature sharing due to production spreads in device parameters.So,it is possible to do SiC module paralleling.Keywords:SiC;Paralleling;Double pulse test［中图分类号】TN325+.2【文献标识码】B［文章编号】1561-0330(2020)05-087-031引言用硅IGBT的工程师们很多曾经有过并联器件的使用经历，它不仅能降低成本还能减小整体系统分布电感。
那么对于新一代的半导体器件SiC而言，是否一样可以并联使用呢？以下就以4个英飞凌6mohn!的SiC模块的硬并联为例，来一超看看实现的可行性。
2四个并联模块分析2.1均流类型任何的同一料号开关器件并联，均流总是最重要的目的，这关系到整个系统的最终功率等级，所以如何做到均流就会是一个挑战。
一种大功率SIC MOSFET模块键合线健康状态检测方法及装置[发明专利]
![一种大功率SIC MOSFET模块键合线健康状态检测方法及装置[发明专利]](https://img.taocdn.com/s3/m/6a6f2cc04793daef5ef7ba0d4a7302768e996fa8.png)
(19)中华人民共和国国家知识产权局(12)发明专利申请(10)申请公布号 (43)申请公布日 (21)申请号 202010526758.4(22)申请日 2020.06.10(71)申请人 徐州中矿大传动与自动化有限公司地址 221116 江苏省徐州市高新区第二工业园珠江路7号(72)发明人 谭国俊 耿程飞 朱春宇 张经伟 (51)Int.Cl.G01R 31/26(2014.01)(54)发明名称一种大功率SIC MOSFET模块键合线健康状态检测方法及装置(57)摘要本发明公开了一种大功率SIC MOSFET模块键合线健康状态检测方法及装置，该方法包括建立SIC MOSFET模块V peak ,sS健康参考值基准数据库；在关断瞬态，同时获取SIC MOSFET模块关断暂态漏极电流I D 和SIC MOSFET模块辅助源极s、功率源极S之间的感应电动势V sS ，并测量出该感应电动势V sS 的峰值V peak ,sS ；将健康参考值V peak ,sS健康与峰值V peak ,sS 进行比较，计算出偏差值；根据偏差值，判断SIC MOSFET模块键合线是否存在脱落故障。
该方法实现了SIC MOSFET模块在线健康状态评估，能够有效避免因为键合线老化带来的安全问题，实现设备的可预测性维护。
权利要求书2页 说明书5页 附图5页CN 111781482 A 2020.10.16C N 111781482A1.一种大功率SIC MOSFET模块键合线健康状态检测方法，其特征在于，所述方法包括，建立SIC MOSFET模块V peak,sS健康参考值基准数据库；在关断瞬态，同时获取SIC MOSFET模块关断暂态漏极电流I D和SIC MOSFET模块辅助源极s、功率源极S之间的感应电动势V sS，并测量出该感应电动势V sS的峰值V peak,sS；将健康参考值V peak,sS健康与峰值V peak,sS进行比较，计算出偏差值；根据偏差值，判断SIC MOSFET模块键合线是否存在脱落故障；其中，所述健康参考值V peak,sS健康和感应电动势V sS的测量峰值V peak,sS，在相同电流信号I D下进行比较。
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SiC MOSFET 双脉冲测试装置
2011 年 2 月
SiC MOSFET 双脉冲测试装置
Bob Callanan ，Cree Inc
W R -A N 09，R E V -C M O S F E T
双脉冲测试装置 - 2011 年 2 月本文描述了一种双脉冲测试装置，它适合用于确定碳化硅 (SiC) MOSFET 的特征。
该装置是一个课本大小的双脉冲测试器，它将所有关键元件都布置在单块印刷电路板上，以提供可重复的测量。
测试装置的照片如图 1 所示。
测试器的原理图如图 2 所示。
该测试装置包含用于 MOSFET 的测试座 (J6)、栅极驱动器 (U1)、电容
组 (C1-C9)、续流二极管 (D1)，以及一个紧密集成的双级电流互感器 (T1)。
可以通过 BNC 接头 (J7 & J10) 监测 VDS 和 VGS 。
这些接头的目的不是为了使用同轴电缆，而是使用同轴电缆来探测转接器，以免需要探头接地线夹。
这样，就避免了接地线夹电线的寄生电感妨碍电压测量的情况。
漏极电流用一个双级电流互感器来测量，该互感器包含一个小的 1:10 铁氧体第一级互感器，以及一个 Pearson Electronics 2878 型电流传感器用于第二级。
得到的比例因子是 1V=100A 。
使用九个聚丙烯薄膜电容器 (C1-C9)，为测试器提供低电感电压源。
VCC 、GND 和 –VEE 是栅极驱动器的输入电压。
VCC 设置栅极脉冲高电压的值，VEE 设置栅极脉冲低电压的值。
VCC 和 –VEE 之间的最大电压为 30V 。
驱动脉冲应用于脉冲发生器输入 BNC 接头。
建议使用 +10 到 +12V 的脉冲来导通栅极脉冲。
此输入端接到 50 Ω 电阻，以匹配 50 Ω 同轴电缆。
端接电阻器 (R3 和 R4) 具有最大 0.5 W 的总额定功率，因此必须适当地限制输入脉冲占空系数 (~10%)，以避免它们烧掉。
电感器跨“低负载” (LOAD LOW) 和“高负载” (LOAD HIGH) 端子连接。
推荐的电感值为大约 850 µH 。
可以用一个空芯电感器来实现该电感值，方法是将单层 107 圈的 AWG 18 磁力线，绕在长度为 4”Schedule 40 PVC 管 (外径 = 4.5”) 上。
图 1：SiC MOSFET
双脉冲测试器
URN
VCC
GND
-VEE
EXTERNAL INDUCTOR CONNECTIONS
图 2：SiC MOSFET 双脉冲测试器原理图
测试器顶部的照片如图 3 所示。
也可以选择将 BNC 接头安装在板的顶部或底部。
本例中，BNC 接头安装在背侧，以使 ThermoStream 测试头能放置在被测器件的上方。
(请注意，当将 BNC 接头安装在背侧时，请勿使接头与 PCB 齐平，否则可能发生短路，可使用一个临时垫片来辅助安装)。
所有电源连接都是采用香蕉插头，可以从电路板的顶部一侧或底部一侧插入。
图 3：SiC MOSFET 双脉冲测试器顶视图
测试器的底部一侧如图 4 所示。
大部分板元件都是安装在板的背部。
D1 安装在一个端子台中，因此可以移除并替换成电阻器，以进行探头偏移校正。
所示的跳线是在原理图中标示的跳线，用于 VDS BNC 接头的中心引脚。
请注意，栅极驱动器板是上下颠倒安装的。
双级电流互感器 (T1) 安装在底部。
Pearson 电源传感器的输出连接到 SMA-SMA 转接器，然后连接到 SMA - BNC 闷头转接器，后者再连通至顶部一侧。
BNC 接头安装
图 4：SiC MOSFET 双脉冲测试器底视图
第一级电流互感器的详细视图如图 5 所示。
该互感器的结构是，10 圈 AWG 26 规格的实心铜质 Teflon 绝缘线，缠绕在一个 Ferroxcube TC9.5/4.8/3.2-3E27 铁氧体环状线圈上。
中心导体是适合于 1.5 kV 测试的强绝缘 AWG 22 总线。
图 6 显示了栅极驱动器板。
该板是“碳化硅隔离式栅极驱动器”应用说明 CPWR-AN10 中所描述的隔离式栅极驱动器板的修改版本。
该板经过修改，可省略 DC-DC 转换器，允许直接连接到栅极驱动电源。
请注意，插座头安装在板的顶部一侧，使板能上下颠倒安装。
图 5：T1 第一级细节
图 6：隔离式栅极驱动器板， 移除和省略了 DC-DC 转换器
要精确测量，必须校正电压和电流探头，以确保所有延迟均相同。
电压探头的校正比较容易，只需将两个探头都连接到一个脉冲发生器输出，并在示波器上调节通道补偿，使得两个脉冲时间同步。
VDS和 ID探头的偏移校正方法是移除电感器，并将二极管 D1替换成低电感的 100 Ω电阻器。
推荐使用 Caddock MP930-100-1%或等效电阻器。
偏移校正过程中必须小心，确保将 VDD设置到低于电阻器最大额定脉冲的水平。
上述电阻器的最大值是 250V。
双脉冲栅极驱动的示例波形如图 7 所示。
MOSFET VDS 和 ID 相应的示例波形如图 8 所示。
该脉冲列由两个脉冲组成，重复频率为大约 1-2 Hz。
第一个脉冲 (~ 22 µsec) 用来建起电感器中的电流。
根据所需的测试电流调节宽度。
当此脉冲终止后，ID 从 MOSFET 换向至续流二极管。
此转换过程用来测量 MOSFET 的关断特性。
第一个和第二个脉冲之间有大约 3 µsec 的延迟。
此延迟的持续时间设置得足够长，使电压和电流趋于稳定，如果该测试装置用来评估 Si IGBT，可能需要将时间设置得更长，以确保足以让拖尾电流稳定下来。
第二个窄脉冲 (~ 2 µsec) 在数微秒后发生。
在此转换过程中，电流从续流二极管换向回到 MOSFET，且在该点上测量 MOSFET 的导通特性。
图 7：示例栅极驱动脉冲 图 8：示例波形
导通时 VDS 和 ID 的示例波形如图 9 中所示。
请注意，导通期间会出现非常少量的电流过冲。
这是因为，与高速硅 PiN 二极管相比，SiC JBS 二极管中存储了非常少量的电荷。
关断时 VDS 和 ID 的示例波形如图 10 中所示。
在 VDS 和 ID 中均观察到振荡，这通常不会在硅 IGBT 中观察到。
原因是 SiC MOSFET 没有电流拖尾。
图 9：导通波形 图 10：关断波形
产生振荡的原因是，SiC MOSFET 的输出电容与高电流路径中杂散电感产生谐振。
硅 IGBT 中的电流拖尾会使这种振荡衰减。
请注意，用来测量 VGS 的接头仅是为了便于设置栅极脉冲电压电平。
从该特定点观察到的实际 VGS 波形，将包含栅极键合线电感的电压降、源极键合线电感的电压降，以及实际 VGS 电压的电压降。
所以，当测量高电流脉冲时，该测试点观察到的电压将具有额外的过冲/下冲，这是由上述键合线电感的电压降造成的。
SiC MOSFET 双脉冲测试装置
2011 年 2 月
双脉冲测试器的物料单如表 1 所示。
Gerber 文件可在以下网址找到：
/products/power/doublepulsefixture.zip。
Array
表 1：物料单。