引脚表
CC2530引脚图表
P0_1
数字I/O
端口0.1
19
P0_0
数字I/O
端口0.0
20
RESET_N
数字输入
复位，低电平有效
21
AVDD5
电源（模拟）
2V—3.6V模拟电源连接
22
XOSC—Q1
模拟I/O
32MHz晶振引脚1或外部时钟输入
23
XOSC—Q2
模拟I/O
32MHz晶振引脚2
24
AVDD3
电源（模拟）
2V—3.6V模拟电源连接
端口1.1
10
DVDD2
电源（数字）
2V—3.6V数字电源连接
11
P1_0
数字I/O
端口1.0—20mA驱动能力
12
P0_7
数字I/O
端口0.7
13
P0_6
数字I/O
端口0.6
14
P0_5
数字I/O
端口0.5
15
P0_4
数字I/O
端口0.4
16
P0_3
数字I/O
端口0.3
17
P0_2
数字I/O
端口0.2
2V—3.6V数字电源连接
40DΒιβλιοθήκη OUPL电源（数字）1.8V 数字电源去耦，不使用外部电路供应
25
RF_P
I/O
RX期间负RF输入信号到LNA
26
RF_N
I/O
RX期间正RF输入信号到LNA
27
AVDD2
电源（模拟）
2V—3.6V模拟电源连接
28
AVDD1
电源（模拟）
2V—3.6V模拟电源连接
DE2-115所有引脚分配表
表1 拨动开关引脚配置
表2 按钮开关引脚配置
表3 LED 引脚配置
表4 七段数码管引脚配置
表5 时钟信号引脚配置信息
表6 LCD 模块引脚配置
表7 HSMC 接口引脚配置
表8 GPIO 引脚配置信息
表9 扩展接口引脚配置信息
表10 ADV7123 引脚配置
表11 音频编解码芯片引脚配置
表12 RS-232 引脚配置
表13 PS/2 引脚配置
表14 千兆以太网芯片引脚配置
表15 TV 解码芯片引脚配置
表16 USB (ISP1362)引脚配置
表17 IR 引脚配置
表18 SRAM 引脚配置
表19 SDRAM 引脚配置
表20 SDRAM 引脚配置
表21 Flash 引脚配置
表22 EEPROM 引脚配置
表23 SD 卡插槽引脚配置。
180个CPU引脚功能表
CPU型号待机控制电源电压时钟振荡复位音量控制亮度控制对比度控制M491269 7 8 915M494B13839 25 26 343128 M37100M8-581251 28 29 272M37102M85864 30 31 295587 M50124SA1021 2 3 234140M50161-554SP23 24 25 2619M50163-150SP3121 2 3 234140M50430-581SP1 9 10 627M50431-101SP2742 1 2 36282923M50431-513SP2742 1 2 362829M50432-551SP3042 33 34 161412M50433-531SP161 33 34 1127M50435-893FP141 33 34 1127M50453-101SP2742 1 2 362829M50436-560SP952 28 29 2724M50436-582SP652 28 29 27M50436-683SP652 28 29 273M50436-5652 28 29 2743CPU型号待机控制电源电压时钟振荡复位音量控制亮度控制对比度控制M50436-688SP652 28 29273M50436-602SP1052 28 29 2724M34300N4-011SP3042 34 35 7101213 M34300N4-012SP3042 34 35 7101213 M34300N4-551SP142 34 35 71011M34300N4-657P142 34 35 7101112 M37103M4-655SP421 28 29 2723839 M34300N4-555SP3042 34 35 7101112 M34300N4-584SP3342 34 35 71312M34300N4-585SP3342 34 35 7131210 M34300N4-587SP3342 34 35 7131210 M34300N4-624SP1742 34 35 7101213 M34300N4-628SP1742 34 35 7101213 M34300N4-721SP1742 34 35 7101213 M37210M3-508SP2127 24 25 30357 CPU型号待机控制电源电压时钟振荡复位音量控制亮度控制对比度控制CH050024142 31 32 33235 CHT0406712 10 11 17CHT08034142 31 32 33CHT0807742 31 32 33CHT08084142 31 32 33CKP100S1734 31 32 33245 CKP1004S2042 31 32 332CKP1101S3834 31 32 3365 CKP1103S3834 28 29 3365 CTV222S.PRC14142 31 32 33235CX519004P1021 2 3 234140CX85116B-621S64 34 35 3662CX513-512P1 9 10 6CX522-054241 22 23 24CX523-110P1721 2 3 364140 CXP80420-134S376434 35 3652CXP80420-139S376434 35 365 6CXP80424-165S376434 35 369 10CXP85332-5123734 35 36PCA84C440/401414231 32 33235 CPU型号待机控制电源电压时钟振荡复位音量控制亮度控制对比度控制PCA84C640/019 414231 32 33235 PCA84C841/177414231 32 33235 PCF84C644194231 32 33263 P87C766414231 32 33IX0237CE201412 13 41716 IX0411CEN1521 2 3 234140 IX0442CE143024 25 2619IX0605CE19 10 6IX0933CE16133 34 1127IX0981CE74240 41 136IX1194CE74240 41 136IX1830CE586430 31 297108 IX2321CE322724 25 30853 IX2372CE466430 31 29IX2504CE222724 25 30LC863316A71210 11 175LC864512A-5C7771210 11 17392332 CPU型号待机控制电源电压时钟振荡复位音量控制亮度控制对比度控制LC864516AN 71210 11 17392331 LC864525A71210 11 17392332 LC864916A71210 11 16262829 SAA129352 1 6 4341011 SC430402CFC1457 59 71ST6315624025 26 24393638 ST6367B1/FEJ374231 32 33534 ST6378B4/FR1374231 32 3353CH04001-5B41813 40 11 12 16363433 CH04001-5553813 40 11 12 16363433 CH04001-5C25813 40 11 12 16363433 CH0403-5H61712 21 10 11 17392332 CH04801-5F43712 21 10 11 17392332 CH05001414231 32 33235 CTV591S.GW3414231 32 33CXP80424-146376434 35 36CXP85332-1083763 64 34 35 36CPU型号待机控制电源电压时钟振荡复位音量控制亮度控制对比度控制LA86C3348A 71210 11 17LC863320A71210 11 175LC86332471210 11 178LC863328A-5T4571210 11 175LC863348A71210 11 175LC864012L-571181311 12 16363433 LC864512V-5D18712 21 10 11 172332 MN181768212940 41 3414MN1874876TSH332262 63 5416TMS73C167105443 44 454TMP47C834N-R12284231 32 33TMP87CH36N344231 32 332TMP87CM36N-3649344231 32 332TMP87CK36N344231 32 332TMP87CX38N204231 32 33TMP87CP38N74231 32 33TMP87CH38N74231 32 33CPU型号待机控制电源电压时钟振荡复位音量控制亮度控制对比度控制TMP87PS38N74231 32 33TMP87CK38N184231 32 334TMP87CS38N84231 32 336ST6368B4/FHO374231 32 33534 ST638837531 32 33P87C7701938 39 41 42 43P83C266BDR 3 41 28 30 31 32 3312ONWA KWEC 852 2 3 444WH2000C413431 32 33KONKA266142831 32 332KS88C8324423431 32 33Z8933212PSC183431 32 33Z90231353431 32 336CCU-2070-LDTV-06A282714Z86227-SR128532147 8 9403739 Z90103-JX-232147 8 9403738 Z90361383431 32 33CPU型号待机控制电源电压时钟振荡复位音量控制亮度控制对比度控制M37210M3-800SP2127 24 25 30357 M37210M3-902SP2127 24 25 30357 M37210M4-650SP27 24 25 30834 14-688SP M37210M4 3127 24 25 3010M37210M4-705SP2127 24 2530357 M37211M-609SP2227 24 2530356M37222M6-B80SP742 31 32 33M34302MB-612SP652 28 29 27213 M37210M3-010SP2127 24 25 30357 M37204MB-852SP5864 30 31 29M37103M4-750SP421 28 29 2723839 M37102M8-503SP5864 30 31 2971213 M37102M8-509SP4464 30 31 2987 M37220M32622 19 20 253415151TWE291 44 45 7163938 MN15151TMN1871611TKA622 62 63 54452524 MN1872432TWI33 22 61 62 63 54452524 CPU型号待机控制电源电压时钟振荡复位音量控制亮度控制对比度控制MN1874033TNW3322 61 62 63 542419 MN152810TTC329144 45 716MN152811TZX24135 36 716MN1871675T6S352262 63 54MN187******** 41 3415245KWC214240 41 83432MN15245S14821JTB7118 19 222MN14821TMN15142TEAI63937 38 83230MN15282 MN15287 852 2 3 4444846 TMP47C433AN84231 32 3324TMP47C430N272822 23 212TMP47C434N224231 32 33243 TMP47C837N224231 32 33465 TMP43238135A144224 25 232018TMP47C1638AU353315442 43 442TMP47C634AN224231 32 33243 TMP47C1238ANU068105442 43 44TMP87PM36N344231 32 332CPU型号待机控制电源电压时钟振荡复位音量控制亮度控制对比度控制TMP73C4715133 34 32393836 TMP87CM38N74231 32 33TMP87CH33N194231 32 33132 TMP47C834N-R12284231 32 33532 TC9150P102422 23 5 6TC9002AP10 3 4TD6368B4/FHO374231 32 33534 HD44840A6572117 18 1513GS8234-OIF446430 31 2987 LK510384231 32 3324LK5140224231 32 33243KD9218B72331 32 2414240 KY88C94611549 50 55514241 KAIDA8803A401 2 3 6343335 UPD1514C-03612815 16 172220UPD1937C11210 11 7Z862274147 8 9373536 BM5069325228 29 2714142 CKP1003S244231 32 332CKP1008S204231 32 33CKP1009S204231 32 33伴音静噪调谐电压场同步脉冲行同步脉冲复合同步脉冲AFT输入遥控输入51711273735 36585972024 156******** 1642938 209 94210281814137，835 37131210，1135 145313515 1529102612 2629104112 13127，835 10150513685 411505136355 411505136355 391505136355伴音静噪调谐电压场同步脉冲行同步脉冲复合同步脉冲AFT输入遥控输入391505136355 221505136355 322038399814 322038399814 232038392214520383998145859212024 222039389814 372038399814 3720383998372038399814420383968144203839681442038396814 361421181116伴音静噪调谐电压场同步脉冲行同步脉冲复合同步脉冲AFT输入遥控输入1272634935 282021331434 10227253542272635 372272633 12726381136 1722726361555 12726161136 20127261136 127263493515423738 1138252826 291830119262912 421637 1538284244 15384847284144 1541284144 1221411272629935伴音静噪调谐电压场同步脉冲行同步脉冲复合同步脉冲AFT输入遥控输入341272629935 1272634935 361272634935 382726169373 42161338201621 27182829102512 35332829958 353328299398 206626334591417111516 156626334531439820211434 82526431344伴音静噪调谐电压场同步脉冲行同步脉冲复合同步脉冲AFT输入遥控输入8252613448252643134481920331834133512 1511 33141327153434272638935 3834272638935 31392625431744 392625431744 31392625431744 82526431344825264313441272634935 1527268937 15384847284144122174126伴音静噪调谐电压场同步脉冲行同步脉冲复合同步脉冲AFT输入遥控输入3982021331434 39820211434 820211434 3982021331434 3982021331434 392625431744 35825261344 253335271321 135539710 11 1 1713837291947 101272636935 37 38 27261335 37 38 27263613353727261335 1722726361535 4 5 27261635422726361335伴音静噪调谐电压场同步脉冲行同步脉冲复合同步脉冲AFT输入遥控输入42361335822726361335 36272635 34272638935 3342726935 17373645 151272637 3839504939517 151272636 151******** 381272636 1712726368127261136 29121222118512221185 92726151236伴音静噪调谐电压场同步脉冲行同步脉冲复合同步脉冲AFT输入遥控输入361421181116 121421181116 401421341516 391421181116 121421181116 431421181516422726361335 409505136355 361412181116 48626315235 6212024 20662631645 156626343 31162110917223221836 34465539171 344655397101伴音静噪调谐电压场同步脉冲行同步脉冲复合同步脉冲AFT输入遥控输入55397 8 10 11 1 1722322136 91722302134 46553951 243335272821 25433992115144 52543269 3839504929517 1343641351181726625 4012726935 20127261335 1722 3912338374715 16 466136935 113471546 37361335伴音静噪调谐电压场同步脉冲行同步脉冲复合同步脉冲AFT输入遥控输入402019131412 427263614 16 35 2027261335 10127269359278 5 634272638935 1030 61643 11134364135 40136935203830292719 3926273237 4121039 21113 32122216185 37355051385 372726361335 1722726361435 1722726361535红字符输出绿字符输出蓝字符输出AV/TV控制时钟总线数据总线画中画输入6162622261605935 36 333423141663420345133415 1664746451447464537 38474645373847464537红字符输出绿字符输出蓝字符输出AV/TV控制时钟总线数据总线画中画输入4746453747464511 12432364323623432432363761626355 5643236373055252525525119红字符输出绿字符输出蓝字符输出AV/TV控制时钟总线数据总线画中画输入22232411394022262437302922232439402223243738222324 5 7 394024232218 19 39402223241112242335 37 414224232235414222232411 12 3940515049515049555351504913555314515049341347484957534422232412红字符输出绿字符输出蓝字符输出AV/TV控制时钟总线数据总线画中画输入2223241222232411 12 39402223241039402423223940335345182726253227262537 3861605947525150136160592122525150 4 44 424322232437302927282934 35 32红字符输出绿字符输出蓝字符输出AV/TV控制时钟总线数据总线画中画输入272829403227282934 3532212223 37 38 32504930312223243622232436414021222337322122233721222337322728293227282934 35 3222232411 12 394024232239405150495355474849红字符输出绿字符输出蓝字符输出AV/TV控制时钟总线数据总线画中画输入2223243728 30 27 29222324373029222324372223243730292223243728 30 27 292122233727282934 40 32313231303837444342929 31 28 30333435115251241122232439402223242394022232439402223241112222324373822232411 37 12 38红字符输出绿字符输出蓝字符输出AV/TV控制时钟总线数据总线画中画输入22232414 34 11122223241137382423223940222324364140222324 4 6 4140343332495024232223940333231 5 6242322239402223243940222324404124232241394024232238414236 37 35342324253023242530 312423224142红字符输出绿字符输出蓝字符输出AV/TV控制时钟总线数据总线画中画输入52515019 2052515019 2052515020121352515032424152515019 20 474652515047 4811121352515019616059212261626355 56616059343361605935 36 333442414029 30 373835341244434250 51 585944434250 51 3157红字符输出绿字符输出蓝字符输出AV/TV控制时钟总线数据总线画中画输入444342452928353412474833326373844434236 37 59603231308 26 373823243133232435333231 5 69161513242337 382423371632333451502423373233344852512223243940红字符输出绿字符输出蓝字符输出AV/TV控制时钟总线数据总线画中画输入222331222324111222232423222324364140561605935 36 33349242337 3834610 29303157 58232425313433 474645332223243940 2223241011 37 12 38 22232411 37 12 38画中画输出地1 32222326 322427 322215 291162222 232121 2221 2222 2325 26262625 26 画中画输出地25 2625 2619 2119 212126 3219 202119 2115 2119 2119 2119 2123 26 画中画输出地219 1511113113132131 6216 1721132 6232 6232 6243 5721画中画输出地2121212921151621212127263226922画中画输出地2299172021211010109 229212132画中画输出地9 369999109 2212 422727302121211 271 211 21画中画输出地1 2111 21212122211 3730 3721 3913 372813 3020111113画中画输出地23 2623 2623 2623 2623 2623 262223 26272632321818 5212 645827 64画中画输出地27 64264258131171 421211421212127 4121 302721画中画输出地21121302121322121481114811 25 2621 1 39 1 21。
常用CPU主要引脚功能表
红字符输出
绿字符输出
蓝字符输出
AV/TV控制
时钟总线
数据总线
画中画输入
画中画输出
地
M50436-688SP
6
52
28 29
27
3
39
1
50
51
36
35
5
47
46
45
37
25 26
M50436-602SP
10
52
28 29
27
2
4
22
1
50
51
36
35
5
47
46
45
11 12
25 26
M34300N4-011SP
常用CPU主要引脚功能表
第6页
待机控制
电源电压
时钟振荡
复位
音量控制
亮度控制
对比度控制
伴音静噪
调谐电压
场同步脉冲
行同步脉冲
复合同步脉冲
AFT输入
遥控输入
红字符输出
绿字符输出
蓝字符输出
AV/TV控制
时钟总线
数据总线
画中画输入
画中画输出
地
LA86C3348A
7
12
10 11
17
39
8
20
21
33
14
34
22
12
13
4
20
38
39
6
8
14
2
5
19 21
M34300N4-628SP
17
42
34 35
7
10
12
13
附录DE2-115引脚表
SW[11]PIN_AB24Slide Switch[11]Depending on JP7 SW[12]PIN_AB23Slide Switch[12]Depending on JP7 SW[13]PIN_AA24Slide Switch[13]Depending on JP7 SW[14]PIN_AA23Slide Switch[14]Depending on JP7 SW[15]PIN_AA22Slide Switch[15]Depending on JP7 SW[16]PIN_Y24Slide Switch[16]Depending on JP7 SW[17]PIN_Y23Slide Switch[17]Depending on JP7表 2 按钮开关引脚配置Signal Name FPGA Pin No.Description I/O Standard KEY[0]PIN_M23Push-button[0]Depending on JP7KEY[1]PIN_M21Push-button[1]Depending on JP7KEY[2]PIN_N21Push-button[2]Depending on JP7KEY[3]PIN_R24Push-button[3]Depending on JP7表 3 LED引脚配置Signal Name FPGA Pin No.Description I/OS tandard LEDR[0]PIN_G19LED Red[0] 2.5VLEDR[1]PIN_F19LED Red[1] 2.5VLEDR[2]PIN_E19LED Red[2] 2.5VLEDR[3]PIN_F21LED Red[3] 2.5VLEDR[4]PIN_F18LED Red[4] 2.5VLEDR[5]PIN_E18LED Red[5] 2.5VLEDR[6]PIN_J19LED Red[6] 2.5VLEDR[7]PIN_H19LED Red[7] 2.5V LEDR[8]PIN_J17LED Red[8] 2.5V LEDR[9]PIN_G17LED Red[9] 2.5V LEDR[10]PIN_J15LED Red[10] 2.5V LEDR[11]PIN_H16LED Red[11] 2.5V LEDR[12]PIN_J16LED Red[12] 2.5V LEDR[13]PIN_H17LED Red[13] 2.5V LEDR[14]PIN_F15LED Red[14] 2.5V LEDR[15]PIN_G15LED Red[15] 2.5V LEDR[16]PIN_G16LED Red[16] 2.5V LEDR[17]PIN_H15LED Red[17] 2.5V LEDG[0]PIN_E21LED Green[0] 2.5V LEDG[1]PIN_E22LED Green[1] 2.5V LEDG[2]PIN_E25LED Green[2] 2.5V LEDG[3]PIN_E24LED Green[3] 2.5V LEDG[4]PIN_H21LED Green[4] 2.5V LEDG[5]PIN_G20LED Green[5] 2.5V LEDG[6]PIN_G22LED Green[6] 2.5V LEDG[7]PIN_G21LED Green[7] 2.5V LEDG[8]PIN_F17LED Green[8] 2.5V 表 4 七段数码管引脚配置Signal Na me FPGA Pin No.Description I/O StandardHEX0[0]PIN_G18Seven Segment Digit 0[0]2.5VHEX0[1]PIN_F22Seven Segment Digit 0[1] 2.5VHEX0[2]PIN_E17Seven Segment Digit 0[2] 2.5VHEX0[3]PIN_L26Seven Segment Digit 0[3]Depending onJP7HEX0[4]PIN_L25Seven Segment Digit 0[4]Depending on JP7HEX0[5]PIN_J22Seven Segment Digit 0[5]Depending on JP7HEX0[6]PIN_H22Seven Segment Digit 0[6]Depending on JP7HEX1[0]PIN_M24Seven Segment Digit 1[0]Depending on JP7HEX1[1]PIN_Y22Seven Segment Digit 1[1]Depending on JP7HEX1[2]PIN_W21Seven Segment Digit 1[2]Depending on JP7HEX1[3]PIN_W22Seven Segment Digit 1[3]Depending onJP7HEX1[4]PIN_W25Seven Segment Digit 1[4]Depending onJP7HEX1[5]PIN_U23Seven Segment Digit 1[5]Depending onJP7HEX1[6]PIN_U24Seven Segment Digit 1[6]Depending onJP7HEX2[0]PIN_AA25Seven Segment Digit 2[0]Depending onJP7HEX2[1]PIN_AA26Seven Segment Digit 2[1]Depending onJP7HEX2[2]PIN_Y25Seven Segment Digit 2[2]Depending on JP7HEX2[3]PIN_W26Seven Segment Digit 2[3]Depending on JP7HEX2[4]PIN_Y26Seven Segment Digit 2[4]Depending on JP7HEX2[5]PIN_W27Seven Segment Digit 2[5]Depending on JP7HEX2[6]PIN_W28Seven Segment Digit 2[6]Depending on JP7HEX3[0]PIN_V21Seven Segment Digit 3[0]Depending on JP7HEX3[1]PIN_U21Seven Segment Digit 3[1]Depending on JP7HEX3[2]PIN_AB20Seven Segment Digit 3[2]Depending onJP6HEX3[3]PIN_AA21Seven Segment Digit 3[3]Depending onJP6HEX3[4]PIN_AD24Seven Segment Digit 3[4]Depending onJP6HEX3[5]PIN_AF23Seven Segment Digit 3[5]Depending onJP6HEX3[6]PIN_Y19Seven Segment Digit 3[6]Depending onJP6HEX4[0]PIN_AB19Seven Segment Digit 4[0]Depending onJP6HEX4[1]PIN_AA19Seven Segment Digit 4[1]Depending on JP6HEX4[2]PIN_AG21Seven Segment Digit 4[2]Depending on JP6HEX4[3]PIN_AH21Seven Segment Digit 4[3]Depending on JP6HEX4[4]PIN_AE19Seven Segment Digit 4[4]Depending on JP6HEX4[5]PIN_AF19Seven Segment Digit 4[5]Depending on JP6HEX4[6]PIN_AE18Seven Segment Digit 4[6]Depending on JP6HEX5[0]PIN_AD18Seven Segment Digit 5[0]Depending on JP6HEX5[1]PIN_AC18Seven Segment Digit 5[1]Depending onJP6HEX5[2]PIN_AB18Seven Segment Digit 5[2]Depending onJP6HEX5[3]PIN_AH19Seven Segment Digit 5[3]Depending onJP6HEX5[4]PIN_AG19Seven Segment Digit 5[4]Depending onJP6HEX5[5]PIN_AF18Seven Segment Digit 5[5]Depending onJP6HEX5[6]PIN_AH18Seven Segment Digit 5[6]Depending onJP6HEX6[0]PIN_AA17Seven Segment Digit 6[0]Depending on JP6HEX6[1]PIN_AB16Seven Segment Digit 6[1]Depending on JP6HEX6[2]PIN_AA16Seven Segment Digit 6[2]Depending on JP6HEX6[3]PIN_AB17Seven Segment Digit 6[3]Depending on JP6HEX6[4]PIN_AB15Seven Segment Digit 6[4]Depending on JP6HEX6[5]PIN_AA15Seven Segment Digit 6[5]Depending on JP6HEX6[6]PIN_AC17Seven Segment Digit 6[6]Depending on JP6HEX7[0]PIN_AD17Seven Segment Digit 7[0]Depending onJP6HEX7[1]PIN_AE17Seven Segment Digit 7[1]Depending onJP6HEX7[2]PIN_AG17Seven Segment Digit 7[2]Depending onJP6HEX7[3]PIN_AH17Seven Segment Digit 7[3]Depending onJP6HEX7[4]PIN_AF17Seven Segment Digit 7[4]Depending on JP6HEX7[5]PIN_AG18Seven Segment Digit 7[5]Depending on JP6HEX7[6]PIN_AA14Seven Segment Digit 7[6] 3.3V表 5 时钟信号引脚配置信息Signal NameFPGA Pin N o.DescriptionI/O StandardCLOCK_50PIN_Y250 MHz clock input3.3V CLOCK2_50PIN_AG1450 MHz clock input 3.3V CLOCK3_50PIN_AG1550 MHz clock input Depending onJP6SMA_CLKOUT PIN_AE23External (SMA) clock o utputDepending onJP6SMA_CLKINPIN_AH14External (SMA) clock in put3.3V表 6 LCD 模块引脚配置Signal NameFPGAPinNo.DescriptionI/OLCD_DATA[7]PIN_M5LCD Data[7]StandardLCD_DATA[6]PIN_M3LCD Data[6]3.3VLCD_DATA[5]PIN_K2LCD Data[5]3.3VLCD_DATA[4]PIN_K1LCD Data[4]3.3VLCD_DATA[3]PIN_K7LCD Data[3]3.3VLCD_DATA[2]PIN_L2LCD Data[2]3.3VLCD_DATA[1]PIN_L1LCD Data[1]3.3VLCD_DATA[0]PIN_L3LCD Data[0]3.3VLCD_ENPIN_L4LCD Enable3.3VLCD_RWPIN_M1LCD Read/Write Select, 0 = Write, 1 = Read3.3VLCD_RSPIN_M2LCD Command/Data S elect, 0 = Command, 1= Data3.3VLCD_ONPIN_L5LCD Power ON/OFF3.3V LCD_BLONPIN_L6LCD Back Light ON/OF F 3.3V表 7 HSMC 接口引脚配置Signal NameFPGA Pin No.DescriptionI/O StandardHSMC_CLKIN0PIN_AH15Dedicated clock inputDepending on JP6HSMC_CLKIN_N1PIN_J28LVDS RX or C MOS I/O or diff erential clock inputDepending on JP7HSMC_CLKIN_N2PIN_Y28LVDS RX or C MOS I/O or diff erential clock inDepending on JP7putHSMC_CLKIN_P1PIN_J27LVDS RX or C MOS I/O or diff erential clock inputDepending on JP7HSMC_CLKIN_P2PIN_Y27LVDS RX or C MOS I/O or diff erential clock in put Depending on JP7HSMC_CLKOUT0PIN_AD28Dedicated clock output Depending on JP7HSMC_CLKOUT_N1PIN_G24LVDS TX or C MOS I/O or diff erential clock in put/output Depending on J P7HSMC_CLKOUT_N2PIN_V24LVDS TX or C MOS I/O or diff erential clock in put/output Depending on J P7HSMC_CLKOUT_P1PIN_G23LVDS TX or C MOS I/O or diff erential clock input/outputDepending on J P7HSMC_CLKOUT_P2PIN_V23LVDS TX or C MOS I/O or diff erential clock input/outputDepending on JP7HSMC_D[0]PIN_AE26LVDS TX or CDepending on JMOS I/O P7HSMC_D[1]PIN_AE28LVDS TX or CMOS I/O Depending on J P7HSMC_D[2]PIN_AE27LVDS TX or CMOS I/O Depending on J P7HSMC_D[3]PIN_AF27LVDS TX or CMOS I/O Depending on J P7HSMC_RX_D_N[0]PIN_F25LVDS RX bit 0n or CMOS I/O Depending on J P7HSMC_RX_D_N[1]PIN_C27LVDS RX bit 1n or CMOS I/O Depending on J P7HSMC_RX_D_N[2]PIN_E26LVDS RX bit 2n or CMOS I/O Depending on J P7HSMC_RX_D_N[3]PIN_G26LVDS RX bit 3n or CMOS I/O Depending on J P7HSMC_RX_D_N[4]PIN_H26LVDS RX bit 4n or CMOS I/O Depending on J P7HSMC_RX_D_N[5]PIN_K26LVDS RX bit 5n or CMOS I/O Depending on J P7HSMC_RX_D_N[6]PIN_L24LVDS RX bit 6n or CMOS I/O Depending on J P7HSMC_RX_D_N[7]PIN_M26LVDS RX bit 7n or CMOS I/O Depending on J P7HSMC_RX_D_N[8]PIN_R26LVDS RX bit 8n or CMOS I/O Depending on J P7HSMC_RX_D_N[9]PIN_T26LVDS RX bit 9n or CMOS I/O Depending on J P7HSMC_RX_D_N[10]PIN_U26LVDS RX bit 10n or CMOS I/O Depending on J P7HSMC_RX_D_N[11]PIN_L22LVDS RX bit 11n or CMOS I/O Depending on J P7HSMC_RX_D_N[12]PIN_N26LVDS RX bit 12n or CMOS I/O Depending on J P7HSMC_RX_D_N[13]PIN_P26LVDS RX bit 13n or CMOS I/O Depending on J P7HSMC_RX_D_N[14]PIN_R21LVDS RX bit 14n or CMOS I/O Depending on J P7HSMC_RX_D_N[15]PIN_R23LVDS RX bit 15n or CMOS I/O Depending on J P7HSMC_RX_D_N[16]PIN_T22LVDS RX bit 16n or CMOS I/O Depending on J P7HSMC_RX_D_P[0]PIN_F24LVDS RX bit 0or CMOS I/O Depending on J P7HSMC_RX_D_P[1]PIN_D26LVDS RX bit 1or CMOS I/O Depending on J P7HSMC_RX_D_P[2]PIN_F26LVDS RX bit 2or CMOS I/O Depending on J P7HSMC_RX_D_P[3]PIN_G25LVDS RX bit 3or CMOS I/O Depending on J P7HSMC_RX_D_P[4]PIN_H25LVDS RX bit 4or CMOS I/O Depending on J P7HSMC_RX_D_P[5]PIN_K25LVDS RX bit 5or CMOS I/O Depending on J P7HSMC_RX_D_P[6]PIN_L23LVDS RX bit 6or CMOS I/O Depending on J P7HSMC_RX_D_P[7]PIN_M25LVDS RX bit 7or CMOS I/O Depending on J P7HSMC_RX_D_P[8]PIN_R25LVDS RX bit 8or CMOS I/O Depending on J P7HSMC_RX_D_P[9]PIN_T25LVDS RX bit 9or CMOS I/O Depending on J P7HSMC_RX_D_P[10]PIN_U25LVDS RX bit 10 or CMOS I/O Depending on J P7HSMC_RX_D_P[11]PIN_L21LVDS RX bit 11 or CMOS I/O Depending on J P7HSMC_RX_D_P[12]PIN_N25LVDS RX bit 12 or CMOS I/O Depending on J P7HSMC_RX_D_P[13]PIN_P25LVDS RX bit 13 or CMOS I/O Depending on J P7HSMC_RX_D_P[14]PIN_P21LVDS RX bit 14 or CMOS I/O Depending on J P7HSMC_RX_D_P[15]PIN_R22LVDS RX bit 15 or CMOS I/O Depending on J P7HSMC_RX_D_P[16]PIN_T21LVDS RX bit 16 or CMOS I/O Depending on J P7HSMC_TX_D_N[0]PIN_D28LVDS TX bit 0n or CMOS I/O Depending on J P7HSMC_TX_D_N[1]PIN_E28LVDS TX bit 1n or CMOS I/O Depending on J P7HSMC_TX_D_N[2]PIN_F28LVDS TX bit 2n or CMOS I/O Depending on J P7HSMC_TX_D_N[3]PIN_G28LVDS TX bit 3n or CMOS I/O Depending on J P7HSMC_TX_D_N[4]PIN_K28LVDS TX bit 4n or CMOS I/O Depending on J P7HSMC_TX_D_N[5]PIN_M28LVDS TX bit 5n or CMOS I/O Depending on J P7HSMC_TX_D_N[6]PIN_K22LVDS TX bit 6n or CMOS I/O Depending on J P7HSMC_TX_D_N[7]PIN_H24LVDS TX bit 7n or CMOS I/O Depending on J P7HSMC_TX_D_N[8]PIN_J24LVDS TX bit 8n or CMOS I/O Depending on J P7HSMC_TX_D_N[9]PIN_P28LVDS TX bit 9n or CMOS I/O Depending on J P7HSMC_TX_D_N[10]PIN_J26LVDS TX bit 10n or CMOS I/O Depending on J P7HSMC_TX_D_N[11]PIN_L28LVDS TX bit 11n or CMOS I/Depending on J P7OHSMC_TX_D_N[12]PIN_V26LVDS TX bit 12n or CMOS I/O Depending on J P7HSMC_TX_D_N[13]PIN_R28LVDS TX bit 13n or CMOS I/O Depending on J P7HSMC_TX_D_N[14]PIN_U28LVDS TX bit 14n or CMOS I/O Depending on J P7HSMC_TX_D_N[15]PIN_V28LVDS TX bit 15n or CMOS I/O Depending on J P7HSMC_TX_D_N[16]PIN_V22LVDS TX bit 16n or CMOS I/O Depending on J P7HSMC_TX_D_P[0]PIN_D27LVDS TX bit 0or CMOS I/O Depending on J P7HSMC_TX_D_P[1]PIN_E27LVDS TX bit 1or CMOS I/O Depending on J P7HSMC_TX_D_P[2]PIN_F27LVDS TX bit 2or CMOS I/O Depending on J P7HSMC_TX_D_P[3]PIN_G27LVDS TX bit 3or CMOS I/O Depending on J P7HSMC_TX_D_P[4]PIN_K27LVDS TX bit 4or CMOS I/O Depending on J P7HSMC_TX_D_P[5]PIN_M27LVDS TX bit 5 Depending on Jor CMOS I/O P7HSMC_TX_D_P[6]PIN_K21LVDS TX bit 6or CMOS I/O Depending on J P7HSMC_TX_D_P[7]PIN_H23LVDS TX bit 7or CMOS I/O Depending on J P7HSMC_TX_D_P[8]PIN_J23LVDS TX bit 8or CMOS I/O Depending on J P7HSMC_TX_D_P[9]PIN_P27LVDS TX bit 9or CMOS I/O Depending on J P7HSMC_TX_D_P[10]PIN_J25LVDS TX bit 10 or CMOS I/O Depending on J P7HSMC_TX_D_P[11]PIN_L27LVDS TX bit 11 or CMOS I/O Depending on J P7HSMC_TX_D_P[12]PIN_V25LVDS TX bit 12 or CMOS I/O Depending on J P7HSMC_TX_D_P[13]PIN_R27LVDS TX bit 13 or CMOS I/O Depending on J P7HSMC_TX_D_P[14]PIN_U27LVDS TX bit 14 or CMOS I/O Depending on J P7HSMC_TX_D_P[15]PIN_V27LVDS TX bit 15 or CMOS I/O Depending on J P7HSMC_TX_D_P[16]PIN_U22LVDS TX bit 16 or CMOS I/O Depending on J P7表8 GPIO 引脚配置信息Signal Nam e FPGA Pin No.Description I/O StandardGPIO[0]PIN_AB22GPIO Connection DATA[0]Depending on JP 6GPIO[1]PIN_AC15GPIO Connection DATA[1]Depending on JP 6GPIO[2]PIN_AB21GPIO Connection DATA[2]Depending on JP 6GPIO[3]PIN_Y17GPIO Connection DATA[3]Depending on JP 6GPIO[4]PIN_AC21GPIO Connection DATA[4]Depending on JP 6GPIO[5]PIN_Y16GPIO Connection DATA[5]Depending on JP 6GPIO[6]PIN_AD21GPIO Connection DATA[6]Depending on JP 6GPIO[7]PIN_AE16GPIO Connection DATA[7]Depending on JP 6GPIO[8]PIN_AD15GPIO Connection DATA[8]Depending on JP 6GPIO[9]PIN_AE15GPIO Connection DATA[9]Depending on JP 6GPIO[10]PIN_AC19GPIO Connection DATA[10]Depending on JP 6GPIO[11]PIN_AF16GPIO Connection DATA[11]Depending on JP 6GPIO[12]PIN_AD19GPIO Connection DATA[12]Depending on JP 6GPIO[13]PIN_AF15GPIO Connection DATA[13]Depending on JP 6GPIO[14]PIN_AF24GPIO Connection DATA[14]Depending on JP 6GPIO[15]PIN_AE21GPIO Connection DATA[15]Depending on JP 6GPIO[16]PIN_AF25GPIO Connection DATA[16]Depending on JP 6GPIO[17]PIN_AC22GPIO Connection DATA[17]Depending on JP 6GPIO[18]PIN_AE22GPIO Connection DATA[18]Depending on JP 6GPIO[19]PIN_AF21GPIO Connection DATA[19]Depending on JP 6GPIO[20]PIN_AF22GPIO Connection DATA[20]Depending on JP 6GPIO[21]PIN_AD22GPIO Connection DATA[21]Depending on JP 6GPIO[22]PIN_AG25GPIO Connection DATA[22]Depending on JP 6GPIO[23]PIN_AD25GPIO Connection DATA[23]Depending on JP 6GPIO[24]PIN_AH25GPIO Connection DATA[24]Depending on JP 6GPIO[25]PIN_AE25GPIO Connection DATA[25]Depending on JP 6GPIO[26]PIN_AG22GPIO Connection DATA[26]Depending on JP 6GPIO[27]PIN_AE24GPIO Connection DATA[27]Depending on JP 6GPIO[28]PIN_AH22GPIO Connection DATA[28]Depending on JP 6GPIO[29]PIN_AF26GPIO Connection DATA[29]Depending on JP 6GPIO[30]PIN_AE20GPIO Connection DATA[30]Depending on JP 6GPIO[31]PIN_AG23GPIO Connection DATA[31]Depending on JP 6GPIO[32]PIN_AF20GPIO Connection DATA[32]Depending on JP 6GPIO[33]PIN_AH26GPIO Connection DATA[33]Depending on JP 6GPIO[34]PIN_AH23GPIO Connection DATA[34]Depending on JP 6GPIO[35]PIN_AG26GPIO Connection DATA[35]Depending on JP 6表9 扩展接口引脚配置信息Signal Name FPGA Pin No.Description I/O Standard EX_IO[0]PIN_J10Extended IO[0] 3.3VEX_IO[1]PIN_J14Extended IO[1] 3.3VEX_IO[2]PIN_H13Extended IO[2] 3.3VEX_IO[3]PIN_H14Extended IO[3] 3.3VEX_IO[4]PIN_F14Extended IO[4] 3.3VEX_IO[5]PIN_E10Extended IO[5] 3.3VEX_IO[6]PIN_D9Extended IO[6] 3.3V表10 ADV7123 引脚配置Signal Name FPGA Pin No.Description I/O Standard VGA_R[0]PIN_E12VGA Red[0] 3.3VVGA_R[1]PIN_E11VGA Red[1] 3.3VVGA_R[2]PIN_D10VGA Red[2] 3.3VVGA_R[3]PIN_F12VGA Red[3] 3.3VVGA_R[4]PIN_G10VGA Red[4] 3.3VVGA_R[5]PIN_J12VGA Red[5] 3.3VVGA_R[6]PIN_H8VGA Red[6] 3.3VVGA_R[7]PIN_H10VGA Red[7] 3.3VVGA_G[0]PIN_G8VGA Green[0] 3.3VVGA_G[1]PIN_G11VGA Green[1] 3.3VVGA_G[2]PIN_F8VGA Green[2] 3.3VVGA_G[3]PIN_H12VGA Green[3] 3.3VVGA_G[4]PIN_C8VGA Green[4] 3.3VVGA_G[5]PIN_B8VGA Green[5] 3.3VVGA_G[6]PIN_F10VGA Green[6] 3.3VVGA_G[7]PIN_C9VGA Green[7] 3.3VVGA_B[0]PIN_B10VGA Blue[0] 3.3VVGA_B[1]PIN_A10VGA Blue[1] 3.3VVGA_B[2]PIN_C11VGA Blue[2] 3.3VVGA_B[3]PIN_B11VGA Blue[3] 3.3VVGA_B[4]PIN_A11VGA Blue[4] 3.3VVGA_B[5]PIN_C12VGA Blue[5] 3.3VVGA_B[6]PIN_D11VGA Blue[6] 3.3VVGA_B[7]PIN_D12VGA Blue[7] 3.3VVGA_CLK PIN_A12VGA Clock 3.3VVGA_BLANK_N PIN_F11VGA BLANK 3.3VVGA_HS PIN_G13VGA H_SYNC 3.3VVGA_VS PIN_C13VGA V_SYNC 3.3VVGA_SYNC_N PIN_C10VGA SYNC 3.3V表11 音频编解码芯片引脚配置Signal Name FPGA Pin No.Description I/O Standard3.3VAUD_ADCLRCK PIN_C2Audio CODEC ADC LR ClockAUD_ADCDAT PIN_D2Audio CODEC ADC Data 3.3V3.3VAUD_DACLRCK PIN_E3Audio CODEC DAC LR ClockAUD_DACDAT PIN_D1Audio CODEC DAC Data 3.3VAUD_XCK PIN_E1Audio CODEC Chip Clock 3.3V3.3VAUD_BCLK PIN_F2Audio CODEC Bit-StreamClockI2C_SCLK PIN_B7I2C Clock 3.3VI2C_SDAT PIN_A8I2C Data 3.3V表12 RS-232 引脚配置Signal Name FPGA Pin No.Description I/O Standard UART_RXD PIN_G12UART Receiver 3.3VUART_TXD PIN_G9UART Transmitter 3.3VUART_CTS PIN_G14UART Clear to Send 3.3VUART_RTS PIN_J13UART Request to Send3.3V表13 PS/2 引脚配置Signal Name FPGA Pin No.Description I/O StandardPS2_CLK PIN_G6PS/2 Clock 3.3VPS2_DAT PIN_H5PS/2 Data 3.3VPS2_CLK2PIN_G5PS/2 Clock (reserved for second PS/2 device)3.3VPS2_DAT2PIN_F5PS/2 Data (reserved for second PS/2 device)3.3V表14 千兆以太网芯片引脚配置Signal Name FPGA Pin No.Description I/O StandardE NET0_GTX_CLK PIN_A17GMII Transmit Clock 12.5VENET0_INT_N PIN_A21Interrupt open drain2.5Voutput 13.3V ENET0_LINK100PIN_C14Parallel LED outputof 100BASE-TX link12.5V ENET0_MDC PIN_C20Management data clock reference 1ENET0_MDIO PIN_B21Management data 12.5V2.5V ENET0_RST_N PIN_C19Hardware reset signal 1ENET0_RX_CLK PIN_A15GMII and MII receiv2.5Ve clock 12.5V ENET0_RX_COL PIN_E15GMII and MII collision 1ENET0_RX_CRS PIN_D15GMII and MII carrie2.5Vr sense 12.5V ENET0_RX_DATA[0]PIN_C16GMII and MII receive data[0] 12.5V ENET0_RX_DATA[1]PIN_D16GMII and MII receive data[1] 12.5V ENET0_RX_DATA[2]PIN_D17GMII and MII receive data[2] 12.5V ENET0_RX_DATA[3]PIN_C15GMII and MII receive data[3] 12.5V ENET0_RX_DV PIN_C17GMII and MII receive data valid 1ENET0_RX_ER PIN_D18GMII and MII receiv2.5Ve error 1ENET0_TX_CLK PIN_B17MII transmit clock 12.5V ENET0_TX_DATA[0]PIN_C18MII transmit data[0]2.5V12.5V ENET0_TX_DATA[1]PIN_D19MII transmit data[1]12.5V ENET0_TX_DATA[2]PIN_A19MII transmit data[2]12.5V ENET0_TX_DATA[3]PIN_B19MII transmit data[3]12.5V ENET0_TX_EN PIN_A18GMII and MII transmit enable 12.5V ENET0_TX_ER PIN_B18GMII and MII transmit error 1ENET1_GTX_CLK PIN_C23GMII Transmit Cloc2.5Vk 22.5V ENET1_INT_N PIN_D24Interrupt open drainoutput 22.5V ENET1_LINK100PIN_D13Parallel LED outputof 100BASE-TX link22.5V ENET1_MDC PIN_D23Management data clock reference 2ENET1_MDIO PIN_D25Management data 22.5V ENET1_RST_N PIN_D22Hardware reset sig2.5Vnal 22.5V ENET1_RX_CLK PIN_B15GMII and MII receive clock 22.5V ENET1_RX_COL PIN_B22GMII and MII collision 22.5V ENET1_RX_CRS PIN_D20GMII and MII carrier sense 22.5V ENET1_RX_DATA[0]PIN_B23GMII and MII receive data[0] 22.5V ENET1_RX_DATA[1]PIN_C21GMII and MII receive data[1] 22.5V ENET1_RX_DATA[2]PIN_A23GMII and MII receive data[2] 2ENET1_RX_DATA[3]PIN_D21GMII and MII receiv2.5Ve data[3] 2ENET1_RX_DV PIN_A22GMII and MII receiv2.5Ve data valid 22.5V ENET1_RX_ER PIN_C24GMII and MII receive error 2ENET1_TX_CLK PIN_C22MII transmit clock 22.5V2.5V ENET1_TX_DATA[0]PIN_C25MII transmit data[0]2ENET1_TX_DATA[1]PIN_A26MII transmit data[1]2.5V2ENET1_TX_DATA[2]PIN_B26MII transmit data[2]2.5V2ENET1_TX_DATA[3]PIN_C26MII transmit data[3]2.5V22.5V ENET1_TX_EN PIN_B25GMII and MII transmit enable 22.5V ENET1_TX_ER PIN_A25GMII and MII transmit error 2ENETCLK_25PIN_A14Ethernet clock sour3.3Vce表15 TV 解码芯片引脚配置Signal Name FPGA Pin No.Description I/O Standard TD_ DATA [0]PIN_E8TV Decoder Data[0] 3.3VTD_ DATA [1]PIN_A7TV Decoder Data[1] 3.3VTD_ DATA [2]PIN_D8TV Decoder Data[2] 3.3VTD_ DATA [3]PIN_C7TV Decoder Data[3] 3.3VTD_ DATA [4]PIN_D7TV Decoder Data[4] 3.3VTD_ DATA [5]PIN_D6TV Decoder Data[5] 3.3VTD_ DATA [6]PIN_E7TV Decoder Data[6] 3.3VTD_ DATA [7]PIN_F7TV Decoder Data[7] 3.3VTD_HS PIN_E5TV Decoder H_SYNC 3.3VTD_VS PIN_E4TV Decoder V_SYNC 3.3V3.3VTD_CLK27PIN_B14TV Decoder Clock Input.TD_RESET_N PIN_G7TV Decoder Reset 3.3VI2C_SCLK PIN_B7I2C Clock 3.3VI2C_SDAT PIN_A8I2C Data 3.3V 表16 USB (ISP1362)引脚配置Signal Name FPGA Pin No.Description I/O StandardOTG_ADDR[0]PIN_H7ISP1362 Address[0] 3.3V OTG_ADDR[1]PIN_C3ISP1362 Address[1] 3.3V OTG_DATA[0]PIN_J6ISP1362 Data[0] 3.3V OTG_DATA[1]PIN_K4ISP1362 Data[1] 3.3V OTG_DATA[2]PIN_J5ISP1362 Data[2] 3.3V OTG_DATA[3]PIN_K3ISP1362 Data[3] 3.3V OTG_DATA[4]PIN_J4ISP1362 Data[4] 3.3V OTG_DATA[5]PIN_J3ISP1362 Data[5] 3.3V OTG_DATA[6]PIN_J7ISP1362 Data[6] 3.3V OTG_DATA[7]PIN_H6ISP1362 Data[7] 3.3V OTG_DATA[8]PIN_H3ISP1362 Data[8] 3.3V OTG_DATA[9]PIN_H4ISP1362 Data[9] 3.3V OTG_DATA[10]PIN_G1ISP1362 Data[10] 3.3V OTG_DATA[11]PIN_G2ISP1362 Data[11] 3.3V OTG_DATA[12]PIN_G3ISP1362 Data[12] 3.3V OTG_DATA[13]PIN_F1ISP1362 Data[13] 3.3V OTG_DATA[14]PIN_F3ISP1362 Data[14] 3.3V OTG_DATA[15]PIN_G4ISP1362 Data[15] 3.3V OTG_CS_N PIN_A3ISP1362 Chip Select 3.3VOTG_RD_N PIN_B3ISP1362 Read 3.3V OTG_WR_N PIN_A4ISP1362 Write 3.3V OTG_RST_N PIN_C5ISP1362 Reset 3.3V OTG_INT[0]PIN_A6ISP1362 Interrupt 0 3.3V OTG_INT[1]PIN_D5ISP1362 Interrupt 1 3.3V OTG_DACK_N[0]PIN_C4ISP1362 DMA Acknowledge 0 3.3V OTG_DACK_N[1]PIN_D4ISP1362 DMA Acknowledge 1 3.3V OTG_DREQ[0]PIN_J1ISP1362 DMA Request 0 3.3V OTG_DREQ[1]PIN_B4ISP1362 DMA Request 1 3.3V3.3V OTG_FSPEED PIN_C6USB Full Speed, 0 = Enable, Z= Disable3.3V OTG_LSPEED PIN_B6USB Low Speed, 0 = Enable, Z= Disable表17 IR 引脚配置Description I/O StandardSignal Name FPGA Pin No.IRDA_RXD PIN_Y15IR Receiver 3.3V表18 SRAM 引脚配置Signal Name FPGA Pin No.Description I/O Standard SRAM_ADDR[0]PIN_AB7SRAM Address[0] 3.3VSRAM_ADDR[1]PIN_AD7SRAM Address[1] 3.3VSRAM_ADDR[2]PIN_AE7SRAM Address[2] 3.3VSRAM_ADDR[3]PIN_AC7SRAM Address[3] 3.3VSRAM_ADDR[4]PIN_AB6SRAM Address[4] 3.3V SRAM_ADDR[5]PIN_AE6SRAM Address[5] 3.3V SRAM_ADDR[6]PIN_AB5SRAM Address[6] 3.3V SRAM_ADDR[7]PIN_AC5SRAM Address[7] 3.3V SRAM_ADDR[8]PIN_AF5SRAM Address[8] 3.3V SRAM_ADDR[9]PIN_T7SRAM Address[9] 3.3V SRAM_ADDR[10]PIN_AF2SRAM Address[10] 3.3V SRAM_ADDR[11]PIN_AD3SRAM Address[11] 3.3V SRAM_ADDR[12]PIN_AB4SRAM Address[12] 3.3V SRAM_ADDR[13]PIN_AC3SRAM Address[13] 3.3V SRAM_ADDR[14]PIN_AA4SRAM Address[14] 3.3V SRAM_ADDR[15]PIN_AB11SRAM Address[15] 3.3V SRAM_ADDR[16]PIN_AC11SRAM Address[16] 3.3V SRAM_ADDR[17]PIN_AB9SRAM Address[17] 3.3V SRAM_ADDR[18]PIN_AB8SRAM Address[18] 3.3V SRAM_ADDR[19]PIN_T8SRAM Address[19] 3.3V SRAM_DQ[0]PIN_AH3SRAM Data[0] 3.3V SRAM_DQ[1]PIN_AF4SRAM Data[1] 3.3V SRAM_DQ[2]PIN_AG4SRAM Data[2] 3.3V SRAM_DQ[3]PIN_AH4SRAM Data[3] 3.3V SRAM_DQ[4]PIN_AF6SRAM Data[4] 3.3V SRAM_DQ[5]PIN_AG6SRAM Data[5] 3.3V SRAM_DQ[6]PIN_AH6SRAM Data[6] 3.3VSRAM_DQ[7]PIN_AF7SRAM Data[7] 3.3VSRAM_DQ[8]PIN_AD1SRAM Data[8] 3.3VSRAM_DQ[9]PIN_AD2SRAM Data[9] 3.3VSRAM_DQ[10]PIN_AE2SRAM Data[10] 3.3VSRAM_DQ[11]PIN_AE1SRAM Data[11] 3.3VSRAM_DQ[12]PIN_AE3SRAM Data[12] 3.3VSRAM_DQ[13]PIN_AE4SRAM Data[13] 3.3VSRAM_DQ[14]PIN_AF3SRAM Data[14] 3.3VSRAM_DQ[15]PIN_AG3SRAM Data[15] 3.3VSRAM_OE_N PIN_AD5SRAM Output EnableSRAM_WE_N PIN_AE8SRAM Write EnableSRAM_CE_N PIN_AF8SRAM Chip SelectSRAM_LB_N PIN_AD4SRAM Lower Byte StrobeSRAM_UB_N PIN_AC4SRAM Higher Byte Strobe表19 SDRAM 引脚配置Signal Name FPGA Pin No.Description I/O Standard DRAM_ADDR[0]PIN_R6SDRAM Address[0] 3.3VDRAM_ADDR[1]PIN_V8SDRAM Address[1] 3.3VDRAM_ADDR[2]PIN_U8SDRAM Address[2] 3.3VDRAM_ADDR[3]PIN_P1SDRAM Address[3] 3.3VDRAM_ADDR[4]PIN_V5SDRAM Address[4] 3.3VDRAM_ADDR[5]PIN_W8SDRAM Address[5] 3.3V DRAM_ADDR[6]PIN_W7SDRAM Address[6] 3.3V DRAM_ADDR[7]PIN_AA7SDRAM Address[7] 3.3V DRAM_ADDR[8]PIN_Y5SDRAM Address[8] 3.3V DRAM_ADDR[9]PIN_Y6SDRAM Address[9] 3.3V DRAM_ADDR[10]PIN_R5SDRAM Address[10] 3.3V DRAM_ADDR[11]PIN_AA5SDRAM Address[11] 3.3V DRAM_ADDR[12]PIN_Y7SDRAM Address[12] 3.3V DRAM_DQ[0]PIN_W3SDRAM Data[0] 3.3V DRAM_DQ[1]PIN_W2SDRAM Data[1] 3.3V DRAM_DQ[2]PIN_V4SDRAM Data[2] 3.3V DRAM_DQ[3]PIN_W1SDRAM Data[3] 3.3V DRAM_DQ[4]PIN_V3SDRAM Data[4] 3.3V DRAM_DQ[5]PIN_V2SDRAM Data[5] 3.3V DRAM_DQ[6]PIN_V1SDRAM Data[6] 3.3V DRAM_DQ[7]PIN_U3SDRAM Data[7] 3.3V DRAM_DQ[8]PIN_Y3SDRAM Data[8] 3.3V DRAM_DQ[9]PIN_Y4SDRAM Data[9] 3.3V DRAM_DQ[10]PIN_AB1SDRAM Data[10] 3.3V DRAM_DQ[11]PIN_AA3SDRAM Data[11] 3.3V DRAM_DQ[12]PIN_AB2SDRAM Data[12] 3.3V DRAM_DQ[13]PIN_AC1SDRAM Data[13] 3.3V DRAM_DQ[14]PIN_AB3SDRAM Data[14] 3.3VDRAM_DQ[15]PIN_AC2SDRAM Data[15] 3.3V SRAM_OE_N PIN_AD5SRAM Output Enable 3.3V SRAM_WE_N PIN_AE8SRAM Write Enable 3.3V SRAM_CE_N PIN_AF8SRAM Chip Select 3.3V SRAM_LB_N PIN_AD4SRAM Lower Byte Strobe3.3VSRAM_UB_N PIN_AC4SRAM Higher Byte Strobe3.3V 表20 SDRAM 引脚配置Signal Name FPGA Pin No.Description I/O StandardDRAM_ADDR[0]PIN_R6SDRAM Address[0] 3.3V DRAM_ADDR[1]PIN_V8SDRAM Address[1] 3.3V DRAM_ADDR[2]PIN_U8SDRAM Address[2] 3.3V DRAM_ADDR[3]PIN_P1SDRAM Address[3] 3.3V DRAM_ADDR[4]PIN_V5SDRAM Address[4] 3.3V DRAM_ADDR[5]PIN_W8SDRAM Address[5] 3.3V DRAM_ADDR[6]PIN_W7SDRAM Address[6] 3.3V DRAM_ADDR[7]PIN_AA7SDRAM Address[7] 3.3V DRAM_ADDR[8]PIN_Y5SDRAM Address[8] 3.3V DRAM_ADDR[9]PIN_Y6SDRAM Address[9] 3.3V DRAM_ADDR[10]PIN_R5SDRAM Address[10] 3.3V DRAM_ADDR[11]PIN_AA5SDRAM Address[11] 3.3V DRAM_ADDR[12]PIN_Y7SDRAM Address[12] 3.3VDRAM_DQ[0]PIN_W3SDRAM Data[0] 3.3V DRAM_DQ[1]PIN_W2SDRAM Data[1] 3.3V DRAM_DQ[2]PIN_V4SDRAM Data[2] 3.3V DRAM_DQ[3]PIN_W1SDRAM Data[3] 3.3V DRAM_DQ[4]PIN_V3SDRAM Data[4] 3.3V DRAM_DQ[5]PIN_V2SDRAM Data[5] 3.3V DRAM_DQ[6]PIN_V1SDRAM Data[6] 3.3V DRAM_DQ[7]PIN_U3SDRAM Data[7] 3.3V DRAM_DQ[8]PIN_Y3SDRAM Data[8] 3.3V DRAM_DQ[9]PIN_Y4SDRAM Data[9] 3.3V DRAM_DQ[10]PIN_AB1SDRAM Data[10] 3.3V DRAM_DQ[11]PIN_AA3SDRAM Data[11] 3.3V DRAM_DQ[12]PIN_AB2SDRAM Data[12] 3.3V DRAM_DQ[13]PIN_AC1SDRAM Data[13] 3.3V DRAM_DQ[14]PIN_AB3SDRAM Data[14] 3.3V DRAM_DQ[15]PIN_AC2SDRAM Data[15] 3.3V DRAM_DQ[16]PIN_M8SDRAM Data[16] 3.3V DRAM_DQ[17]PIN_L8SDRAM Data[17] 3.3V DRAM_DQ[18]PIN_P2SDRAM Data[18] 3.3V DRAM_DQ[19] PIN_N3SDRAM Data[19] 3.3V DRAM_DQ[20]PIN_N4SDRAM Data[20] 3.3V DRAM_DQ[21]PIN_M4SDRAM Data[21] 3.3V DRAM_DQ[22]PIN_M7SDRAM Data[22] 3.3VDRAM_DQ[23]PIN_L7SDRAM Data[23] 3.3V DRAM_DQ[24]PIN_U5SDRAM Data[24] 3.3V DRAM_DQ[25]PIN_R7SDRAM Data[25] 3.3V DRAM_DQ[26]PIN_R1SDRAM Data[26] 3.3V DRAM_DQ[27]PIN_R2SDRAM Data[27] 3.3V DRAM_DQ[28]PIN_R3SDRAM Data[28] 3.3V DRAM_DQ[29]PIN_T3SDRAM Data[29] 3.3V DRAM_DQ[30]PIN_U4SDRAM Data[30] 3.3V DRAM_DQ[31]PIN_U1SDRAM Data[31] 3.3V DRAM_BA[0]PIN_U7SDRAM Bank Address[0] 3.3V DRAM_BA[1]PIN_R4SDRAM Bank Address[1] 3.3V DRAM_DQM[0]PIN_U2SDRAM byte Data Mask[0] 3.3V DRAM_DQM[1]PIN_W4SDRAM byte Data Mask[1] 3.3V DRAM_DQM[2]PIN_K8SDRAM byte Data Mask[2] 3.3V DRAM_DQM[3]PIN_N8SDRAM byte Data Mask[3] 3.3V DRAM_RAS_N PIN_U6SDRAM Row Address Strobe 3.3V3.3V DRAM_CAS_N PIN_V7SDRAM Column Address StrobeDRAM_CKE PIN_AA6SDRAM Clock Enable 3.3V DRAM_CLK PIN_AE5SDRAM Clock 3.3V DRAM_WE_N PIN_V6SDRAM Write Enable 3.3V DRAM_CS_N PIN_T4SDRAM Chip Select 3.3V 表21 Flash 引脚配置Signal Name FPGA Pin No.Description I/O StandardFL_ADDR[0]PIN_AG12FLASH Address[0] 3.3V FL_ADDR[1]PIN_AH7FLASH Address[1] 3.3V FL_ADDR[2]PIN_Y13FLASH Address[2] 3.3V FL_ADDR[3]PIN_Y14FLASH Address[3] 3.3V FL_ADDR[4]PIN_Y12FLASH Address[4] 3.3V FL_ADDR[5]PIN_AA13FLASH Address[5] 3.3V FL_ADDR[6]PIN_AA12FLASH Address[6] 3.3V FL_ADDR[7]PIN_AB13FLASH Address[7] 3.3V FL_ADDR[8]PIN_AB12FLASH Address[8] 3.3V FL_ADDR[9]PIN_AB10FLASH Address[9] 3.3V FL_ADDR[10]PIN_AE9FLASH Address[10] 3.3V FL_ADDR[11]PIN_AF9FLASH Address[11] 3.3V FL_ADDR[12]PIN_AA10FLASH Address[12] 3.3V FL_ADDR[13]PIN_AD8FLASH Address[13] 3.3V FL_ADDR[14]PIN_AC8FLASH Address[14] 3.3V FL_ADDR[15]PIN_Y10FLASH Address[15] 3.3V FL_ADDR[16]PIN_AA8FLASH Address[16] 3.3V FL_ADDR[17]PIN_AH12FLASH Address[17] 3.3V FL_ADDR[18]PIN_AC12FLASH Address[18] 3.3V FL_ADDR[19]PIN_AD12FLASH Address[19] 3.3V FL_ADDR[20]PIN_AE10FLASH Address[20] 3.3V FL_ADDR[21]PIN_AD10FLASH Address[21] 3.3V。
Excel格式的STM32F103引脚表
2. FT = 5 V tolerant.3. Function availability depends on the chosen device. For devices having reduced peripheral counts, it is always the lower nu4. If several peripherals share the same I/O pin, to avoid conflict between these alternate functions only one peripheral should5. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current (36. Main function after the first backup domain power-up. Later on, it depends on the contents of the Backup registers even aft7. Unlike in the LQFP64 package, there is no PC3 in the TFBGA64 package. The V REF+ functionality is provided instead.8. This alternate function can be remapped by software to some other port pins (if available on the used package). For more de9. The pins number 2 and 3 in the VFQFPN36 package, 5 and 6 in the LQFP48 and LQFP64 packages, and C1 and C2 in th The use of PD0 and PD1 in output mode is limited as they can only be used at 50 MHz in output mode.wer number of peripheral that is included. For example, if a device has only one SPI and two USARTs, they will be called SPI1 and USART1 & US hould be enabled at a time through the peripheral clock enable bit (in the corresponding RCC peripheral clock enable register).nt (3 mA), the use of GPIOs PC13 to PC15 in output mode is limited: the speed should not exceed 2 MHz with a maximum load of 30 pF and the en after reset (because these registers are not reset by the main reset). For details on how to manage these IOs, refer to the Battery backup domore details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual, available from the STMicroe 2 in the TFBGA64 package are configured as OSC_IN/OSC_OUT after reset, however the functionality of PD0 and PD1 can be remapped by so& USART2, respectively. Refer to Table 2 on page 10.nd these IOs must not be used as a current source (e.g. to drive an LED).domain and BKP register description sections in the STM32F10xxx reference manual, available from the STMicroelectronics website: Microelectronics website: .by software on these pins. For the LQFP100 package, PD0 and PD1 are available by default, so there is no need for remapping. For more details, r.com.ails, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual.。
常用三极管引脚参数排列表
L 火线 N 零线 色环电阻的识别方法：1mH81nlMm棕1,红2,橙3,黄4,绿5,蓝6,紫7,灰8,白9,黑0,这是色环电阻的R ：输出电压与最大输出电流的比值。
T ：为交流电周期。
电容降压后的电流计算应按容抗来计算既：Xc = 1/(3 C ) = 1/ (2 n f C ) 常见器耐压的标注是采用一个数字和一个字母组合而成。
数字表示10的幂指数字母=数值A= B=1.25 C= D= E=2.5 F=3.15 G= H= J= K= Z= 例如：2A 代表 *100=100V 1J 代表 *10=63V 常用三极管代表数字。
4环电阻，一 位为误差位。
二位数值位，第3位为倍率(什么颜色就是 10的几次方)，第4 四环色环电阻的误差: 三位数值位，第4位为倍率， 第5位为误差位。
，金表示5%,银表示10% 。
五环色环电阻的误差: 棕表示1%,红表示2%,灰表示％，白表示环保电阻， 绿表示％，蓝表示％，紫表示%，金表示5%，银表示10%例如，4环电阻表示10K 电阻，综黑橙金(10*10的3次方 4环电阻表示10K 电阻，综黑黑红棕(100*10的2次方,5%误差) 1%误差)数字电阻的表示方法为：最后一位数表示倍率，而前几位为数值位。
滤波电容的选择：经验公式：C=(3〜5)(T/2)王R值，单位是V (伏)。
(即乘以10的2次冥) 型号结 构耗散功 率 (mW) Pcm集电极 电流 Max(mA ) Icm集电 极-基极电 压 (V ) Vcbo集电 极- 发射 极电 压 (V)发射 极-基 极电 压 (V ) Vebo引脚排列 放大 系数 hfeVce oA92 PN625 500 300 300 5 EBC P500 500 35 30 5 ECB A562 PNP400 500 35 35 4 ECB A673 PNP1000 1000 30 25 5 ECB A683 PNPA733 PN250 150 60 50 5 EBC P900 1500 30 30 5 ECB A966 PNPA1015 PN400 150 50 50 5 ECB P350 600 160 150 5 EBC 2N5401 PNP1000 1500 40 25 6 EBC S8550 PNP625 500 40 20 5 EBC 8550S PNP625 500 40 20 5 EBC 9012 PNP450 100 50 45 5 EBC 9015 PNP625 500 300 300 6 EBC A42 NPN500 500 40 20 5 EBC D261 NPN300 50 35 30 4 ECB C380 NPN300 50 50 45 4 ECB C383 NPNC388A NP300 50 30 25 4 ECB NC458 NP200 100 30 30 5 ECB NC495 NPN1000 1000 70 50 5 ECBC536 NPN 400 100 55 ] 50 5一] . .ECBC815 NPN400 200 60 45 5 ECBC945 NPN250 150 60 j 50 5 ECBC1008 NPN800 700 80 60 8 EBCC1383 NPN1000 1000 30 25 5 ECBC1627 NPN600 300 80 80 5 ECB型号结构■耗散功率(mW)Pcm集电极］集电］集电］发射电流极-基极-极-基Max 极电发射极电(mA)压极电压Icm (V)压(V)Vcbo (V) VeboVce_____ ・o引脚排列放大系数hfeC1674 NPN250 20 30 20 4 EBCC1815 NPN400 150 60 50 5 ECBC2001 NPN 600 700 30 25 5■. .ECBC2060 NPN750 700 40 32 5 ECBC2229 NPN800 50 200 150 5 ECBC2230 NPN800 100 200 160 5 ECBC2236 NPN C2271 NPN 9009001500 30130 5100 -I 300 300 6- r J I I；：ECBECBC2383 NPN900 1000 160 160 6 ECB C2482 NPN900 100 300 300 7 ECB 2N3904 NPN350 200 60 40 6 EBC 2N5551 NPN350 600 180 160 6 EBC S8050 NPN1000 1500 40 25 6 EBC 8050S NPN625 500 40 20 5 EBC 9011 NPN400 30 50 30 5 EBC 9013 NPN625 500 40 20 5 EBC 9014 NPN450 100 50 45 5 EBC 9016 NPN400 25 30 20 4 EBC 9018 NPN400 50 30 15 5 EBC3DD1300 1 NPN1200 200 600 400 7 BCE 8-40MJE1300 1 NPN7000 300 500 400 9 ECB(to-92 )8-40MJE1300 2 NPN1200 1000 600 400 7 BCE 10-4MJE1300 3 NPN40000 2000 700 400 9 BCE 5-403DD1300 5 NPN75000 4000 700 400 9 BCEMJE1300 5 NPN75000 5000 700 400 9 BCEMJE1300 6 NPN80000 8000 600 300 9 BCE 5-60MJE1300 7 NPN80000 8000 700 400 9 BCEMJE1300 8 NPN1000012000 600 300 9 BCE 6-40MJE1300 9 NPN1000012000 700 400 9 BCE 6-40型号结构耗散功率(mW)Pcm集电极电流Max(mA)Icm集电极-基极电压(V)Vcbo集电极-发射极电压(V)Vceo发射极-基极电压(V)Vebo引脚排列放大系数hfe。
74161引脚功能表
74161引脚功能表74161是一款4位二进制同步计数器，具有多种功能。
它有16个引脚，每个引脚都有特定的功能和用途。
下面是74161引脚功能表的详细介绍：引脚1（CP CLOCK）：时钟输入引脚，用于控制计数器的计数速度。
在每个时钟脉冲上升沿触发。
引脚2（MR MASTER RESET）：主复位引脚，用于将计数器复位为0。
引脚3（PR1 PARALLEL ENABLE）：并行数据输入使能引脚，用于启用并行数据输入。
引脚4（PR2 PARALLEL ENABLE）：并行数据输入使能引脚，用于启用并行数据输入。
引脚5（D0 PARALLEL DATA INPUT）：并行数据输入引脚，用于输入计数器的初始值。
引脚6（D1 PARALLEL DATA INPUT）：并行数据输入引脚，用于输入计数器的初始值。
引脚7（D2 PARALLEL DATA INPUT）：并行数据输入引脚，用于输入计数器的初始值。
引脚8（D3 PARALLEL DATA INPUT）：并行数据输入引脚，用于输入计数器的初始值。
引脚9（R0 REGISTERED DATA OUTPUT）：注册数据输出引脚，用于输出当前计数器的值。
引脚10（R1 REGISTERED DATA OUTPUT）：注册数据输出引脚，用于输出当前计数器的值。
引脚11（R2 REGISTERED DATA OUTPUT）：注册数据输出引脚，用于输出当前计数器的值。
引脚12（R3 REGISTERED DATA OUTPUT）：注册数据输出引脚，用于输出当前计数器的值。
引脚13（MR2 MASTER RESET）：主复位引脚，用于将计数器复位为0。
引脚14（GND GROUND）：接地引脚。
引脚15（QE QUADRATURE INPUT）：正交输入引脚，用于控制输入时钟方向。
引脚16（VCC POWER SUPPLY）：电源引脚。
以上是74161引脚功能表的详细介绍，每个引脚都有特定的功能和用途。
IDE接口引脚定义表
IDE接口引脚定义表--------------------------------------------------------------------------------1、REASET2、GND3-18、DD线19、GND20、NC21、DMARQ22、GND23、DIOW24、GND25、DIOR26、GND27、IORDY28、ALE29、DMACK30、GND31、INTRQ32、IOCS1633、DA134、PDIAG35、DA036、DA237、CXO[size=-1]fx[/size]38、CXI[size=-1]fx[/size]39、DASP40、GND其中3-18DD线的阻值均相同，33、35阻值相同。
2.5英寸笔记本硬盘接口定义-------------------------------------------------------------------------------- 01.RESET# 02.GND03.D7 04.D805.D6 06.D907.D5 08.D1009.D4 10.D1111.D3 12.D1213.D2 14.D1315.D1 16.D1417.D0 18.D1519.GND 20.未用21.GND 22.GND23.HIOW 24.GND25.HIOR 26.GND27.IOCHRDY 28.HALE29.DAKS 30.GND31.IRQBUS 32.IOCS1633.A1 34.未用PDIAG35.A0 36.A237.HCS0 38.HCS139.DASP 40.GND41.+5V逻辑电源(驱动电路板）42.+5V（给电机供电）43.GND 44.NC45. 46.47.D 48.C49.B 50.A2.5英寸笔记本硬盘一般使用50针接口，其中41针一般为驱动逻辑（电路板）提供+5V 电压，42针为电动机提供+5V电压（笔记本硬盘用+5V电机，台式机硬盘用+12V电机）数据D0-D15是主机和驱动器之间的双向传输线RESET#是上电时主机送来的信号，使驱动器复位，其后保持高电平写选通HIOW：当低电平有效时，把主机送来的数据写入寄存器或驱动器的数据寄存器读选通HIOR：当低电平有效时，读某个寄存器或驱动器的数据寄存器地址锁存允许HALE：用于锁存地址信号中断请求IRQBUS：驱动器向主机发送中断请求信号I/O芯片选中IOCS16：它通知主机，16位寄存器已经选中，驱动器准备发送或接收16位数据地址信号A0-A2片选HCS0,HCS1:是主机地址译码后得到的片选信号，选择可直接存取的寄存器。
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附录E LP-2900开发装置FPGA引脚分配
LP-2900以Altera公司EPF10K10TC144-4型或EP1C3T144C8型FPGA为核心，外部接口资源有8个电平按键、6个脉冲按键、2个8位的DIP拨动开关，1个3×4的键盘阵列、34个发光二极管、6个以动态扫描方式连接的共阴七段显示器，1个8×8的双色发光二极管阵列，1个音频蜂鸣器，一个16×2字符的液晶显示屏。
另外还有1片8位的逐次比较模数转换器ADC0804和1片8位的R-2R倒T网络的数模转换器AD7528。
由于开发装置上FPGA 芯片的I/O引脚已经在硬件上与各外部设备相连，设计时必须按照引脚连接关系进行FPGA 引脚分配。
以下按LP2900开发装置面板的划分区域介绍各外设与EPF10K10TC144或EP1C3T144C8的接口关系，由于FPGA的I/O端口有限，所以某些外设受相同的FPGA引脚控制，使用时需要注意。
1．FPGA主板
FPGA主板独立于LP-2900的面板，主板上有一片Altera的FLEX10K系列芯片EPF10K10TC144或CYCLONE系列的芯片EP1C3T144C8、一个EPROM插座或一片配置芯片EPS1和一个复位按键RESET。
主板外围有一圈LED发光二极管，每一个都与EPF10K10TC144-4的一个I/O端口对应连接。
使用者可以通过LED了解FPGA相应I/O端口的状态。
当端口信号为高电平时，LED亮；低电平时，LED灭。
2．电平按键与开关（J区）
J区位于LP2900开发装置面板左下方，有8个带LED显示的电平按键SW1~SW8和2组8位的DIP拨动开关SW9~SW24，位置分布见附录C，与FPGA的连接关系见表E-1。
SW1~SW8按键按下时灯亮，FPGA相应的I/O端口输入高电平；反之灯灭，端口输入低电平。
SW9~SW24拨向上FPGA相应的I/O端口输入高电平；拨向下时FPGA端口输入低电平。
表E-1 电平按键与EPF10K10TC144-4引脚的连接关系
3．脉冲按键（K区）
K区位于LP2900开发装置面板下方中部，有4个带LED显示的脉冲按键PS1~PS4，位置分布见附录C，电路原理见附录D图D-2，与FPGA的连接关系见表E-2。
PS1和PS2为负脉冲按键，未按时LED亮，FPGA相应的I/O端口为高电平；按下时FPGA端口为低电平，FPGA输入一个脉冲下降沿。
PS3和PS4为正脉冲按键，未按时LED灭，FPGA相
应的I/O端口为低电平；按下时LED亮，FPGA端口为高电平，FPGA输入一个脉冲上升沿。
表E-2 脉冲按键与FPGA引脚连接关系
4．键盘阵列（L区）
L区位于K区的右方，有12个排成3列4行的电话键盘阵列。
键盘阵列的行信号由FPGA控制外部的3线-8线的译码器74138扫描驱动，FPGA通过键盘阵列的列信号判断各键的状态，电路原理见附录D图D-3。
74138的译码输入端DE1~DE3以及键盘阵列列信号端RK1~RK3与FPGA的连接关系见表E-3。
表E-3 按键阵列和74138与FPGA引脚的连接关系
5．石英晶体振荡器等（F区）
F区位于LP2900开发装置面板左方，有1个10MHz的石英晶体振荡器OSC，2个带LED显示的负脉冲按键UP、DOWN，8个黄色的LED发光二极管L27~L34，位置分布见附录C。
8个LED的阴级连在一起，由3线-8线译码器74138的Y6控制，FPGA的引脚连接关系见表E-4。
当FPGA引脚DE3、DE2和DE1输出“110”时，74138的输出Y6为低电平，控制L27~L34为高电平可使相应的LED发光。
表E-4 F区外设与FPGA引脚的连接关系
6．LED发光二极管（A区和D区）
A区和D区位于LP2900开发装置面板上方，A区有四组红、绿、黄三色12个LED 发光二极管L1~L12，D区有红、绿两组以电子骰子状分布的14个LED发光二极管L13~L26。
两区的LED阴级分别相连，各由一个反相驱动器控制，反相器的输入分别为ACOM和DCOM。
当控制COM端的FPGA引脚为高电平时，L1~L24的高电平信号使相应的LED发光。
各LED与FPGA的引脚连接关系见表E-5，由于FPGA控制L1~L12与L13~L24的引脚相同，所以A、D两区的发光二极管不能同时使用。
表E-5 A、D区LED与FPGA引脚的连接关系
7．七段共阴显示器（B区）
B区位于A区的下方，从左到右六个共阴极七段显示器C1~C6连接成扫描显示方式，电路原理见附录D图D-1。
每个显示器的阴极分别由3线-8线译码器74138的6个输出Y0~Y5控制，74138的译码输入端受FPGA的DE3~DE1端口控制，引脚编号见表E-4。
显示器的段控制端a~g、dp与FPGA的连接关系见表E-6。
74138输入码不同时，a~g、dp控制不同的显示器显示，对应关系如表E-7所示。
表E-6 七段共阴显示器与FPGA引脚连接关系
表E-7 74138输入码与显示器的控制关系
8．8×8点阵显示器（H区）
B区位于L区按键阵列的上方，有64个发光二极管排成8行8列，电路原理见附录D 图D-5。
每一行发光二极管的阳极连在一起，从上到下分别由ROW1~ROW8控制。
每个发光二极管有两个阴极CR和CG，CR有效时二极管发红光，CG有效时发绿光。
每一列发光二极管的同色阴极连在一起通过反相器驱动，从左到右各列反相器的输入控制信号为CR1~CR8及CG1~CG。
发光二极管点阵各控制端与FPGA的引脚连接关系见表E-8。
表E-8 发光二极管点阵与FPGA引脚的连接关系
9．蜂鸣器（C区）
C区为蜂鸣器BUZZER，电路原理见附录D图D-3，由EPF10K10TC144的引脚Pin46或EP1C3T144C8的引脚Pin54控制。
当FPGA控制端口输出频率范围在20Hz~20kHz之间的脉冲信号时，蜂鸣器鸣响。
10．八位单片微处理机8051（I区）
I区位于LP2900开发装置面板右方，为一个可插Intel MCS51八位单片微处理机的40芯插座和单片机复位按钮RESET。
FPGA通过8位数据总线DB0~DB7与8051的P0口连接，接口关系如表E-9所示。
8051的P1、P2、P3口与FPGA的引脚连接关系见表E-10。
表E-9 FPGA控制数据总线的引脚
表E-10 8051P1、P2、P3口与FPGA引脚连接关系
11。
LCD显示模块（E区）、A/D、D/A转换电路（M区）
LP200开发装置面板右上方E区为16×2的液晶显示屏LCD，右下方M区为8位的模数转换器ADC0804和数模转换器AD7528。
ADC0804、AD7528和LCD控制芯片HD44780的数据端口都与总线DB0~DB7对应相连，电路原理见附录D图D-4，接口关系见表E-9。
HD44780的读/写控制端RW与AD7528的写控制端WR以及ADC0804的读控制端RD相连，由EPF10K10TC144-4的引脚Pin128或EP1C3T144C8的引脚Pin110控制。
其他诸如片选、使能端与FPGA的引脚关系见表E-11。
ADC0804的转换启动端WR由FPGA外部的译码器74138的输出Y7控制，74138的输入端DE3~DE1与FPGA引脚的连接关系见表E-4，当DE3~DE1为“111”时，启动模数转换器ADC0804。
表E-11 HD44780、ADC0804、AD7528控制端与FPGA引脚连接关系。