MOSFET参数详解

Power MOSFET Technical Training
Datasheet Overview
Giovanni Privitera
Senior Product Engineer
MOSFET & IGBT DIVISION
giovanni.privitera@
Maximum
Ratings
Represent the extreme capability of the devices.To be used as worst conditions (single parameter) that the design should
guarantee will not be exceeded. [only VDS & VDGR may be exceeded in limited avalanche conditions]Never exceed !!!!!!!!!!!!
The avalanche breakdown voltage of ST’s PowerMOSFET is always higher than its voltage rating due to normal production process margins.
In order to achieve high forecasted reliability the worst case operating
voltage should be lower than the maximum one. The maximum voltage
during turn off should not exceed 70 to 90% of the rated voltage. This
derating is suggested by the years of experience.For the Drain-Gate Voltage capability
(Rgs to avoid floating gate)
Exceeding Vgs may result in permanent device degradation due to
oxide breakdown and dielectric rupture.
The real oxide breakdown capability is higher than this value, and is related to the oxide thickness; but this value, with a reasonable guardband, is the 100% TESTED & warranted one
Tj must be always lower than 150ºC
Reflects a minimum device service lifetime.Operation at conditions that guarantee a junction temperature less than Tjmax may enhance long term operating life.
Ptot=dT/Rthjc=(150-25)/Rthjc derating=1/Rthjc
The majority of reliability tests are done at maximum junction temperature, especially the HTRB (High Temperature Reversed Bias) and HTFB (High Temperature Forward Bias). These test results are used as input information for calculation of acceleration factors in different reliability models. In order to achieve high forecasted reliability the maximum operating temperature should be lower than the maximum one. For example, by theoretical models, reducing the junction temperature by 30°C will improve the MTBF (Mean Time Between Failure) of the MOSFET by an order of magnitude.
P tot =Ron(@Tjmax)*I²P tot = (Tjmax-Tc)/R THj-c
I= (Tjmax-Tc)/Ron(@Tjmax)*Rthjc
Limited also by wire size : to avoid any fuse effect
Limited by Ptot & Rdson
Maximum dv/dt capability during diode reverse recovery (dynamic dv/dt) To be distinguished two kind of dv/dt (static and dynamic)
Due to the false turn-on, the device falls into the current conduction state, and
in severe cases, high power dissipation develops in the device and creates
destructive failure.
Static dv/dt
a) False turn on
b) Parasitic transistor turn on
If the parasitic bipolar transistor is turned on, the
breakdown voltage of the device is reduced from BVCBO
to BVCEO which is 50 ~ 60 [%] of BVCBO . If the
applied drain voltage is larger than BVCEO, the device
will be brought into the avalanche breakdown, and if the
drain current cannot be limited externally, the device could
be destroyed by the second breakdown of parasitic bipolar.
Diode recovery dv/dt
The value of di/dt and dv/dt becomes larger as Rg is reduced.
The device is destroyed by the simultaneous stresses
such as high drain current, high drain source voltage
and the displacement current of the parasitic
capacitance.
Highest Stress point
ST insulated packages are tested 100% to guarantee this value.
Thermal resistance
Parameter which indicates how "easily" the heat flows between two points A and B
Small R TH implies that the heat is transferred from A to B with little temperature difference between A and B
Large R TH implies that the transfer of the same quantity of heat from A to B requires a greater temperature difference between the two points
Thermal resistance is defined as : R THb-a= (T b-T a)/P diss
Thermal resistance
In electronic devices the two most important temperatures are the ambient temperature T a and the temperature reached by the junction Tj
The R THj-a(device) depends by frame dimension and frame material.
The R THj-a(module) depends by the device, insulation, mounting method, heatsink size and cooling method (forced
air,radiation....)
Thermal resistance Thermal chain exists from the
silicon to the ambient through
the die attach, the frame, the
contact and the external
dissipator.
R THj-a=R THj-c+R THc-s+R THs-a
Thermal model for transient takes
into account thermal capacitances
Rthjc=1/0.32=3.1 K/W
V=Ron(@Tj)*I
K=0.1
Zth=kRth V I=(Tj-Tc)/Zth K=0.04
K=0.01K=1Allowed but not reachable region
Zth: Transient Thermal Impedance
Ptot(dc)=(Tj-Tc)/Rth(j-c)
Ptot(pulse)=(Tj-Tc)/Zth(j-c)
Iar, defined as the maximum current that can flow through the device during the avalanche operations without any bipolar latching phenomenon.
EAS(Energy during Avalanche for Single Pulse) is defined as the maximum energy that can be dissipated in the device during a single avalanche operation, at the Iar and at the starting junction temperature of 25°C, to bring the junction temperature up to the maximum one stated in the absolute maximum ratings.
E=0.5*L*I 2
*(V(BR)eff/(V(BR)eff-VDD))
E=0.5*V(br)eff*Io*tav
Unclamped Inductive Switching
N-
P+
N+
S G
D
D
R p
S G
Failure mode
Vbe
Id
1-As soon as the current begins to interest the p region causing a sufficient drop of voltage to equal the VBEon of the BJT, the current of the base, IB, in conjunction with the of the transistor will cause the localized BJT turn-on. Subsequent local temperature increase decreases Vbeon and runaway occurs.
2-The power that is dissipated in the MOSFET causes an increase of temperature of the junction. If the temperature increases to a critical value set by the property of the silicon, the failure, without the contribution of the parasitic bipolar, occurs because of the creation of thermally generated carriers in the epitaxyal / bulk region and so the creation of hot spots.
A
t K P T 320=D Very short rectangular pulses (~tens ms)Triangular impulses haven’t the same thermal response time Tj
A
t K Zth =A
t K P T 0=D Eas calculation: thermal model
Die Area
The EAS is function of Die size Silicon characteristics Peak power Starting and maximum temperature
202
204921K
P T A t P Eas av D ==2202229K P T A t av D =with
00.050.10.150.20.250.30.350.40.45
T (50µs/div )
-200
020040060080010001200V d s (V )
-5
0510********I d (A )
FAIL FOR PARASITIC CONDUCTION
UIS ON ST W8NB90
Vdd=150V; L=1mH; Vgs=10V; Rg=47 ohm; startingTj=25°C
0.20.40.60.811.21.41.61.8
T (200µs/div )
-200
020040060080010001200V d s (V )
-2
024681012
I d (A )
FAILURE FOR ENERGY
UIS ON STW8NB90
Vdd=150V; L=16mH; Vgs=10V; Rg=47 ohm; startingTj=25°C
UIS:Failure mode
●Current Crowding due to Parasitic BJT Turn-on
●
Thermal Dissipation with Tj highly exceeding the guaranteed Tjmax (150 degC)
D
G
S
Tracer waveform
As junction temperature increases, BV also increases linearly,
D
G
S IDSS is sensitive to the temperature and it has positive temperature coefficient.
D G
S
D
G
S Threshold voltage VGS(th) is the minimum gate
voltage that initiates drain current flow.
VGS(th) has a negative temperature coefficient
D
G
S RDS(on) is not constant vs Id
RDS(on) has a positive temperature coefficient
D
S
G
Gfs=
di ds
dv gs Vds=const T
G
D
S
C GS
C DS
C GD
C iss = C G
D + C GS C oss = C DS + C GD C rss = C GD
Temperature variations have very little effect
Resistive load switching
V D
V G =0I D =0
I DS [A]
V DS [V]
500
4
3
2
1
01
43
2
56Resistive load switching
1
V D
V G =0I D ~0
V G = V Th
500
4
3
2
1
01
43
2
56Charging the Ciss to Vth.
No evident drain current flows;Vds remains essentially at Vdd
V DS [V]
DS
1
V D
V G =0I D =0
V T
500
4
3
2
1
01
43
2
56Continues the Ciss Charging. Drain current starts to flow;Vds remains essentially at Vdd
V DS [V]
DS
1
V D
V G =0I D =0
V G = V Gm
V T
500
4
3
2
1
01
43
2
56Continues the Ciss Charging.
Drain current flows to the maximum;Vds remains essentially at Vdd
V DS [V]
DS
V G =01
V D
I D =0
V G = V Gm
V T
500
4
3
2
1
01
43
2
56Cgd is Charging and Ciss increases mantaining Vg flat. Id constant
Vds approaches to Vdson
V DS [V]
DS
1
V D
V G =0I D =0
V T
500
4
3
2
1
01
43
2
56MOSFET in ohmic region.
Vg increases to applied voltage charging input capacitances
V DS [V]
DS
V G =01
V D
I D =0
V T
500
4
3
2
1
01
43
2
5
6V DS [V]
DS
V G =01
V D
I D =0
V T
500
4
3
2
1
01
43
2
5
6V DS [V]
DS
10V It is used to determine the amount of charge, defined as Qg, required to bring the Ciss from 0V to 10V
D
S
G
ISD
Irrm
Q rr~0.5t rr*I rrm。