研究生PLD&SOPC实验 Xilinx SOPC开发环境1
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P L D
I/O-centric
2003
Lowest “Cost per I/O”
Non-Volatile FPGA
New
Generation
•Hardened DSP
and Embedded
Processing
Functionality
•Enhanced power
management
•Market-optimized
•I/O Solutions
“Trilogy”
•1.6M system gates
•648Kbits Block RAM
•376 I/O pins
•325MHz multipliers
•SPI flash support
•Targets Digital
Consumer Market
•Mini-LVDS, PCI-64/66,
PCI-X, DDR 333
•$2 for 100K gates
•$9 for 1.2M gates
Spartan-3E
•Low Power
•Up to 98%
quiescent
power
reduction
•5M system gates
•1.8Mbits Block RAM
•784 I/O pins
•18x18 Multipliers
for Low-cost DSP
•Soft Embedded
Processing
Capability
Spartan-3
Lowest Cost
Spartan-3L
20082010
20002004CoolRunner-II
Spartan-3E
100 MHz, 92 DMIPS
Next Generation
Spartan
Spartan-3
100 MHz, 92 DMIPS
Virtex-II Pro
150 MHz, 120 DMIPS
Virtex-4
200 MHz, 160 DMIPS
Rainier
Mont Blanc
Virtex-4, 450 MHz
Virtex-II Pro
Rainier
Mont Blanc
Trilogy
Flexible Soft IP
MicroBlaze ™
32-Bit RISC Core
UART
10/100E-Net
On-Chip Peripheral
FLASH/SRAM FSL
FIFO Channels 0,1 (7)
Custom Functions
Custom Functions
BRAM
Local Memory
Bus
D-Cache
BRAM
I-Cache BRAM
Configurable Sizes
A r b i t e r
Processor Local Bus
Instruction
Data
PLB
Bus Bridge
PowerPC 405 Core
Dedicated Hard IP
Possible in Virtex-II Pro
Hi-Speed Peripheral
E-Net
GB Memory e.g.Controller
A r b i t e r
OPB
On-Chip Peripheral Bus