数字电路英文版-第十二单元

② Read
8
§12.2 RANDOM-ACCESS MEMORIES (RAMs)
RAMs are real/write memories in which data can be written into or read from any selected address in any sequence. A RAM is typically used for short-term data storage because it cannot retain stored data when power is turn off.
①
Leabharlann Baidu
2
3
Address bus
4
5
6 7
Data register
11000001
1 1 00 0 0 10 10 10 0 0 11
01 0 01 0 10 11 0 000 01 1 1 101 00 0 1 0 0 0 1 1 01 0 1 1 10 01 0 10 0 0 0 0 0 0
③
Data bus
16
1 2 3 4 5 6
62 63 64
1
1 2 3 4 (c) 64*1 array
(b) 16*4 array
4
Memory Address and Capacity
1 2 3 4 5 6 7 8
12 3 4 5 1 7 8
(a) The address of the bit highlighted in blue is row 5, column 4.
Bit 0
Bit 1 Bit 2 Bit 3
11
256 rows
Memory array
256 rows x 128 X 8 columns
128 columns
8 bits
12
Address lines
Row decoder
I/O1 I/O8
CS WE OE
Input data control
Read Write
6
Basic Memory operations 1
The Write Operation
Address register
101
Address 0
decoder 1
①
2
3
Address bus
4
5
6 7
Data register
1
10001101
1 1 00 0 0 10
10 10 0 0 11
9
Static RAMs (SRAMs)
Bit Select
+Vcc
Data
Data
10
Row Select 0 Row Select 1 Row Select 2
Row Select n
Data Input/Output Buffers and Control
Data I/O Data I/O Data I/O Data I/O
Burst Logic
Burst control CLK
Binary counter Q1 Q0
A0 A1
LSBs of external address
A0’ LSBs of
internal
A1’
burst address
Cache Memory : Cache memory is a relatively small, high-speed memory that stores the most recently used instructions or data from the larger but slower main memory.
2
Units of Binary Data:
Bits, Bytes, Nibbles, and Words
18 4
n* 8 ( 9 )
3
The Basic Semiconductor Memory Array
1
1
2
2
3
3
4
4
5
5
6
6
7
8
12 3 4 5 6 7 8
13
14
15
(a) 8*8 array
01 0 01 0 10
11 0 000 01 1 1 101 00 0
②
1 0 0 0 1 1 0 1 Data bus
0 1 1 10 01 0
10 0 0 0 0 0 0
③ Write
7
The Read Operation
Address register
011
Address 0
decoder 1
CHAPTER 12 MEMORY AND STORAGE
§12.1 BASICS OF SEMICONDUCTOR MEMORY
Memory is the portion of a system for storing binary data in large quantities. Semiconductor memories consist of arrays of storage elements that are either latches or capacitors.
1 2 3 4 5 6 7 8
12 3 4 5 1 7 8
(b) The address of the byte highlighted in blue is row 3.
5
Basic Memory operations
Address decoder
Address bus
Memory array
Data bus
G1 G2
Memory array
256 rows x 128 x 8 columns
Column I/O Column decoder
Output data
Address lines
13
The Burst Feature
Synchronous SRAMs normally have an address burst feature, which allows the memory to read or write at up to four locations using a single address.
Cache Analogy : refrigerator ( cache ) supermarket
14
Cache (CLK )
L1 and L2 Caches
Microprocessor
L1 cache (internal)
Data bus
Address bus
Cache controller
L2 cache (SRAM)
Main memory ( DRAM )