设计时序逻辑时采用阻塞赋值与非阻塞赋值
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时序逻辑设计
‐‐‐‐‐‐‐‐‐阻塞赋值与非阻塞赋值区别
阻塞式
`timescale 1ps/1ps
module blocking(b,c,a,clk);
output [3:0] b,c;
input [3:0] a;
input clk;
reg [3:0] b,c;
always @(posedge clk)
begin
b = a;
c = b;
$display("Blocking: a = %d, b = %d, c = %d.",a,b,c);
end
endmodule
非阻塞式
`timescale 1ps/1ps
module non_blocking(clk,a,b,c);
output [3:0] b,c;
input [3:0] a;
input clk;
reg [3:0] b,c;
always @(posedge clk)
begin
b <= a;
c <= b;
$display("Non_Blocking: a = %d, b = %d, c = %d.",a,b,c); end
endmodule
Testbench
`timescale 1ps/1ps
module test_tp();
wire [3:0] b1,c1,b2,c2;
reg [3:0] a;
reg clk;
initial
begin
clk = 0;
forever #50 clk = ~clk;
end
initial
begin
a = 4'h3;
$display("____________________________");
# 100 a = 4'h7;
$display("____________________________");
# 100 a = 4'hf;
$display("____________________________");
# 100 a = 4'ha;
$display("____________________________");
# 100 a = 4'h2;
$display("____________________________");
# 100 $display("____________________________");
$stop;
end
non_blocking non_blocking1(.clk(clk),.a(a),.b(b2),.c(c2)); blocking blocking1(.clk(clk),.a(a),.b(b1),.c(c1)); endmodule
Transcript
# ____________________________
# Blocking: a = 3, b = 3, c = 3.
# Non_Blocking: a = 3, b = x, c = x.
# ____________________________
# Non_Blocking: a = 7, b = 3, c = x.
# Blocking: a = 7, b = 7, c = 7.
run
# ____________________________
# Non_Blocking: a = 15, b = 7, c = 3.
# Blocking: a = 15, b = 15, c = 15.
run
# ____________________________
# Non_Blocking: a = 10, b = 15, c = 7.
# Blocking: a = 10, b = 10, c = 10.
run
# ____________________________
# Non_Blocking: a = 2, b = 10, c = 15.
# Blocking: a = 2, b = 2, c = 2.
run
# ____________________________
Author: Apple Cai
Data: 31 Aug 2010