【电子科技大学】2015下数字逻辑设计(作业题)Chapter 4 Exercise Solutions(对应老教材第3章题号)

Chapter 4

【以下为老版教材（John F. Wakerly著）的题号】

3.1 The Stub Series Terminated low Voltage logic (SSTV) family, used for SDRAM modules, defines a LOW signal to be in the range 0.0～0.7V, and a HIGH signal to be in the range 1.7～2.5V. Under a positive-logic convention, indicate the logic value associated with each of the following signal levels:

(a) 0.0V (b) 0.7V (c) 1.7V (d) -0.6V

(e) 1.6V (f) -2.0V (g) 2.5V (h) 3.3V

(a) 0 (b) 0 (c) 1 (d) undefined

(e) undefined (f) undefined (g) 1 (h) undefined

3.2 Repeat exercise 3.1 using a negative-logic convention.

(a) 1 (b) 1 (c) 0 (d) undefined

(e) undefined (f) undefined (g) 0 (h) undefined

3.5 True or false: For a given set of input values, a NAND gate produces the opposite output as a NOR gate.

When the two inputs are different, it will be ture.

3.9 For a given silicon area, which is likely to be faster, a CMOS NAND gate or a CMOS NOR?

CMOS NAND will be faster than CMOS NOR.

3.11 The circuit in Figure 3-1 is a type of CMOS AND-OR-INVERT gate. Try to wirte its logic expression and draw its logic diagram using the method Mr. yuan told you with AND and OR gates and inverters.

Figure 3-1

A B C D Z 0 X 0 0 1 X 0 0 0 1 -- -- -- -- 0

∵ A • B = 0 且 (C + D) = 0 即 A • B + (C + D) = 0 ∴ Logic expression: Z = ( A • B + C + D )’

Logic diagram:

3.16 Which has fewer transistors, a CMOS inverting gate or a noninverting gate?

CMOS inverting gate has fewer transistors.

3.21 How much high-state DC noise margin is available in an inverter whose transfer characteristic under worst-case conditions is shown in Figure 3-2? How much low-state DC noise margin is available? Assume 1.5V and 3.5V thresholds for LOW and HIGH. (Hints : The thresholds voltage means a input voltage. That is to say: V ILmax =1.5V ，V IHmin =3.5V )

Figure 3-2

从图中可以看出，在输入为0~1.5V 的有效低态范围内，输出的高态范围为4.75~5V ，即V OHmin =4.75V ，在输入为3.5V~5V 的有效高态范围内，输出的低态范围为0~0.25V ，即V OLmax =0.25V 。

High-state DC noise margin = V OHmin - V IHmin = 4.75 - 3.5 = 1.25 (V)

Low-state DC noise margin = V ILmax - V OLmax = 1.5 - 0.25 = 1.25 (V)

(C + D) A • B 且

3.27 For each of the following resistive loads, determine whether the output drive specifications of the 74HC00 over the commercial operating range are exceeded (use V OLmax = 0.33V ，V OHmin = 3.84V and V CC = 5.0 V). You may not exceed I OLmax (4mA) or I OHmax (4mA) in any state.

(d) 470 Ω to V CC and 470 Ω to GND (f) 1.2k Ω to V CC and 820 Ω to GND

(d) V Thev = Vcc ×R2 / (R1+R2)

= 5 / 2 = 2.5V

I Short = Vcc / R1 R Thev = V Thev / I Short = R1×R2 / (R1+R2) = 470 / 2

= 235 Ω

∵V OHmin = 3.84V ∴ I OH = (V OHmin -V Thev

Thev OHmax ∵V OLmax = 0.33V ∴ I OL = (V Thev - V OLmax ) / R Thev ≈ 9.2 mA

> I OLmax = 4 mA 因此，超出了商用工作范围，不能驱动负载。

(f) V Thev = Vcc ×R2 / (R1+R2)

= 5×820 / (1200+820)

≈ 2.03V I Short = Vcc / R1

R Thev = V Thev / I Short = R1×R2 / (R1+R2)

= 1200×820 / (1200+820)

≈ 487.13 Ω

∵V OHmin = 3.84V ∴ I OH = (V OHmin -V Thev ) / R Thev ≈ 3.7 mA < I OHmax = 4 mA ∵V OLmax = 0.33V ∴ I OL = (V Thev - V OLmax ) / R Thev ≈ 3.5 mA < I OLmax = 4 mA 因此，没有超出商用工作范围，可以正常驱动负载。

3.37 A particular Schmitt-trigger inverter has V ILmax = 0.8 V, V IHmin = 2.0 V, V T+ =1.7 V, and V T - = 1.2 V. How much hysteresis does it have?

Hysteresis = V T+ - V T - = 1.7-1.2 = 0.5V

3.39 Discuss the pros and cons of larger versus smaller pull-up resistors for open-drain CMOS outputs.

较小的上拉电阻：优点是输出电平在上升时较快，使得其工作运行的速度较快；缺点是在输出低电平时电源对地的电流较大，使得其功耗较大。

较大的上拉电阻：优点是在输出低电平时电源对地的电流较小，使得其功耗较小；缺点是输出电平在上升时较慢，使得其工作运行的速度较慢。

3.47 How many diodes are required for an n -input diode AND gate?

n diodes are required.