ICC版图综合实例

Core area here: width=300um height=100um Green rectangle is the pin – follow what we define in pin constraint file
Unplaced STD here
Floorplan
Create PG ring
Place
set_operating_conditions -analysis_type on_chip_variation -max ss_1p62v_125c -min ff_1p98v_0c Select mode “on_chip_variation” for better optimize “MAX” using the slow library “MIN” using the fast library
“my_clock” is the only clock in our design. “max_transition” defined by yourself according to the process. “max_capacitance” defined by yourself according to the process. “max_fanout” you can ask FE designer. “max_buffer_levels” also can get from FE designer. “target_skew” we do CTS is right to decrease the skew. The smaller the better.
Floorplan
Usually we report timing info. in the ideal condition just after floorplan done. If there report any timing violation, please contact with FE designer, his/her design is wrong. (We can do nothing because we even do not place and route, everything is the best condition in our layout design now.)
Design input
Then use following command to make design active.
Design input
Read timing constraint file (.sdc) into design
Though there are some warning, but it’s okay because sometimes FE design just need to designer like that. Confirm with FE designer first.
Floorplan
Initial the core area initialize_rectilinear_block -shape L -control_type length -core_side_dim {300 100 0 0 300 100} -orientation N -core_utilization 1 -row_core_ratio 1.00 -start_first_row -flip_first_row -left_io2core 1.1 -right_io2core 1.1 top_io2core 1.1 -bottom_io2core 1.1
Cell for CTS
Antenna rule file
Filler cell
Design & Input data definition
Design input
Create_mw_lib Read_verilog
335 std cells are used
Design input
Read verilog netlist successfully! Then you can see the physical view in last page.
Make PG strap to decrease the IR drop from P/G IO to each cell
Floorplan
You can report physical info. using following command report_design -physical
ICC版图综合实例
根据逻辑综合组最后的结果 进行版图综合
步骤
Design setup & input Floorplan Place CTS Route Design Finishing
步骤
Design setup & input Floorplan Place CTS Route Design Finishing
Place
report_placement_utilization To see the area info.
Actually the design utilization is very low, you will be killed by your boss if you design like that in real product. But for we, remain enough margin has the first priority. In real design, the utilization after place depends, usually, 70% wil; input Floorplan Place CTS Route Design Finishing
Floorplan
Read pin constraints Read_io_constraints ../input/pin_order.tcl
Place
Report timing info. after place. Suppose the setup violation should be almost clean after place. Because setup is hard to fix by hand.
步骤
Design setup & input Floorplan Place CTS Route Design Finishing
CTS
set_operating_conditions -analysis_type on_chip_variation -max ss_1p62v_125c -min ff_1p98v_0c Still use on_chip_viaration to get better optimize. set_clock_tree_options -clock_tree my_clock -max_transition 0.3 max_capacitance 0.900 -max_fanout 6 -max_buffer_levels 20 target_skew 0.000 -buffer_relocation TRUE -gate_sizing FALSE delay_insertion FALSE -buffer_sizing TRUE -gate_relocation TRUE
Floorplan
Create PG strap
create_power_straps -direction vertical -start_at 40 -num_placement_strap 7 increment_x_or_y 38 -nets {VDD GND} -layer M4 -width 2 -pitch_within_group 2
Design setup
Design_name: VLSI_TOP Other setup
Logic library
Physical library
Parasitical parameter file
Design setup
Cell for hold time fixing
Cell for tie high/low
Global skew after CTS is 0.00557
CTS
Report timing info. after CTS Suppose no setup violation after CTS, because routing only can make setup time worse. And setup time is hard to be fixed by hand.
Place
place_opt -area_recovery -effort medium If the design is big, maybe the command will operated several times to get a better result.
After command operated, all STD cells are placed into the core area.
We are lucky that there isn’t any violations after CTS.
CTS
Now let us see a detail path timing report!
Path type:max It’s a path to check setup.
This is defined in sdc
create_rectangular_rings -nets {GND VDD} -left_offset -7 -left_segment_layer M4 left_segment_width 3 -right_offset -7 -right_segment_layer M4 -right_segment_width 3 bottom_offset -7 -bottom_segment_layer M5 -bottom_segment_width 3 -top_offset -7 top_segment_layer M5 -top_segment_width 3
CTS
clock_opt -only_cts -no_clock_route -cts_effort high
The highlight cell is the cells that added automatically for CTS.
CTS
Report the CTS info. of “my_clock” “report_clock_tree”
Library setup time
CTS
Setup time requirement = data required time – data arrival time Hold time requirement = -data required time + data arrival time
Set ideal condition before report!
Thanks god, our FE designer is an expert!
步骤
Design setup & input Floorplan Place CTS Route Design Finishing
width: pin metal width; side: 1-west, 2-north, 3-east, 4-south; offset: distance to the start point of each side; layers: metal layer used for this pin