SystemVerilog验证方法实例 random_generator

EXAMPLE: module Tb(); integer add_1;
initial begin repeat(5) begin #1; add_1 = $random % 10; end end
initial $monitor("add_1 = %d",add_1);
endmodule
RESULT:
#10 clock = ~clock;
Task And Function
end
Process Control
Disableing The Block
initial
Watchdog
begin
Compilation N
repeat(5)@(negedge clock)
Simulation Switchs
Index
Introduction
Linear Tb
File Io Tb
State Machine Based
Verilog has system function $random ,which can be used to generate random Tb
input vectors. With this approach, we can generate values which we wouldn't Task Based Tb
We have seen how to generate random numbers. But the numbers range from ‑ (2**32 ‑1) to 2 **32. Most of the time, the requirement don't need this range. For example, take a memory. The address starts from 0 to some 1k or 1m.Generating a random address which DUT is not supporting is meaningless. In verilog there are no constructs to constraint randomization. Fallowing example demonstrated how to generate random number between 0 to 10.Using % operation, the remainder of any number is always between 0 to 10.
EXAMPLE: module Tb(); integer add;
initial begin repeat(5) begin #1; add = 40 + {$random} % (50 ‑ 40) ; $display("add = %d",add); end end endmodule
RESULT:
Report a Bug or
Comment on This
section ‑ Your input is
what keeps Testbench.in
$random() system function returns a new 32‑bit random number each time it is improving with time!
have got, if listed manually. In this topic I would like to discuss what natural Self Checking
things happening behind $random and how we use it in different manners.
Testbench
Verification Flow
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Clock Generator
Simulation
EXAMPLE:
Incremental
module Tb_mem();
Compilation
reg clock;
Store And Restore
reg read_write;
Event Cycle Simulation
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module Tb(); integer address;
WWW.TESTBENCH.IN - Verilog for Verification
initial begin repeat(5) #1 address = $random; end
The above example shows the generation of numbers from 0 to N.Some specification require the range to start from non Zero number. MIN + {$random} % (MAX ‑ MIN ) will generate random numbers between MIN and MAX.
add = 48 add = 47 add = 47 add = 47 add = 47
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initial $monitor("add_3 = %d;add_2 = %d;add_1 = %d",add_3,add_2,add_1);
endmodule
RESULT:
add_3 = 7;add_2 = 7;add_1 = 8 add_3 = 7;add_2 = 7;add_1 = 4294967287 add_3 = 1;add_2 = 2;add_1 = 4294967295 add_3 = 7;add_2 = 8;add_1 = 9 add_3 = 9;add_2 = 2;add_1 = 9
reg [31:0] data;
Time Scale And
reg [31:0] address;
Precision
Stimulus Generation
initial
System Function
begin
Random A Myth
clock = 0;
Race Condition
forever
Checker
$monitor($time,"read_write = %d ; data = %d ; address = Finding Testsenarious
%d;",read_write,data,address);
Handling Testcase Files
Terimination
endmodule
add_1 = 8; add_1 = 4294967287; add_1 = 4294967295; add_1 = 9; add_1 = 9;
OOPS!...... The results are not what is expected. The reason is $random generates negative numbers also. The following example demonstrates proper way of generating a random number between 0 to 10. Concatenation operator returns only bit vector. Bit vectors are unsigned, so the results are correct as we expected. Verilog also has $unsigned systemtask to convert signed numbers to
called. The random number is a signed integer; it can be positive or negative.
The following example demonstrates random generation of signed numbers.
EXAMPLE:
initial $monitor("address = %d;",address);
endmodule
RESULT:
address = 303379748; address = ‑1064739199; address = ‑2071669239; address = ‑1309649309; address = 112818957;
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WWW.TESTBENCH.IN - Verilog for Verification signed number. This can also be used to meet the requirements. The following example shows the usage of concatenation operator and $unsigned.
begin read_write = $random ; data = $random;address = $random; end
Debugging
$finish;
About Code Coverage
end
Testing Stratigies
File Handling
initial
Verilog Semaphore
13-12-17
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40read_write = 1 ; data = 112818957 ; address = 1189058957;
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60read_write = 1 ; data = 2302104082 ; address = 15983361;
80read_write = 1 ; data = 992211318 ; address = 512609597;
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SYSTEM FUNCTION RANDOM A MYTH
EXAMPLE: module Tb(); integer add_2; reg [31:0] add_1; integer add_3;
initial begin repeat(5) begin #1; add_1 = $random % 10; add_2 = {$random} %10 ; add_3 = $unsigned($random) %10 ; end end
Error Injuction
Register Verification
RESULT:
Parameterised Macros
White Gray Black Box
20read_write = 0 ; data = 3230228097 ; address = 2223298057;
Regression