Synthesis Optimization - 综合优化,来自synopsys

Applies globally, no local setting Results are saved in .sdc file Turn option OFF for subsequent runs

Saves
on run time
10
Global Setting

The difference between FSM Compiler and FSM Explorer is the way the encoding is selected. FSM Compiler select the encoding style solely based on the number of states, while FSM Explorer applies each style to the state machine and select the most performant. This results is FSM Explorer running slightly longer than FSM Compiler. While FSM Compiler can be applied locally or globally, FSM Explorer is always a global switch.
[0:3]
state[0:3]
un1_un1_in1_1
rst clk
next_state[1:3]
[1]
un1_in1_1
[1]
un1 un1 in1
9
FSM Explorer Option

Option set in the Project window

Saved in the project file for each implementation
7

Beginning with the C-2009.09-SP1 release, the behavior for retiming unconstrained I/O pads has changed. If retiming is enabled, registers connected to unconstrained I/O pins are not retimed by default. If you want to revert back to how retiming I/O paths was previously implemented, you can:



Flip-flops with no control signals (resets, presets, and clock enables) are moved. Flip-flops with minimal control logic can also be retimed. Multiple flip-flops with reset, set or enable signals that need to be retimed together are only retimed if they have exactly the same control logic. The software does not retime the following combinatorial sequential elements: flip-flops with both set and reset, flip-flops with attributes like syn_preserve, flip-flops packed in I/O pads, level-sensitive latches, registers that are instantiated in the code, SRLs, and RAMs. If a RAM with combinatorial logic has syn_ramstyle set to registers, the registers can be retimed into the combinatorial logic. Retimed flip-flops are only moved through combinatorial logic. The software does not move flip-flops across the following objects: black boxes, sequential components, tristates, I/O pads, instantiated components, carry and cascade chains, and keepbufs. For Altera designs, registers that are in counter modes are not retimed to preserve the performance benefit of the counter mode.
4
Retiming

Retiming in the Synplify Pro tool is register balancing

Registers moved across combinatorial logic to improve timing Timing driven
Global Setting
After Retiming
[2] [1] [0]
[2]
D Q
[2]
ff_2_.Q
[1] [0] [2]
output
nput1[2:0]
[2:0]
D Q
g1_1.G_2
nput2[2:0]
[2:0]
ff_ret.Q
g1
output.G_3
6

Here are some implications and results of retiming:
FSM Explorer uses FSMs extracted by FSM Compiler
runs
through each coding style (sequential, binary, gray) for each state machine in the design will select best implementation
2

Re-timing FSM Compiler & FSM Explorer Shannon Expansion Operand Reordering Setting Fanout Limits Route Constraint
3
Re-timing

What is Re-timing>
Automatically
moving registers across combinatorial logic to improve timing while ensuring identical logic behavior Up to 20% Faster (ave. 5%) Retiming is timing based
@N:MT322 : | Clock constraints cover only FF-to FF paths associated with the clock.
8
FSM Compiler Option

Netlist Optimization by State Machine detection
Synthesis Optimization
Timing Optimizations Settings
Use realistic design constraints, about 10 - 15% of the real goal. Over constraining your design can be counterproductive. Use clock, false path, and multicycle path constraints to make the constraints realistic. Select a balanced fanout constraint. A large constraint creates nets with large fanouts, and a low fanout constraint results in replicated logic. If the critical path goes through arithmetic components, try disabling Resource Sharing. You can get faster Times at the expense of increased area, but use this technique carefully. If the P&R and synthesis tools report different critical paths, use a timing constraint with the -route option. For FSMs, use the onehot encoding style, because it is often the fastest implementation. If a large output decoder follows an FSM, gray or sequential encoding could be faster. For designs with black boxes, characterize the timing models accurately, using the syn_tpd, syn_tco, and syn_tso directives. Make sure that you pass your timing constraints to the place-and-route tools, so that they can use the constraints to optimize timing.
clk
[1]
D Q
[1]
ff_1_.Q
This attribute marks the register as one that can be moved during retiming, but does not necessarily force it to be moved during retiming
0 [1:2]
out1[2:0]
in1
[3]
un1_in1_2
[3]
un1_un1_in1_2
010 001 [2] 100 010 000 100 [2] [0] 001
un1_in1_3
e d e d e d e d e d e d e d
[1:3] [1:3]
D[3:0] Q[3:0] R PAT
clk nput1[2:0]
[2:0] [0] [2] [1] [0]
D Q
[0]
ff_0_.Q
nput2[2:0]
[2:0]
[1] [0] [2]
output
g1_1.G_2
g1
output.G_3
Names of the registers created as a result of retiming, and which did not exist in the RTL view. The added registers have a _ret suffix

Global switch in Project window Assignment by syn_allow_retiming attribute

ห้องสมุดไป่ตู้
Global
Global Setting

Individual register
Local Setting
5
Retiming Example
Before Retiming


– Globally turn on the Use clock period for unconstrained IO switch from the Constraints tab of the Implementation Options panel. – Add constraints to all input/output ports. – Separately constrain each I/O pin as required