ispLever使用教程演示幻灯片
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architecture rtl1 of and_gate is begin X<=A AND B; end rtl1;
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library ieee; use ieee.std_logic_1164.all;
entity decoder is PORT(input:IN std_logic_vector(2 downto 0);
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library ieee; use ieee.std_logic_1164.all;
entity decoder_38 is PORT(input:IN std_logic_vector(2 downto 0);
output:OUT std_logic_vector(7 downto 0)); end;
entity dff1 is port(clk,d:in std_logic; q:out std_logic);
end;
architecture rtl of dff1 is begin
process(clk) begin
if(clk'event and clk='1')then q<=d;
end if; end process; end rtl;
end process; end rtl1;
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library ieee; use ieee.std_logic_1164.all;
entity ym3_8 is port(a:in std_logic_vector(2 downto 0); y:out std_logic_vector(7 downto 0));
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选器件
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点击下一步
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点击New
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后面的操作同前
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作业：用VHDL语言： 1、设计一个3线－8线译码器； 2、设计一个上升沿触发JK触发器。
CLR
JQ
CLK
K
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library ieee; use ieee.std_logic_1164.all;
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双击Generate Schematic Symbol
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点击器件ispLSI1032E-70LJ84
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双击Fit Design
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下载
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（八）ISPLEVER 软件的使用方法
2、VHDL的原理图方式设计
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点击File —>New Project
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选VHDL Module
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填入文件名、实体名（两者要一致）和
结构体名
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点
OK
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输入程序
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保存
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退出
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点击dff1(dff1.vhd)
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源程序编写完成以后是综合 双击Synplify Synthesize VHDL File
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双击VHDL Test Bench Template
end ym3_8;
architecture rtl of ym3_8 is begin process(a)
case a is when "000"=>y<="11111110"; when "001"=>y<="11111101"; when "010"=>y<="11111011"; when "011"=>y<="11110111"; when "100"=>y<="11101111"; when "101"=>y<="11011111"; when "110"=>y<="10111111"; when others=>y<="01111111";
architecture rtl1 of decoder is begin
process(input) case input is when "000"=>yout<="11111110"; when "001"=>yout<="11111101"; when "010"=>yout<="11111011"; when "011"=>yout<="11110111"; when "100"=>yout<="11101111"; when "101"=>yout<="11011111"; when "110"=>yout<="10111111"; when "111"=>yout<="01111111"; end case;
ISPLEVER 软件的使用方法
1、VHDL的文本方式设计
1
点击程序－>Lattice Semiconductor—> ispLEVER Project Navigator
2
点击File —>New Project
3
输入项目名，选VHDL，点下一步
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选器件
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点击下一步
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点击完成
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点击Source —New
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library ieee; use ieee.std_logic_1164.all;
entity and_gate is PORT(A,B:IN std_logic;X:OUT
std_logic); end;
architecture rtl of and_gate is begin X<=A AND B; end rtl;
end process; end rtl1;
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library ieee; use ieee.std_logic_1164.all;
entity decoder is PORT(input:IN std_logic_vector(2 downto 0);
yout:OUT std_logic_vector(7 downto 0)); end;
output:OUT std_logic_vector(7 downto 0)); end;
architecture rtl1 of decoder is begin
process(input) case input is when 0=>output<="11111110"; when 1=>output<="11111101"; when 2=>output<="11111011"; when 3=>output<="11110111"; when 4=>output<="11101111"; when 5=>output<="11011111"; when 6=>output<="10111111"; when 7=>output<="01111111"; end case;
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library ieee; use ieee.std_logic_1164.all;
entity decoder is PORT(input:IN std_logic_vector(2 downto 0);
54
library ieee; use ieee.std_logic_1164.all;
entity decoder_38 is PORT(input:IN std_logic_vector(2 downto 0);
output:OUT std_logic_vector(7 downto 0)); end;
entity dff1 is port(clk,d:in std_logic; q:out std_logic);
end;
architecture rtl of dff1 is begin
process(clk) begin
if(clk'event and clk='1')then q<=d;
end if; end process; end rtl;
end process; end rtl1;
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library ieee; use ieee.std_logic_1164.all;
entity ym3_8 is port(a:in std_logic_vector(2 downto 0); y:out std_logic_vector(7 downto 0));
38
39
选器件
40
点击下一步
41
点击New
44
45
46
47
48
49
50
后面的操作同前
51
作业：用VHDL语言： 1、设计一个3线－8线译码器； 2、设计一个上升沿触发JK触发器。
CLR
JQ
CLK
K
52
library ieee; use ieee.std_logic_1164.all;
22
23
双击Generate Schematic Symbol
24
25
点击器件ispLSI1032E-70LJ84
26
双击Fit Design
27
28
29
30
下载
31
32
33
34
35
36
（八）ISPLEVER 软件的使用方法
2、VHDL的原理图方式设计
37
点击File —>New Project
9
选VHDL Module
10
填入文件名、实体名（两者要一致）和
结构体名
11
点
OK
12
13
输入程序
14
保存
15
退出
16
17
点击dff1(dff1.vhd)
18
源程序编写完成以后是综合 双击Synplify Synthesize VHDL File
19
20
21
双击VHDL Test Bench Template
end ym3_8;
architecture rtl of ym3_8 is begin process(a)
case a is when "000"=>y<="11111110"; when "001"=>y<="11111101"; when "010"=>y<="11111011"; when "011"=>y<="11110111"; when "100"=>y<="11101111"; when "101"=>y<="11011111"; when "110"=>y<="10111111"; when others=>y<="01111111";
architecture rtl1 of decoder is begin
process(input) case input is when "000"=>yout<="11111110"; when "001"=>yout<="11111101"; when "010"=>yout<="11111011"; when "011"=>yout<="11110111"; when "100"=>yout<="11101111"; when "101"=>yout<="11011111"; when "110"=>yout<="10111111"; when "111"=>yout<="01111111"; end case;
ISPLEVER 软件的使用方法
1、VHDL的文本方式设计
1
点击程序－>Lattice Semiconductor—> ispLEVER Project Navigator
2
点击File —>New Project
3
输入项目名，选VHDL，点下一步
4
选器件
5
点击下一步
6
点击完成
7
8
点击Source —New
53
library ieee; use ieee.std_logic_1164.all;
entity and_gate is PORT(A,B:IN std_logic;X:OUT
std_logic); end;
architecture rtl of and_gate is begin X<=A AND B; end rtl;
end process; end rtl1;
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library ieee; use ieee.std_logic_1164.all;
entity decoder is PORT(input:IN std_logic_vector(2 downto 0);
yout:OUT std_logic_vector(7 downto 0)); end;
output:OUT std_logic_vector(7 downto 0)); end;
architecture rtl1 of decoder is begin
process(input) case input is when 0=>output<="11111110"; when 1=>output<="11111101"; when 2=>output<="11111011"; when 3=>output<="11110111"; when 4=>output<="11101111"; when 5=>output<="11011111"; when 6=>output<="10111111"; when 7=>output<="01111111"; end case;