集成电路设计-05-反相器动静态特性

Transfer curve shows static input/output relationship—hold input voltage, measure output voltage.
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反相器噪声容限的三种求法

求法1

Voh
Voh,min

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Simulated VTC
2.5
2
1.5
out
V
(V)
1 0.5 0 0
0.5
1
1.5
2
2.5
V (V)
in
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Impact of Process Variations
2.5 2
Good PMOS Bad NMOS Nominal
1.5
Vout(V)
1 0.5 0 0
Good NMOS Bad PMOS
0.5
1
1.5
2
2.5
Vin (V)
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5-4 传输延迟（Propagation Delay）
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Delay

Assume ideal input (step), RC load.
V DD V DD
Rp
V out Rn
V out
VOL = 0 VOH = VDD VM = f(Rn, Rp)
V in = V DD
V in = 0
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CMOS Inverter: Transient Response
V DD Rp V DD
tpHL = f(R on.CL) = 0.69 RonCL
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上升时间（rise time）, pullup on; 下降时间（fall time）, pullup off.
V DD Rp V DD
tpHL = f(R on.CL) = 0.69 RonCL
V out CL Rn V out
CL
(a) Low-to-high
2.5 2
0.25um, (W/L)p/(W/L)n = 3.4 (W/L)n = 1.5 (min size) VDD = 2.5V VM 1.25V, g = -27.5
Vout (V)
1.5 1
0.5 0 0 0.5 1 1.5 2 2.5
VIL = 1.2V, VIH = 1.3V NML = NMH = 1.2 (actual values are VIL = 1.03V, VIH = 1.45V NML = 1.03V & NMH = 1.05V)
I Dn
V
out
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PMOS Load Lines
I Dp I Dn I Dn V =0 in V =1.5 in
V =0 in V =1.5 in
V =-1 GSp V =-2.5 GSp
V DSp
V DSp
V out
V = V +V in DD GSp I =-I Dn Dp
最低输出高电平、最高 输出低电平； 找到对应的输入； 求差；
VNL=Voff – Vil
VNH=Vih – Von
Vol,max Vol Vil Voff Von
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Vih
19

求法2

Voh
Voh,min

单位增益点（斜率为1， -1）； 找到对应的输入； 求差；
All polarities of all voltages and currents are reversed
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PMOS Load Lines
V in
V DD
V out
C L
V = V +V in DD GSp I =-I Dn Dp V = V +V out DD DSp
(b) High-to-low
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Current through transistor


Transistor starts in saturation region, then moves to linear region. Vout增大

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I-V Plot (PMOS)
-2
VDS (V)
-1
0 0
VGS = -1.0V VGS = -1.5V VGS = -2.0V
-0.2 -0.4 -0.6 -0.8
VGS = -2.5V
-1 X 10-4
PMOS transistor, 0.25um, Ld = 0.25um, W/L = 1.5, VDD = 2.5V, VT = -0.4V
9
I-V NMOS
2.5
X 10-4
VGS = 2.5V
2 1.5 1 0.5 0 0 0.5 1 1.5 2 2.5
VGS = 2.0V
VGS = 1.5V
VGS = 1.0V
VDS (V)
NMOS transistor, 0.25um, Ld = 0.25um, W/L = 1.5, VDD = 2.5V, VT = 0.4V
V = V +V out DD DSp
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CMOS Inverter Load Characteristics
ID n Vin = 0 Vin = 2.5
PMOS
Vin = 0.5
Vin = 2
NMOS
Vin = 1 Vin = 1.5 Vin = 2 Vin = 2.5 Vin = 1.5

低输出阻抗 对噪声和干扰不敏感

极高的输入阻抗（input resistance） 稳态下 Vdd 和 GND 间无直流通路

无静态功耗
是负载电容和晶体管电阻的函数。

传输延迟（Propagation delay）

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CMOS Inverter ——First-Order DC Analysis
3
VOH = VDD
By definition, VIH and VIL are where dVout/dVin = -1 (= gain) NMH = VDD - VIH NML = VIL - GND
VM
ቤተ መጻሕፍቲ ባይዱ
2
1
Approximating: VIH = VM - VM /g VIL = VM + (VDD - VM )/g
1
1.5
2
2.5
NMOS res PMOS off 2.5 Vin
0.5
0.5
1
1.5
2
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噪声容限



反映了对噪声的敏 感程度； 电路0，1电平允许 的输入范围； 越大越好；

VDD
logic 1 VH unknown VL
高电平噪声容限 低电平噪声容限
VSS
logic 0
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Logic level matching

Levels at output of one gate must be sufficient to drive next gate.
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Transfer characteristics
VIL
VOL = GND0
Vin VIH A piece-wise linear approximation of VTC
So high gain in the transition region is very desirable
22
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CMOS Inverter VTC from Simulation
Rn≈1/[βn (Vgs – Vt)]
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Gain Determinates
Vin
0 0 -2 -4 -6 -8 -10 -12 -14 -16 -18 0.5 1 1.5 2
Gain is a strong function of the slopes of the currents in the saturation region, for Vin = VM
4
Two Inverters
Share power and ground
VDD
Connect in Metal
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CMOS 反相器基本特点

输出


电源和GND 噪声容限大

逻辑电平与尺寸无关，可以采用最小尺寸 稳态输出时，VDD或GND与输出之间总存在有限电阻的通路
Output resistance low-output = 2.4k high-output = 3.3k
Vin (V)
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VM与PMOS及NMOS的宽长比
1.5 1.4 1.3 1.2 1.1 1 0.9 0.8 0.1 1
~3.4
Increasing
(1+r) g ---------------------------------(VM-VTn-VDSATn/2)(ln - lp ) Determined by technology parameters, especially channel length modulation (l). Only designer influence through supply voltage and VM (transistor sizing).

完整性和稳定性


性能


能量效率

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5-2 反相器（Inverter）
CMOS Inverter
VDD
N Well VDD 2l PMOS
Contacts
Vin
Vout
In
Out Metal 1
CL
Polysilicon
NMOS GND
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Vin = 1.5 Vin = 1 Vin = 1 Vin = 0.5 Vin = 0 Vout
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CMOS Inverter VTC
Vout NMOS off PMOS res NMOS s at PMOS res NMOS sat PMOS sat NMOS res PMOS sat
V out CL Rn V out
CL
V in = 0 (a) Low-to-high
V in = V DD (b) High-to-low
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5-3 Voltage Transfer Characteristic

NMOS+PMOS 图解法
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the width of the PMOS moves VM towards VDD
Increasing the width of the NMOS moves VM toward GND
决定因素：宽长比
10
近似为等效电阻之比。
(W/L)p/(W/L)n 工艺因子： k’ = µ Cox 导电因子： βn = k’（W/L）
集成电路设计
第五章 CMOS反相器
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Outline



电路特性 反相器 CMOS反相器电压传输特性 噪声容限 传输延迟 驱动大电容负载

功耗及低功耗设计
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5-1 特性

成本

复杂性和面积
静态（稳态）特性 动态（瞬态）特性 能耗和功率
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Gain as a function of VDD
2.5
0.2
2
0.15
(V)
(V) V
out
1.5
V
out
0.1
1
0.05
0.5
Gain=-1
0 0 0.5 1 V (V)
in
1.5
2
2.5
0 0
0.05
0.1 V (V)
in
0.15
0.2


100mv时，VTC变差； 过渡区增益接近-1 一般，为达到足够的增益，电源应大于热电势的两倍 VDDmin > 2, 4 KT/q KT/q室温下约为26mv
VNL=Voff – Vil
VNH=Vih – Von
Vol Vil Voff Von
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Vol,max
Vih
20

求法3

工作中心点；

Vin = Vout Vgs = Vds

找到对应的输入； 求差；
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Noise Margins Determining VIH and VIL