十进制加法计数器程序
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[例5.6.1] 十进制计数器的VHDL描述（sw向上是0(on)；灯亮为0 ）LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity count10 is
PORT (cp,r:IN S TD_LOGIC;
q:OUT STD_LOGIC_VECTOR(3 DOWNTO 0) );
end count10;
ARCHITECTURE Behavioral OF count10 IS
SIGNAL count:STD_LOGIC_VECTOR(3 DOWNTO 0) ;
BEGIN
PROCESS (cp,r)
BEGIN
if r='0' then count<="0000";
elsiF cp'EVENT AND cp='1' THEN
if count="1001" THEN
count <="0000";
ELSE count <= count +1;
END IF;
end if;
END PROCESS;
q<= count;
end Behavioral;
[例5.6.1] 十进制计数器的VHDL描述（sw向上是1；灯亮为1）library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity count10 is
PORT (cp,r:IN S TD_LOGIC;
q:OUT STD_LOGIC_VECTOR(3 DOWNTO 0) );
end count10;
ARCHITECTURE Behavioral OF count10 IS
SIGNAL count:STD_LOGIC_VECTOR(3 DOWNTO 0) ;
BEGIN
PROCESS (cp,r)
BEGIN
if r='1' then count<="0000";
elsiF cp'EVENT AND cp='1' THEN
if count="1001" THEN
count <="0000";
ELSE count <= count +1;
END IF;
end if;
END PROCESS;
q<=not count;
end Behavioral;