锁相技术译文翻译

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锁相技术译文翻译

英文原文:

An On-Chip All-Digital Measurement Circuit to Characterize Phase-Locked Loop Response in 45-nm SOI

译文:45纳米SOI全数字片上测量电路表征锁相环响应特性年级专业:

姓名:学号:

2013 年 6 月 2 日

英文中文

An On-Chip All-Digital Measurement

Circuit to Characterize Phase-Locked

Loop Response in 45-nm SOI

Abstract—An all-digital measurement Circuit , built in 45-nm SOI-CMOS enabl

es on-chip characterization of phase-loc

ked loop (PLL) response to a self-induce

d phas

e step.

This technique allows estimation

of PLL closed-loop bandwidth and jitter

peaking. The circuit can

be used to plot step-response vs.time, measure static phase error,

and observe phase-lock status. INTRODUCTION

Many applications such as PCI Express? require a PLL to produce alow-jitter clo

ck at a given frequency while meeting s tringent bandwidth and jitter peaking r 45纳米SOI全数字片上测量电路表征锁相

环响应特性

摘要---建立在45纳米的SOI-CMOS上一个全数字测量电路,它能够表征PLL对自诱导相步进的响应

这项技术允许对PLL闭环带宽和抖动峰值的估计。这个电路被用来绘制阶跃响应随时间

变化的曲线,测量静态相位误差和观察相位

锁定状态。

介绍

很多应用例如PCI Express?需要一个PLL来产生一个低抖动的在一个给定频率的时钟,

这个频率满足精确带宽和抖动峰值的要求。

equirements. Process, voltage, and tem perature (PVT) variations as well as rand om device mismatch make it difficult to

guarantee a narrow range for PLL resp onse. For example ,loop parameters suc h as VCO gain

could vary by more than 2X over

PVT corners. In Fig. 1, we see the closed

-loop jitter transfer functions of two PLL

s with identical reference clock and out

put frequencies. One PLL exhibits large

peaking and low bandwidth while the

other shows little peaking but high ban dwidth. Although differences in this exa mple are more extreme than usual, simil

ar but smaller differences often result fr

om PVT variations.

PLL response is often measured on a

test bench using signal generators, osci lloscopes, and/or spectrum analyzers.

For example, the transfer functions in Fi 工艺,电压,和温度(PVT)变化以及随机的选择不搭配的器件都使得很难保证一个窄

的变化范围的PLL响应,例如,

环路参数如VCO增益变化可能超过PVT角2倍上以。

图一中,我们可以看到两个具有相同参考时

钟和输出频率PLL的闭环抖动传递函数

一个PLL展现大的峰值和低带宽,而另一个

展示了小峰值但是高带宽

虽然这个例子中显示的差异比通常的要极

端,这种相似会随着PVT的变化而变小

PLL的响应往往使用一个信号发生器、示波器,和/或频谱分析仪。

g. 1 were automatically generated by m

odulating the 100-MHz reference clock with various frequencies while observin g the amplitudes of the resulting outpu

t spurs. Such methods, which may requi re many seconds to complete, motivate the need for faster, less expensive, and preferably on-chip techniques to charac terize PLL response [1]-[3]. Fig. 2 shows the PLL output phase transient respons e to an induced phase step. Similar to other second-order feedback systems, t he PLL tends to overcorrect (or oversho ot) as it works to eliminate the induced phase error. If the PLL is underdamped, as in this example, the PLL may ring sev eral times before settlingto its final lock state. A key metric in the PLL step-resp onse is crossover, defined here as the elapsed time from input step toonset of phase overshoot. Another key metric is MaxOvershoot. It 例如,在图一中传递函数是通过调制100MHz能产生各种频率的参考时钟

同时观察输出马刺产生的幅值自动生成的。

这种方法,可能需要一些时间去完成,这促

进了更快,更便宜的方法的需要。

比较好的方法是片上系统来表征PLL的响应特性[1]-[3]。

表二表明致相步进响应的输出瞬态相位。

类似于其他二阶反馈系统,PLL倾向于过调(或过调),那是因为它是为了消除相位误差。

如果锁相环工作在欠阻尼状态,在这种状态

下,PLL可能要经过几次锁存在达到最终锁

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