闹钟代码

--译码器可将KEYPAD信号转换为0~9的整型数，以直观地表示和处理用户输入的数字。

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity decoder is
Port ( keypad : in STD_LOGIC_VECTOR (9 downto 0);
value : out STD_LOGIC_VECTOR (3 downto 0));
end decoder;
architecture Behavioral of decoder is
begin
WITH keypad SELECT
value<= "0000" WHEN "0000000001",
"0001" WHEN "0000000010",
"0010" WHEN "0000000100",
"0011" WHEN "0000001000",
"0100" WHEN "0000010000",
"0101" WHEN "0000100000",
"0110" WHEN "0001000000",
"0111" WHEN "0010000000",
"1000" WHEN "010*******",
"1001" WHEN "1000000000",
"0000" WHEN OTHERS;
end Behavioral;
--分频器将较高速的外部时钟频率分频成每分钟一次的时钟频率，以便进行时钟计数。

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entityfq_divider is
Port ( clk_in : in STD_LOGIC;
reset : in STD_LOGIC;
clk_out : out STD_LOGIC);
endfq_divider;
architecture Behavioral of fq_divider is
signaltemp:std_logic_vector(5 downto 0);
begin
process(reset,clk_in)
begin
if reset='1' then
temp<="000000";
clk_out<='0';
elsifrising_edge(clk_in)then
if(temp="111011") then
temp<="000000";
clk_out<='1';
else
temp<=temp+1;
clk_out<='0';
end if;
end if;
end process;
end Behavioral;
--键盘缓冲器是一个移位寄存器，暂存用户键入的数字，
-------------并且实现用户键入数字在显示器上从右到左的依次显示。

-------------这里需要注意的是，由图6.23可以看出，KEY_BUFFER的时钟端连接的是外部KEY_DOWN 信号。

-------------这表示用户每输入一个数字，KEY_BUFFER移位一次。

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entitykey_buffer is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
key : in STD_LOGIC_VECTOR (3 downto 0);
new_time1 : out STD_LOGIC_VECTOR (3 downto 0);
new_time2 : out STD_LOGIC_VECTOR (3 downto 0);
new_time3 : out STD_LOGIC_VECTOR (3 downto 0);
new_time4 : out STD_LOGIC_VECTOR (3 downto 0));
endkey_buffer;
architecture Behavioral of key_buffer is
signalreg : STD_LOGIC_VECTOR(15 downto 0):="0000000000000000";
begin
PROCESS(clk,reset)
BEGIN
if reset='1' then
reg<="0000000000000000";
elsIFrising_edge(clk) THEN
reg<= reg(11 downto 0)& key;
END IF;
END PROCESS ;
new_time1<= reg(15 downto 12);
new_time2<= reg(11 downto 8);
new_time3<= reg(7 downto 4);
new_time4<= reg(3 downto 0);
end Behavioral;
--计数器实际上是一个异步复位、异步置数的累加器，
---------通常情况下进行时钟累加计数，必要时可置入新的时钟值，然后从该值开始新的计数。

----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entityalarm_counter is
Port ( load_new_c : in STD_LOGIC;
reset : in STD_LOGIC;
clk : in STD_LOGIC;
new_current_time1 : in STD_LOGIC_VECTOR (3 downto 0);
new_current_time2 : in STD_LOGIC_VECTOR (3 downto 0);
new_current_time3 : in STD_LOGIC_VECTOR (3 downto 0);
new_current_time4 : in STD_LOGIC_VECTOR (3 downto 0);
new_time1 : out STD_LOGIC_VECTOR (3 downto 0);
new_time2 : out STD_LOGIC_VECTOR (3 downto 0);
new_time3 : out STD_LOGIC_VECTOR (3 downto 0);
new_time4 : out STD_LOGIC_VECTOR (3 downto 0)); endalarm_counter;
architecture Behavioral of alarm_counter is
signal temp1,temp2,temp3,temp4:std_logic_vector(3 downto 0):="0000";
begin
process(reset,clk,load_new_c)
begin
if reset='1' then
temp1<="0000";
temp2<="0000";
temp3<="0000";
temp4<="0000";
--new_time1<="0000";
--new_time2<="0000";
--new_time3<="0000";
--new_time4<="0000";
elsifload_new_c='1' then
temp1<=new_current_time1;
temp2<=new_current_time2;
temp3<=new_current_time3;
temp4<=new_current_time4;
elsifrising_edge(clk) then
if temp4="1001" then
temp4<="0000";
if temp3="0101" then
temp3<="0000";
if (temp1="0010")and (temp2="0011")then
temp1<="0000";
temp2<="0000";
elsif (temp1<="0010")and (temp2="1001")then
temp2<="0000";
temp1<=temp1+1;
else
temp2<=temp2+1;
end if;
else
temp3<=temp3+1;
end if;
else
temp4<=temp4+1;
end if;
end if;
end process;
new_time1 <=temp1;
new_time2 <=temp2;
new_time3 <=temp3;
new_time4 <=temp4;
end Behavioral;
--寄存器用于保存用户设置的闹钟时间，是一个异步复位寄存器。

----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entityalarm_reg is
Port ( clk : in STD_LOGIC;
load_new_a : in STD_LOGIC;
reset : in STD_LOGIC;
new_alarm_time1 : in STD_LOGIC_VECTOR (3 downto 0);
new_alarm_time2 : in STD_LOGIC_VECTOR (3 downto 0);
new_alarm_time3 : in STD_LOGIC_VECTOR (3 downto 0);
new_alarm_time4 : in STD_LOGIC_VECTOR (3 downto 0);
alarm_time1 : out STD_LOGIC_VECTOR (3 downto 0);
alarm_time2 : out STD_LOGIC_VECTOR (3 downto 0);
alarm_time3 : out STD_LOGIC_VECTOR (3 downto 0);
alarm_time4 : out STD_LOGIC_VECTOR (3 downto 0)); endalarm_reg;
architecture Behavioral of alarm_reg is
begin
process(reset,clk)
begin
if reset='1' then
alarm_time1<="0000";
alarm_time2<="0000";
alarm_time3<="0000";
alarm_time4<="0000";
elsifrising_edge(clk) then
ifload_new_a='1' then
alarm_time1<= new_alarm_time1;
alarm_time2<= new_alarm_time2;
alarm_time3<= new_alarm_time3;
alarm_time4<= new_alarm_time4;
end if;
end if;
end process;
end Behavioral;
--显示器根据需要显示当前时间、用户设置的闹钟时间或用户通过键盘输入的新的时间，---------同时判断当前时间是否已到了闹钟时间，实际上是一个多路选择器加比较器。

----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entitydisplay_driver is
Port ( show_new_time : in STD_LOGIC;
show_a : in STD_LOGIC;
new_time1 : in STD_LOGIC_VECTOR (3 downto 0);
new_time2 : in STD_LOGIC_VECTOR (3 downto 0);
new_time3 : in STD_LOGIC_VECTOR (3 downto 0);
new_time4 : in STD_LOGIC_VECTOR (3 downto 0);
current_time1 : in STD_LOGIC_VECTOR (3 downto 0);
current_time2 : in STD_LOGIC_VECTOR (3 downto 0);
current_time3 : in STD_LOGIC_VECTOR (3 downto 0);
current_time4 : in STD_LOGIC_VECTOR (3 downto 0);
alarm_time1:in STD_LOGIC_VECTOR (3 downto 0);
alarm_time2:in STD_LOGIC_VECTOR (3 downto 0);
alarm_time3:in STD_LOGIC_VECTOR (3 downto 0);
alarm_time4:in STD_LOGIC_VECTOR (3 downto 0);
display1:out STD_LOGIC_VECTOR (3 downto 0);
display2:out STD_LOGIC_VECTOR (3 downto 0);
display3:out STD_LOGIC_VECTOR (3 downto 0);
display4:out STD_LOGIC_VECTOR (3 downto 0);
sound_alarm :outstd_logic);
enddisplay_driver;
architecture Behavioral of display_driver is
begin
process(show_new_time,show_a,current_time1,current_time2,current_time3,current_time4) begin
if (current_time1=alarm_time1) and (current_time2=alarm_time2) and (current_time3=alarm_time3) and (current_time4=alarm_time4) then
sound_alarm<='1';
else
sound_alarm<='0';
end if;
end process;
process
(show_new_time,show_a,current_time1,current_time2,current_time3,current_time4,new_time 1,new_time2,new_time3,new_time4,alarm_time1,alarm_time2,alarm_time3,alarm_time4) begin
if(show_new_time='1')then
display1<=new_time1;
display2<=new_time2;
display3<=new_time3;
display4<=new_time4;
elsif (show_a='1')then
display1<=alarm_time1;
display2<=alarm_time2;
display3<=alarm_time3;
display4<=alarm_time4;
else
display1<=current_time1;
display2<=current_time2;
display3<=current_time3;
display4<=current_time4;
end if;
end process;
end Behavioral;
--控制器是设计的核心部分，按设计要求产生相应的控制逻辑，以控制其他各部分的工作。

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entityalarm_controller is
Port ( key : in STD_LOGIC;
clk : in STD_LOGIC;
reset : in STD_LOGIC;
time_button : in STD_LOGIC;
alarm_button : in STD_LOGIC;
load_new_c : out STD_LOGIC;
load_new_a : out STD_LOGIC;
show_new_time : out STD_LOGIC;
show_a : out STD_LOGIC);
endalarm_controller;
ARCHITECTURE ART OF ALARM_CONTROLLER IS
TYPE t_state IS (S0, S1, S2, S3,S4);
CONSTANT KEY_TIMEOUT :std_logic_vector := "11101";
SIGNAL CURR_STATE :t_state;
SIGNAL NEXT_STATE :t_state;
SIGNAL COUNTER :std_logic_vector(4 downto 0);
SIGNAL ENABLE_COUNT : STD_LOGIC;
SIGNAL COUNT_END : STD_LOGIC ;
BEGIN
PROCESS(CLK,RESET)
BEGIN
IF RESET ='1' THEN
CURR_STATE <= S0;
ELSE
IF rising_edge(clk) THEN
CURR_STATE <= NEXT_STATE;
END IF;
END IF;
END PROCESS;
PROCESS(KEY,ALARM_BUTTON,TIME_BUTTON,CURR_STATE,
COUNT_END)
BEGIN
NEXT_STATE <= CURR_STATE;
LOAD_NEW_A <= '0';
LOAD_NEW_C <= '0';
SHOW_A <= '0';
SHOW_NEW_TIME <= '0';
ENABLE_COUNT <= '0';
CASE CURR_STATE IS
WHEN S0 =>
IF (KEY = '1') THEN
NEXT_STATE <= S1;
SHOW_NEW_TIME <= '1';
ELSIF (ALARM_BUTTON = '1') THEN
NEXT_STATE <= S4;
SHOW_A <= '1';
ELSE
NEXT_STATE <= S0;
END IF;
WHEN S1 =>
IF (KEY = '1') THEN
NEXT_STATE <= S1;
ELSIF (ALARM_BUTTON = '1') THEN NEXT_STATE <= S2;
LOAD_NEW_A <= '1';
ELSIF (TIME_BUTTON = '1') THEN
NEXT_STATE <= S3;
LOAD_NEW_C <= '1';
ELSE
IF (COUNT_END = '1') THEN
NEXT_STATE <= S0;
ELSE
NEXT_STATE <= S1;
END IF;
ENABLE_COUNT <= '1';
END IF;
SHOW_NEW_TIME <= '1';
WHEN S2 =>
IF (ALARM_BUTTON = '1') THEN
NEXT_STATE <= S2;
LOAD_NEW_A <= '1';
ELSE
NEXT_STATE <= S0;
END IF;
WHEN S3 =>
IF (TIME_BUTTON = '1') THEN
NEXT_STATE <= S3;
LOAD_NEW_C <= '1';
ELSE
NEXT_STATE <= S0;
END IF;
WHEN S4 =>
IF (KEY = '1') THEN
NEXT_STATE <= S1;
ELSE
NEXT_STATE <= S4;
IF (COUNT_END = '1') THEN
NEXT_STATE <= S0;
ELSE
NEXT_STATE <= S4;
SHOW_A <= '1';
END IF;
ENABLE_COUNT <= '1';
END IF;
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS;
PROCESS(ENABLE_COUNT,CLK)
BEGIN
IF (ENABLE_COUNT = '0') THEN
COUNTER <= "00000";
COUNT_END <= '0';
ELSIF (RISING_EDGE(CLK)) THEN
IF (COUNTER >= KEY_TIMEOUT) THEN
COUNT_END <= '1';
ELSE
COUNTER <= COUNTER+ 1;
END IF;
END IF;
END PROCESS;
END ART;
-- 测试文件
-------------------------------------------------------------------------------- LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY clock_tb_vhd IS
END clock_tb_vhd;
ARCHITECTURE behavior OF clock_tb_vhd IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT clock
PORT(
keypad : IN std_logic_vector(9 downto 0);
key_down : IN std_logic;
clk : IN std_logic;
reset : IN std_logic;
time_button : IN std_logic;
alarm_button : IN std_logic;
sound_alarm : OUT std_logic;
display1 : OUT std_logic_vector(3 downto 0);
display2 : OUT std_logic_vector(3 downto 0);
display3 : OUT std_logic_vector(3 downto 0);
display4 : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
--Inputs
SIGNAL key_down :std_logic := '0';
SIGNAL clk :std_logic := '0';
SIGNAL reset :std_logic := '0';
SIGNAL time_button :std_logic := '0';
SIGNAL alarm_button :std_logic := '0';
SIGNAL keypad :std_logic_vector(9 downto 0) := (others=>'0');
--Outputs
SIGNAL sound_alarm :std_logic;
SIGNAL display1 :std_logic_vector(3 downto 0);
SIGNAL display2 :std_logic_vector(3 downto 0);
SIGNAL display3 :std_logic_vector(3 downto 0);
SIGNAL display4 :std_logic_vector(3 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: clock PORT MAP(
keypad => keypad,
key_down =>key_down,
clk =>clk,
reset => reset,
time_button =>time_button,
alarm_button =>alarm_button,
sound_alarm =>sound_alarm,
display1 => display1,
display2 => display2,
display3 => display3,
display4 => display4
);
clk<=not clk after 20 ns;
tb : PROCESS
BEGIN
reset<='1';
wait for 80 ns;
reset<='0';
wait for 3000 ns;
keypad<="0000000010";
wait for 20 ns;
key_down<='1';
wait for 40 ns;
key_down<='0';
wait for 20 ns;
keypad<="0000000100";
wait for 20 ns;
key_down<='1';
wait for 40 ns;
key_down<='0';
wait for 20 ns;
keypad<="0000001000";
wait for 20 ns;
key_down<='1';
wait for 40 ns;
key_down<='0';
wait for 20 ns;
keypad<="0000000010";
wait for 20 ns;
key_down<='1';
wait for 40 ns;
key_down<='0';
wait for 40 ns;
time_button<='1';
wait for 60 ns;
time_button<='0';
wait for 200 ns;
keypad<="0000000010";
wait for 20 ns;
key_down<='1';
wait for 40 ns;
key_down<='0';
wait for 20 ns;
keypad<="0000000100";
wait for 20 ns;
key_down<='1';
wait for 40 ns;
key_down<='0';
wait for 20 ns;
keypad<="0000001000";
wait for 20 ns;
key_down<='1';
wait for 40 ns;
key_down<='0';
wait for 20 ns;
keypad<="0000001000";
wait for 20 ns;
key_down<='1';
wait for 40 ns;
key_down<='0';
wait for 40 ns;
alarm_button<='1';
wait for 60 ns;
alarm_button<='0';
wait; -- will wait forever END PROCESS;
END;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY AND_OR_TB_vhd IS
END AND_OR_TB_vhd;
ARCHITECTURE behavior OF AND_OR_TB_vhd IS
COMPONENT AND_OR
PORT(
INP : IN std_logic_vector(3 downto 0);
Z : OUT std_logic
);
END COMPONENT;
--Inputs
SIGNAL INP :std_logic_vector(3 downto 0) := (others=>'0');
--Outputs
SIGNAL Z :std_logic;
signal A_STIM,B_STIM:STD_LOGIC_VECTOR(1 downto 0);
BEGIN
INP<=A_STIM&B_STIM;
-- Instantiate the Unit Under Test (UUT)
uut: AND_OR PORT MAP(
INP => INP,
Z => Z
);
A_STIM<="00","01" after 50 ns,"10" after 100 ns,"11"after 150 ns; TB: PROCESS
BEGIN
B_STIM<="11";
-- Wait 100 ns for global reset to finish
wait for 50 ns;
B_STIM<="10";
-- Place stimulus here
wait for 50 ns;
B_STIM<="01";
wait for 50 ns;
B_STIM<="00";
wait; -- will wait forever
END PROCESS;
END;。