FPGAVHDL硬件描述语言基础PPT课件
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q : out bit); end test1; architecture test1_body of test1 is begin process (clk, d, reset) begin
if (reset = ‘1’) then q <= ‘0’;
elsif (clk = ‘1’) then q <= d;
More Detail
process (clk, d, reset)
– this say that the OUTPUT change when either clk, d or reset change, if clk, d or reset not change, then maintain the output
Result
Configure the Altera Device and do on board debugging,
prototyping or production
Copyright © 1997 Altera Corporation
3
2020/7/312020/7/31 P.3
What do you expect from VHDL?
Copyright © 1997 Altera Corporation
11
2020/7/312020/7/31 P.11
Why I have a Flip-Flop not a Latch
Latch with a Sensitivity list
process (clk, d, reset)
Flip-Flop with a Sensitivity list
Copyright © 1997 Altera Corporation
2
VHDL Design Flow - VSAR
VHDL
Entry
Synthesis
Architecture Synthesis
Use any Text Editor to input your design
Use any VHDL Compiler to convert your language design to Gate level with optimization in term of Speed/Area To map the logic to Altera Device Architecture e.g. LUT, Carry/Cascade Chain, EAB......(further logic optimization)
Within the process excute in step-by-step
8
This is a LATCH
Copyright © 1997 Altera Corporation
9
2020/7/312020/7/31 P.9
Entity test1 is
port (clk, d , reset : in bit;
VHDL Coding Style Target at
Performance/Delay/LC Usage
Copyright © 1997 Altera Corporation
1
2020/7/312020/7/31 P.1
整体 概述
一 请在这里输入您的主要叙述内容
二
请在这里输入您的主要 叙述内容
三 请在这里输入您的主要叙述内容
end if; end process; end test1_body;
Reset take over the control first
Clk take the control second
Copyright © 1997 Altera Corporation
2020/7/312020/7/31 P.8
– what kind of device will provide this function ?
LATCH
Copyright © 1997 Altera Corporation
13
2020/7/312020/7/31 P.13
process (clk)
– this say that OUTPUT change when CLK change, if clk does not change, maintain the output
q : out bit);
end test1;
architecture test1_body of test1 is
begin
process (clk)
begin
if (reset = ‘1’) then
q <= ‘0’;
elsif (clk=‘1’) then
q <= d;
d is not included in sensitivity list
Copyright © 1997 Altera Corporation
5
2020/7/312020/7/31 P.5
Use the Suitable Coding Style
Different coding style has different performance
OR
Copyright © 19Байду номын сангаас7 Altera Corporation
6
2020/7/312020/7/31 P.6
Issue 1
Latch or Flipflop
Copyright © 1997 Altera Corporation
7
2020/7/312020/7/31 P.7
How to do the Latch
Entity test1 is port (clk, d , reset : in bit;
end if; end process;
it’s change will not change the output
end test1_body;
Copyright © 1997 Altera Corporation
10
2020/7/312020/7/31 P.10
I get a Flip-Flop not a LATCH
process(clk)
Q : What is the Sensitivity list use for ? A : The OUTPUT change when the Sensitivity list
change
Copyright © 1997 Altera Corporation
12
2020/7/312020/7/31 P.12
if (reset = ‘1’) then q <= ‘0’;
elsif (clk = ‘1’) then q <= d;
More Detail
process (clk, d, reset)
– this say that the OUTPUT change when either clk, d or reset change, if clk, d or reset not change, then maintain the output
Result
Configure the Altera Device and do on board debugging,
prototyping or production
Copyright © 1997 Altera Corporation
3
2020/7/312020/7/31 P.3
What do you expect from VHDL?
Copyright © 1997 Altera Corporation
11
2020/7/312020/7/31 P.11
Why I have a Flip-Flop not a Latch
Latch with a Sensitivity list
process (clk, d, reset)
Flip-Flop with a Sensitivity list
Copyright © 1997 Altera Corporation
2
VHDL Design Flow - VSAR
VHDL
Entry
Synthesis
Architecture Synthesis
Use any Text Editor to input your design
Use any VHDL Compiler to convert your language design to Gate level with optimization in term of Speed/Area To map the logic to Altera Device Architecture e.g. LUT, Carry/Cascade Chain, EAB......(further logic optimization)
Within the process excute in step-by-step
8
This is a LATCH
Copyright © 1997 Altera Corporation
9
2020/7/312020/7/31 P.9
Entity test1 is
port (clk, d , reset : in bit;
VHDL Coding Style Target at
Performance/Delay/LC Usage
Copyright © 1997 Altera Corporation
1
2020/7/312020/7/31 P.1
整体 概述
一 请在这里输入您的主要叙述内容
二
请在这里输入您的主要 叙述内容
三 请在这里输入您的主要叙述内容
end if; end process; end test1_body;
Reset take over the control first
Clk take the control second
Copyright © 1997 Altera Corporation
2020/7/312020/7/31 P.8
– what kind of device will provide this function ?
LATCH
Copyright © 1997 Altera Corporation
13
2020/7/312020/7/31 P.13
process (clk)
– this say that OUTPUT change when CLK change, if clk does not change, maintain the output
q : out bit);
end test1;
architecture test1_body of test1 is
begin
process (clk)
begin
if (reset = ‘1’) then
q <= ‘0’;
elsif (clk=‘1’) then
q <= d;
d is not included in sensitivity list
Copyright © 1997 Altera Corporation
5
2020/7/312020/7/31 P.5
Use the Suitable Coding Style
Different coding style has different performance
OR
Copyright © 19Байду номын сангаас7 Altera Corporation
6
2020/7/312020/7/31 P.6
Issue 1
Latch or Flipflop
Copyright © 1997 Altera Corporation
7
2020/7/312020/7/31 P.7
How to do the Latch
Entity test1 is port (clk, d , reset : in bit;
end if; end process;
it’s change will not change the output
end test1_body;
Copyright © 1997 Altera Corporation
10
2020/7/312020/7/31 P.10
I get a Flip-Flop not a LATCH
process(clk)
Q : What is the Sensitivity list use for ? A : The OUTPUT change when the Sensitivity list
change
Copyright © 1997 Altera Corporation
12
2020/7/312020/7/31 P.12