伪随机数产生器

伪随机数产生器

-----------------------------------------------------------------------------

--

-- The following information has been generated by Exemplar Logic and -- may be freely distributed and modified.

--

-- Design name : pseudorandom

--

-- Purpose : This design is a pseudorandom number generator. This design

-- will generate an 8-bit random number using the polynomial p(x) = x + 1.

-- This system has a seed generator and will generate 2**8 - 1 unique -- vectors in pseudorandom order. These vectors are stored in a ram which

-- samples the random number every 32 clock cycles. This variance of a

-- priority encoded seed plus a fixed sampling frequency provides a

truely

-- random number.

--

-- This design used VHDL-1993 methods for coding VHDL. --

----------------------------------------------------------------------------

Library IEEE ;

use IEEE.std_logic_1164.all ;

use IEEE.std_logic_arith.all ;

entity divide_by_n is

generic (data_width : natural := 8 );

port (

data_in : in UNSIGNED(data_width - 1 downto 0) ;

load : in std_logic ;

clk : in std_logic ;

reset : in std_logic ;

divide : out std_logic

);

end divide_by_n ;

architecture rtl of divide_by_n is

signal count_reg : UNSIGNED(data_width - 1 downto 0) ;

constant max_count : UNSIGNED(data_width - 1 downto 0) := (others => '1') ;

begin

cont_it : process(clk,reset)

begin

if (reset = '1') then

count_reg <= (others => '0') ;

elsif (clk = '1' and clk'event) then

if (load = '1') then

count_reg <= data_in ;

else

count_reg <= count_reg + "01" ;

end if ;

end if;

end process ;

divide <= '1' when count_reg = max_count else '0' ;

end RTL ;

Library IEEE ;

use IEEE.std_logic_1164.all ;

use IEEE.std_logic_arith.all ;

entity dlatrg is

generic (data_width : natural := 16 );

port (

data_in : in UNSIGNED(data_width - 1 downto 0) ;

clk : in std_logic ;

reset : in std_logic ;

data_out : out UNSIGNED(data_width - 1 downto 0)

);

end dlatrg ;

architecture rtl of dlatrg is

begin

latch_it : process(data_in,clk,reset)

begin

if (reset = '1') then

data_out <= (others => '0') ;

elsif (clk = '1') then

data_out <= data_in ;

end if;