数字电路设计 FPGA 讲义— number-representation
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NUMBER REPRESENTATION
Why we study number representation
•To meet design metrics minimum number of bits that result in correct answer are required
•Additional bits will results in:
•Additional Hardware
•Increases power (Because of more switching of gates and wires)
•May increase latency
Fixed point integer •Unsigned (Non-negative integer)
•For n-bit number, range is given by
[0, 2n -1]
•Ex. 111
range [0, 7]
Fixed point integer
•Signed
•Sign magnitude
•For n-bit number, range is given by:
•Ex. 0 111 7 1 111
-7
•Signed 2’s complement
•For n-bit number, range is given by:
•Ex. 1 1 1 1
[-(2n-1 –1), 2n-1 -1]
Sign bit Sign bit
Magnitude
Magnitude
[-2n-1 , 2n-1 -1]
-8421
-1
Fixed point integer-Example for different types
Binary number Unsigned Sign magnitude Signed 2’s complement 111115-7-1
111014-6-2
100080-8
0111777
Fixed point fraction
•Fraction can be represented as follows
_ _ _ . _ _
n= i + f
Where n is total no. of bits
•Unsigned range
•
Signed (2’s complement) range
Integer Fraction
i f
[0, 2i –2-f ]
[-2i-1 , 2i-1 –2-f ]
Sign extension
•Needed for 2’s complement addition
•Consider case of adding two numbers of different widths
1 0 1 1 -5
0 1 0 0 1 0 +18
---------------
0 1 1 1 0 1 +29!
Sign extension Rules
•Rule #1: 2’s complement numbers must be the same word‐width because of implied zeros
0 0 1 0 1 1 -5
0 1 0 0 1 0 +18
---------------
0 1 1 1 0 1 +29! => Still Wrong
Sign extension
•Rule #2: Despite a fundamental change to the number’s definition, the value of a 2’s complement number will never change due to any amount of sign extension—positive or negative
1011 -5=-8+2+1
11011 -5=-16+8+2+1
111011 -5=-32+16+8+2+1
Sign extension
•Procedure:
•Calculate the width of the answer word so that it contains all input possibilities
•It’s up to you to make sure the output range is sufficient
•Extend the inputs’ sign bits to the width of the answer
•Add as usual
•Ignore bits that ripple to the left of the answer’s MSB
1 1 1 0 1 1 -5
0 1 0 0 1 0 +18
---------------
x 0 0 1 1 0 1 +13