低功耗高增益LNA设计

CG LNA consists in using an active boost circuit such that the boosting gain A>1.
III. DESIGN OF A COMMON GATE ACTIVE BOOST LNA
Although CCCT was detailed in 2000 [4], only few papers investigated the possibility of over-unity gm-boost gain. In [5] an n-turn on-chip transformer is proposed with a k-coupling factor between coils. This circuit offers a boost gain A=nk potentially higher than one, but consumes significant silicon area. More recently, [3] proposed a self biased active boost using a common source topology but not in an inductorless context.
A. Proposed Circuit.
Vdd
R3
M5A
Cc4
+ v3
RB M3A
Cc2
I3
I1
R1
R1
M5B
R3
Cc4
+ vOUT −diff −
M1A
M1B
− v3
RB M3B
Cc2
I1 I3
IREF
vIN +
I vIN − REF
Fig. 3. Schematic of the differential CG Active Boost LNA.
of capacitors does not increase PDC but limits the boosting gain to A=1. Another degree of freedom in the design of
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GIN = (gm1 )
Fig. 1. Inductorless LNAs, Resistive SFB (A1), Active SFB (A2) and CG (A3). Gain (Av) and input admittance (Gin) expressions are given.
Another option is the use of a source follower along with RF (Fig. 1-A2) [2], but the extra PDC required for gm2 limits the amplifier’s performance. CG circuits enable both higher gain and lower input impedance when gm1 increases (Fig. 1-A3), but input matching conditions force gm1 to be equal to 1/50Ω=20mS making CG circuit inappropriate for input matching at low PDC. For all these circuits, a high output impedance affects the gain bandwidth because of capacitive load. Therefore gain increase through a gm enhancement technique is preferable. Recently, several papers avoided the PDC-gm tradeoff in differential CG amplifiers (Fig. 2–B0) by applying a capacitive cross coupling technique (CCCT) depicted in Fig. 2-B1 [4]. It consists in AC coupling of the transistor gates thus doubling the AC amplifier current.
The CCCT can be seen as a gate voltage booster (Fig. 2–
B2) by enabling a gm-boost effect since the equivalent gm is doubled for constant biasing current. In Fig. 2–B1, the use
II. LNA INDUCTORLESS TECHNIQUES
Inductorless LNA circuits with 50 -input impedance are either based on shunt-feedback (SFB) structure or common gate (CG) topology [1]. The challenge in both CG and SFB circuits is to keep high voltage gain and good input matching with low power consumption. The SFB amplifier can be built with a pure resistive feedback (Fig. 1-A1), where the input admittance GIN is defined through the ratio of the voltage gain AV and the feedback resistance RF. RF does not consume power but degrades the output impedance and, thus, the gain capability when gm1 is small [1].
( ) GV −D = gm1RL
-A1
B2
V__II_NN_-_D
2
Z IN GV
=2
= (g
/ [(1+ ) m1RL
2
A)g m1 ] .(1+ A)
Fig. 2. B0- Differential CG amplifier B1-Differential CG amplifier with CCCT B2- Principle of gm-boost in CG circuit.
The proposed circuit is depicted in Fig.3. It is basically composed of a "main" amplifier (NMOS M1A-B, R1) and a so-called "gm-boost" amplifier (NMOS M3A-B, R3). This last also uses the CG topology for several reasons. First, CG circuits are known to be more linear [4]. Second, this auxiliary CG circuit helps in lowering the input impedance. Finally, CCCT is applied, with CC2, to interestingly "boost the gm-boost amplifier" without extra PDC. The output load of the gm-boost amplifier is defined by R3 and excessive voltage drop is avoided through the use current sources M5A-B. Their gates are connected in a middle point to avoid early gain cut-off due to parasitic active inductor. The gain bandwidth is enhanced with neutralization capacitors (CC4) that cancel the gate-todrain capacitance of M1 and creates a peaking effect on the gm-boost gain.
Rf= gf-1
RL
OUT
gm1
A1
IN
( ) Av = − gm1 − g f gL + g f
GIN = g f (1 − Av )
gm2
RL
OUT
Rf gm1
A2
IN
Av = − gm1RL
( ) GIN
=
gm2(1− Av)
1+ gm2Rf
RL
RBias
OUT
gm1
A3
IN
Av = − gm1RL
A 1.3mW 20dB Gain Low Power Inductorless LNA with
4dB Noise Figure for 2.45GHz ISM Band
François Belmas1, Frédéric Hameau1, Jean-Michel Fournier2 1. CEA LETI F38054 Grenoble FRANCE, 2. IMEP-LHAC, BP 257 38016 Grenoble.
RL
RL
VOUT-D
_
+
gm1
gm1
Байду номын сангаас
RL
RL
V _
OUT-D
+
gm1
gm1
RL OV__U_O_TU__T_-D_ 2
gm1
V__I_N_-_D _ 2+
B0
VIN-D
Z IN−D = 2 / gm1
( ) GV −D = gm1RL / 2
_ C1 C1 +
B1
VIN-D
Z IN−D = 1 / gm1
Index Terms — LNA, Low Power, inductorless, 2.4GHz, ISM
I. INTRODUCTION
Emerging wireless sensor network standards (WSN) like IEEE802.15.4 or Bluetooth Low Energy (BLE) address short-range ULP applications with increased battery lifetime. Typical applications, such as WPAN or BAN, promise mass market development with high volume production. At the same time, continuous CMOS technology downscaling increases the MOS transistor performance but also drastically increases the cost-perarea of all radio frequency integrated circuits (RFIC). In this context, a lot of effort is focused on inductorless designs in order to produce compact RFICs [1-3]. Focusing on the above mentioned standards, both the inductorless and ULP requirements cause new design challenges to be addressed with creative solutions. In this paper we propose a new differential ULP inductorless LNA dedicated to WSN applications. The LNA offers simultaneously strong reduction of the DC power consumption (PDC) while maintaining high gain along with reduced Noise Figure (NF). Part II lists the known inductorless LNA circuits and their limitations. In part III we show the theoretical analysis of the proposed circuit. Finally, part IV shows measurement results.
Abstract — This paper presents an inductorless low power (LP) low noise amplifier (LNA) based on a Common Gate (CG) topology. The circuit combines gain boosting techniques to enable high gain LP LNA. The circuit is integrated in a 130nm CMOS technology and shows 20dB gain with 4dB Noise Figure and -12dBm IIP3. The power consumption is 1.32mW from a 1.2V supply.