数字集成电路分析与设计 第一章答案
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CHAPTER 1
P1.1.To express each equation as sum-of-product and as a product-of-sum first write the truth table then create a Karnaugh map from the truth table. Then use the 1’s for sum-of products and 0’s for product of sums.
a.F CBA CBA CBA CBA
=+++
Collecting the terms together we find:
()()()
F AB AC BC A B A C B C
=++=+++
=+++
b.F DC A DCA DA C D CA
Collecting the terms together we find:
()()
=+=++
F D A DA A D A D
P1.2. There are many ways to do the circuit, here’s one version. First create a truth table.
The Boolean equation is: F
ABC ABC ABC ABC A B C =+++=⊕⊕. a. All NAND circuit (yours may be slightly different) is shown below:
A
b. All NOR circuit:
P1.3. There are many ways to do the circuits, here’s one version.
a. F AB BC =+
A
B C
b. F A B C =⊕⊕
See solution to P1.2 for guidance.
P1.4.
a. Implementing the truth table into K-Map form:
the resulting Boolean equations are:
Sum AB AB A B Carry AB
=+=⊕=
b. The associated gate equivalent will be:
A
B A
B
Figure P 1
P1.5. First, the full adder truth table:
a. Implementing the truth table into K-Map form:
OUT Sum ABC ABC ABC ABC A B C Carry AB AC BC
=+++=⊕⊕=++
b. The associated gate equivalent is straight-forward based on the previous problems.
P1.6.
a. F A BC ABC ABC =++
(
)()()()()()
F A BC ABC ABC A BC
ABC ABC A B C A B C A B C =++==++++++
b. F ABC A BC =+
(
)()
()()F ABC ABC ABC ABC A B C A B C =+==++++
P1.7. This question is as easy as it looks, no tricks here.
a. The delay from ‘a’ to ‘b’ is simply the delay of an inverter times the number of inverters which would be 10 ns.
b.
i. The period in this case is simply twice the delay around the loop, T=20 ns. ii. The frequency is 1/T =50 MHz.
P1.8. The delay of an RC circuit with a step input applied is:
() 1.2(1)t RC
V t e
-=-
In our case, we are solving for t : a. For V(t)=0.6V:
()31510
1.21
2.5(10)(100)10ln 12.510ln 2866s 0.6t p --⎛⎫=⨯== ⎪
⎝⎭
b. 1.2V:
t =∞
This circuit will never read 1.2V. c. The delay from 10% to 90% V DD :
10%0.1(1)
132t RC
e
t ps -=-∴=
90%0.9(1)
2.88t RC
e
t ns
-=-∴=
90%10% 2.880.132 2.75s t t t n =-=-=
P1.9. The delay for a and b uses the exponential rise/fall equation:
a. For R DOWN :
() 1.28.66t RC
DOWN V t e
t ms -=∴=
b. For R UP :
() 1.2(1)
20.8t RC
UP V t e
t ms -=-∴=
c. The ratio of delays is:
20.8
2.48.7
UP RATIO DOWN
t t t =
=
= or 0.42 (depending on which way you did the ratio.)