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EECS 247 Lecture 12: Data Converter Performance Metrics
Mixed Analog and Digital IC Design
ADC
DAC
Vout
Spectrum Analyzer
© 2008 H. K. Page 54
Data Converter Basics
Data Converter Performance Metrics
Mixed Analog and Digital IC Design
© 2008 H. K. Page 50
Data Converter Basics
Static Measurement
Example: Hiding Problems in the Noise
DNL/INL Measurement – Histogram Testing
Input with known PDF; amplitude & offset don’t matter Ramp: uniform pdf, difficult with high purity generation Sine: ”bath-tub” shape PDF, IEEE standard
Data Converter Basics
Dynamic Performance
Discrete Fourier Transform (DFT) Properties
• DFT of N samples spaced Ts=1/fs seconds:
– N frequency bins from DC to fs – Bin m represents frequencies at m * fs /N [Hz]
EECS 247 Lecture 12:
Data Converter Performance Metrics
Mixed Analog and Digital IC Design
© 2008 H. K. Page 55
Data Converter Basics
Dynamic Performance
Analyzing ADC Outputs via Discrete Fourier Transform (DFT)
Data Converter Basics
Dynamic Performance
Direct ADC Spectral Test via DAC
Device Under Test (DUT) Vin Signal Generator Clock Generator
• Need DAC with much better performance compared to ADC under test • Beware of DAC output sinx/x frequency shaping • Good way to "get started"...
• For additional info
EECS 247 Lecture 12:
Spectral testing
© 2008 H. K. Page 52
Data Converter Performance Metrics
Mixed Analog and Digital IC Design
Data Converter Basics
Mixed Analog and Digital Integrated Circuit Design
/
{qli,huanglt}@
2009–2010
Mixed Analog and Digital IC in Last Lecture
Dynamic Performance
ADC Spectral Test via Data Acquisition Sytem
Device Under Test (DUT) Vin Signal Generator Clock Generator ADC Data Acquisition System PC
Am =
n=0
Σx
n WN
mn
m = 0,1,2,…,N-1
WN ≡ e
EECS 247 Lecture 12:
-j2π/N
Data Converter Performance Metrics
Mixed Analog and Digital IC Design
© 2008 H. K. Page 57
INL
Code transition deviation from ideal position, always analog INL[i], i=[1,2,· · · N-2] INL[m] = m−1 DNL[i] 1 Ideal curve: end-point & best-fit
Monotonocity
• INL 5 missing codes • DNL "smeared out" by noise! • Always look at both DNL/INL • INL usually does not lie...
EECS 247 Lecture 12:
[Source: David Robertson, Analog Devices]
EECS 247 Lecture 12:
Data Converter Performance Metrics
Mixed Analog and Digital IC Design
© 2008 H. K. Page 58
Data Converter Basics
Dynamic Performance
DFT Magnitude Plots
DAC: non-monotonic when DNL<-1 ADC: complicated, no DNL definition at non-monotonic steps
DNL/INL Measurement – Code Boundary Servo
Feedback loop to find code transition point Slow; error due to ADC kicking-back
• Because magnitudes of DFT bins (Am) are symmetric around fS /2, it is redundant to plot ⏐Am⏐’s for m >N/2
0 •
fs/2
fs
Usually magnitudes are plotted on a log scale normalized so that a full scale sinusoidal waveform with rms value aFS yields a peak bin of 0dBFS:
• Static testing does not tell the full story
– E.g. no info about "noise“ or high frequency effects
• Frequency dependence (fs and fin) ?
– In principle we can vary fs and fin when performing histogram tests – Result of such sweeps is usually not very useful – Hard to separate error sources, ambiguity – Typically we use fs=fsNOM and fin << fs/2 for histogram tests
Discrete Fourier Transform
The DFT of a block of N time samples {x(k)} = {x(0), x(1), x(2),…,x(N-1)} yields a set of N frequency bins {Am} = {A0,A1,A2,…,AN-1} where: N-1
Dynamic Performance
DAC Spectural Test or Simulation
Digital Sinusoid Signal Generator Device Under Test (DUT) Vout Spectrum Analyzer
DAC
Clock Generator
• Input sinusoid linearity Need to have significantly better purity compared to DAC
EECS 247 Lecture 12: Data Converter Performance Metrics
Mixed Analog and Digital IC Design
© 2008 H. K. Page 56
Data Converter Basics
Dynamic Performance
•
Ref: B. Ginetti and P. Jespers, “Reliability of Code Density Test for High Resolution ADCs,” Electron. Lett., vol. 27, pp. 2231-3, Nov. 1991.
EECS 247 Lecture 12:
• DFT frequency resolution:
– Proportional to fs /N in [Hz/bin]
• DFT with N = 2k ( k is an integer) can be found using a computationally more efficient algorithm named: – FFT Fast Fourier Transform
x(t)
⇒
x(k)
• Sinusoidal waveform has all its power at one single frequency • An ideal, infinite resolution ADC would preserve ideal, single tone spectrum • DFT used as a vehicle to reveal ADC deviations from ideality
Data Converter Performance Metrics
Mixed Analog and Digital IC Design
© 2008 H. K. Page 51
Data Converter Basics
Dynamic Performance
Why Additional Tests/Metrics?
• Spectrum analyzer need to have better linearity than DUT
EECS 247 Lecture 12: Data Converter Performance Metrics © 2008 H. K. Page 53
Mixed Analog and Digital IC Design
Mixed Analog and Digital IC Design
Data Converter Basics
Static Measurement
Histogram Testing Limitations
• • • The histogram (as any ADC test, of course) characterizes one particular converter. Test many devices to get valid statistics. Histogram testing assumes monotonicity E.g. “code flips” will not be detected. Dynamic sparkle codes produce only minor DNL/INL errors E.g. 123, 123, …, 123, 0, 124, 124, … look at ADC output to detect Noise not detected & averaged out E.g. 9, 9, 9, 10, 9, 9, 9, 10, 9, 10, 10, 10, …
Mixed Analog and Digital IC Design
ADC
DAC
Vout
Spectrum Analyzer
© 2008 H. K. Page 54
Data Converter Basics
Data Converter Performance Metrics
Mixed Analog and Digital IC Design
© 2008 H. K. Page 50
Data Converter Basics
Static Measurement
Example: Hiding Problems in the Noise
DNL/INL Measurement – Histogram Testing
Input with known PDF; amplitude & offset don’t matter Ramp: uniform pdf, difficult with high purity generation Sine: ”bath-tub” shape PDF, IEEE standard
Data Converter Basics
Dynamic Performance
Discrete Fourier Transform (DFT) Properties
• DFT of N samples spaced Ts=1/fs seconds:
– N frequency bins from DC to fs – Bin m represents frequencies at m * fs /N [Hz]
EECS 247 Lecture 12:
Data Converter Performance Metrics
Mixed Analog and Digital IC Design
© 2008 H. K. Page 55
Data Converter Basics
Dynamic Performance
Analyzing ADC Outputs via Discrete Fourier Transform (DFT)
Data Converter Basics
Dynamic Performance
Direct ADC Spectral Test via DAC
Device Under Test (DUT) Vin Signal Generator Clock Generator
• Need DAC with much better performance compared to ADC under test • Beware of DAC output sinx/x frequency shaping • Good way to "get started"...
• For additional info
EECS 247 Lecture 12:
Spectral testing
© 2008 H. K. Page 52
Data Converter Performance Metrics
Mixed Analog and Digital IC Design
Data Converter Basics
Mixed Analog and Digital Integrated Circuit Design
/
{qli,huanglt}@
2009–2010
Mixed Analog and Digital IC in Last Lecture
Dynamic Performance
ADC Spectral Test via Data Acquisition Sytem
Device Under Test (DUT) Vin Signal Generator Clock Generator ADC Data Acquisition System PC
Am =
n=0
Σx
n WN
mn
m = 0,1,2,…,N-1
WN ≡ e
EECS 247 Lecture 12:
-j2π/N
Data Converter Performance Metrics
Mixed Analog and Digital IC Design
© 2008 H. K. Page 57
INL
Code transition deviation from ideal position, always analog INL[i], i=[1,2,· · · N-2] INL[m] = m−1 DNL[i] 1 Ideal curve: end-point & best-fit
Monotonocity
• INL 5 missing codes • DNL "smeared out" by noise! • Always look at both DNL/INL • INL usually does not lie...
EECS 247 Lecture 12:
[Source: David Robertson, Analog Devices]
EECS 247 Lecture 12:
Data Converter Performance Metrics
Mixed Analog and Digital IC Design
© 2008 H. K. Page 58
Data Converter Basics
Dynamic Performance
DFT Magnitude Plots
DAC: non-monotonic when DNL<-1 ADC: complicated, no DNL definition at non-monotonic steps
DNL/INL Measurement – Code Boundary Servo
Feedback loop to find code transition point Slow; error due to ADC kicking-back
• Because magnitudes of DFT bins (Am) are symmetric around fS /2, it is redundant to plot ⏐Am⏐’s for m >N/2
0 •
fs/2
fs
Usually magnitudes are plotted on a log scale normalized so that a full scale sinusoidal waveform with rms value aFS yields a peak bin of 0dBFS:
• Static testing does not tell the full story
– E.g. no info about "noise“ or high frequency effects
• Frequency dependence (fs and fin) ?
– In principle we can vary fs and fin when performing histogram tests – Result of such sweeps is usually not very useful – Hard to separate error sources, ambiguity – Typically we use fs=fsNOM and fin << fs/2 for histogram tests
Discrete Fourier Transform
The DFT of a block of N time samples {x(k)} = {x(0), x(1), x(2),…,x(N-1)} yields a set of N frequency bins {Am} = {A0,A1,A2,…,AN-1} where: N-1
Dynamic Performance
DAC Spectural Test or Simulation
Digital Sinusoid Signal Generator Device Under Test (DUT) Vout Spectrum Analyzer
DAC
Clock Generator
• Input sinusoid linearity Need to have significantly better purity compared to DAC
EECS 247 Lecture 12: Data Converter Performance Metrics
Mixed Analog and Digital IC Design
© 2008 H. K. Page 56
Data Converter Basics
Dynamic Performance
•
Ref: B. Ginetti and P. Jespers, “Reliability of Code Density Test for High Resolution ADCs,” Electron. Lett., vol. 27, pp. 2231-3, Nov. 1991.
EECS 247 Lecture 12:
• DFT frequency resolution:
– Proportional to fs /N in [Hz/bin]
• DFT with N = 2k ( k is an integer) can be found using a computationally more efficient algorithm named: – FFT Fast Fourier Transform
x(t)
⇒
x(k)
• Sinusoidal waveform has all its power at one single frequency • An ideal, infinite resolution ADC would preserve ideal, single tone spectrum • DFT used as a vehicle to reveal ADC deviations from ideality
Data Converter Performance Metrics
Mixed Analog and Digital IC Design
© 2008 H. K. Page 51
Data Converter Basics
Dynamic Performance
Why Additional Tests/Metrics?
• Spectrum analyzer need to have better linearity than DUT
EECS 247 Lecture 12: Data Converter Performance Metrics © 2008 H. K. Page 53
Mixed Analog and Digital IC Design
Mixed Analog and Digital IC Design
Data Converter Basics
Static Measurement
Histogram Testing Limitations
• • • The histogram (as any ADC test, of course) characterizes one particular converter. Test many devices to get valid statistics. Histogram testing assumes monotonicity E.g. “code flips” will not be detected. Dynamic sparkle codes produce only minor DNL/INL errors E.g. 123, 123, …, 123, 0, 124, 124, … look at ADC output to detect Noise not detected & averaged out E.g. 9, 9, 9, 10, 9, 9, 9, 10, 9, 10, 10, 10, …