FPGA编写的串口通信程序

//接收器
module async_receiver(clk,rst,RxD,RxD_data,RxD_data_ready);
input clk,rst,RxD;
output [7:0] RxD_data;
output RxD_data_ready;

reg[7:0] RxD_data;
reg RxD_data_ready;

parameter ClkFrequency = 16384000; // 50MHz
parameter Baud = 115200; //比特率

parameter Baud8 = Baud*8; //8倍的采样时钟
parameter Baud8GeneratorAccWidth = 16;
parameter Baud8GeneratorInc = ((Baud8<<(Baud8GeneratorAccWidth-7))+(ClkFrequency>>8))/(ClkFrequency>>7);
reg [Baud8GeneratorAccWidth:0] Baud8GeneratorAcc;

always @(posedge clk or negedge rst)
begin
if(~rst)
Baud8GeneratorAcc <= 0;
else
Baud8GeneratorAcc <= Baud8GeneratorAcc[Baud8GeneratorAccWidth-1:0] + Baud8GeneratorInc;
end
// Baud8Tick 为波特率的8倍
wire Baud8Tick = Baud8GeneratorAcc[Baud8GeneratorAccWidth];

//用两个D触发器构成移位寄存器，用于采样
reg [1:0] RxD_sync;
always @(posedge clk)
if(Baud8Tick)
RxD_sync <= {RxD_sync[0],~RxD};

//滤波
reg [1:0] RxD_cnt;
reg RxD_bit;
always @(posedge clk)
if(Baud8Tick)
begin
if(RxD_sync[1] && RxD_cnt!=2'b11) RxD_cnt <= RxD_cnt + 1;
else if (~RxD_sync[1] && RxD_cnt!=2'b00) RxD_cnt <= RxD_cnt - 1;
if(RxD_cnt==2'b00) RxD_bit <= 0;
else if(RxD_cnt==2'b11) RxD_bit <= 1;
end

// next_bit 为波特率 － 115200
reg [3:0] state;
reg [2:0] bit_spacing;
always @(posedge clk or negedge rst)
if(~rst)
bit_spacing <= 0;
else if(state == 0)
bit_spacing <= 0;
else if(Baud8Tick)
bit_spacing <= bit_spacing + 1;
wire next_bit = (bit_spacing==7);

always @(posedge clk or negedge rst)
if(~rst)
state <= 4'b0000;
else if(Baud8Tick)
case(state)
4'b0000: if(RxD_bit) state <= 4'b1000; // start bit found?
4'b1000: if(next_bit) state <= 4'b1001; // bit 0
4'b1001: if(next_bit) state <= 4'b1010; // bit 1
4'b1010: if(next_bit) state <= 4'b1011; // bit 2
4'b1011: if(next_bit) state <= 4'b1100; // bit 3
4'b1100: if(next_bit) state <= 4'b1101; // bit 4
4'b1101: if(next_bit) state <= 4'b1110; // bit 5
4'b1110: if(next_bit) state <= 4'b1111; // bit 6
4'b1111: if(next_bit) state <= 4'b0001; // bit 7
4'b0001: if(next_bit) state <= 4'b0000; // stop bit
default: state <= 4'b0000;
endcase

always @(posedge clk or negedge rst)
if(~rst)
RxD_data <= 8'b00000000;
else if(Baud8Tick && next_bit && state[3]) RxD_data <= {~RxD_bit,RxD_data[7:1]};

always @(posedge clk or negedge rst)
if(~rst)
RxD_data_ready <= 0;
else RxD_data_ready <=(Baud8Tick && next_bit && state==4'b0001);

endmodule






//发送器
module async_transmitter(clk,rst, TxD_start, TxD_data, TxD, TxD_busy);
input clk, rst,TxD_start;
input [7:0] TxD_data;
output TxD, TxD_busy;

reg TxD;
reg [7:0] TxD_dataReg; // 寄存器发送模式，因为在串口发送过程中输入端不可能一直保持有效电平
reg [3:0] state;

parameter ClkFrequency = 50000000; // 50MHz
parameter Baud = 115200;

// Baud generator
parameter BaudG

eneratorAccWidth = 16;
parameter BaudGeneratorInc = ((Baud<<(BaudGeneratorAccWidth-4))+(ClkFrequency>>5))/(ClkFrequency>>4);
reg [BaudGeneratorAccWidth:0] BaudGeneratorAcc;
wire BaudTick = BaudGeneratorAcc[BaudGeneratorAccWidth];
wire TxD_busy;
always @(posedge clk or negedge rst)
if(~rst)
BaudGeneratorAcc <= 0;
else if(TxD_busy)
BaudGeneratorAcc <= BaudGeneratorAcc[BaudGeneratorAccWidth-1:0] + BaudGeneratorInc;

assign TxD_busy = (state!=0);

// 把待发送数据放入缓存寄存器 TxD_dataReg
always @(posedge clk or negedge rst)
if(~rst)
TxD_dataReg <= 8'b00000000;
else if(~TxD_busy & TxD_start)
TxD_dataReg <= TxD_data;

// 发送状态机
always @(posedge clk or negedge rst)
if(~rst)
begin
state <= 4'b0000; // 复位时，状态为0000，发送端一直发1电平
TxD <= 1'b1;
end
else
case(state)
4'b0000: if(TxD_start) begin
state <= 4'b0100; // 接受到发送信号，进入发送状态
end
4'b0100: if(BaudTick) begin
state <= 4'b1000; // 发送开始位 - 0电平
TxD <= 1'b0;
end
4'b1000: if(BaudTick) begin
state <= 4'b1001; // bit 0
TxD <= TxD_dataReg[0];
end
4'b1001: if(BaudTick) begin
state <= 4'b1010; // bit 1
TxD <= TxD_dataReg[1];
end
4'b1010: if(BaudTick) begin
state <= 4'b1011; // bit 2
TxD <= TxD_dataReg[2];
end
4'b1011: if(BaudTick) begin
state <= 4'b1100; // bit 3
TxD <= TxD_dataReg[3];
end
4'b1100: if(BaudTick) begin
state <= 4'b1101; // bit 4
TxD <= TxD_dataReg[4];
end
4'b1101: if(BaudTick) begin
state <= 4'b1110; // bit 5
TxD <= TxD_dataReg[5];
end
4'b1110: if(BaudTick) begin
state <= 4'b1111; // bit 6
TxD <= TxD_dataReg[6];
end
4'b1111: if(BaudTick) begin
state <= 4'b0010; // bit 7
TxD <= TxD_dataReg[7];
end
4'b0010: if(BaudTick) begin
state <= 4'b0011; // stop
TxD <= 1'b1;
end

default: if(BaudTick) begin
state <= 4'b0000;
TxD <= 1'b1;
end
endcase
endmodule


//232控制器
module RS232_Controller(oDATA,iDATA,oTxD,oTxD_Busy,iTxD_Start,
iRxD,oRxD_Ready,iCLK,irst);
input [7:0] iDATA;
input iTxD_Start,iRxD,iCLK,irs

t;
output [7:0] oDATA;
output oTxD,oTxD_Busy,oRxD_Ready;

async_receiver u0 ( .clk(iCLK), .RxD(iRxD), .rst(irst),
.RxD_data_ready(oRxD_Ready),
.RxD_data(oDATA));
async_transmitter u1 ( .clk(iCLK), .TxD_start(iTxD_Start), .rst(irst),
.TxD_data(iDATA), .TxD(oTxD),
.TxD_busy(oTxD_Busy));

endmodule