片上多核处理器架构

INTEL
2006，Woodcrest (Xeon 5100) 2006，Clovertown四核
Qi Zhang, USTC 2
发展趋势
提高处理器性能
提高主频 更多核心
主频的提高带来功耗的提高，传统的体系结构 技术已面临瓶颈，纷纷转向多线程和多内核。
Qi Zhang, USTC
Qi Zhang, USTC
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Cell处理器架构
Qi Zhang, USTC
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Tile64
Qi Zhang, USTC
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TILE64™ Processor Block Diagram
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Tile64™ Processor Family
The TILE64™ family of multicore processors delivers immense compute performance to drive the latest generation of embedded applications. This revolutionary processor features 64 identical processor cores (tiles) interconnected with Tilera’s iMesh™ on-chip network. Each tile is a complete full-featured processor, including integrated L1 & L2 cache and a non-blocking switch that connects the tile into the mesh. This means that each tile can independently run a full operating system, or multiple tiles taken together can run a multi-processing operating system like SMP Linux. The TILE64™ processor family slashes board real estate and system cost by integrating a complete set of memory and I/O controllers, thus eliminating the need for an external North Bridge or South Bridge. It delivers scalable performance, power efficiency and low processing latency in an extremely compact footprint. With a standard ANSI C programming environment, developers can leverage their existing software investment as well as utilize the vast body of Open Source code available. Tiles can be grouped into clusters to apply the appropriate amount of horsepower to each application. Since multiple operating system instances can be run on the TILE64™ simultaneously, it can replace multiple CPU subsystems for both the data plane and control plane.
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AMD四核酷龙
Large shared L3 cache shares data between cores efficiently while helping reduce latency to main memory Dedicated L1 and L2 cache per core helps performance of virtualized environments and large databases by reducing cache pollution associated with a shared L2 cache The L1 cache of AMD Opteron processors can handle double the number of loads per cycle as Second-Generation AMD Opteron processors to help keep CPU cores busy
编译器设计人员
将一种高级语言程序按一种程序执行模型转换成一种目标 机器语言程序
系统实现人员
该程序执行模型在具体目标机器上的有效实现
程序执行模型的适用性决定多核处理器能否以 最低的代价提供最高的性能
Qi Zhang, USTC
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Intel Core微架构
Qi Zhang, USTC
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Intel双核
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wk.baidu.com
Intel Conroe
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Intel Core微架构
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Intel四核
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Intel四核
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AMD双核
Qi Zhang, USTC
缺点
基于总线的结构可扩展性较差
Qi Zhang, USTC
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基于片上互连的结构
每个CPU核心具有独立的处理单元和cache，各 个核心通过交叉开关或片上网络等方式连接在 一起，各个核心间通过消息通信。 优点
可扩展性好 数据带宽有保证
缺点
硬件结构复杂 软件改动较大
主流片上高效通信机制
基于总线共享的cache结构 基于片上的互连结构
Qi Zhang, USTC
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总线共享cache结构
每个CPU内核拥有共享的二级或三级cache (last level cache)，用于保存比较常用的数据，并通过 连接核心的总线进行通信。 优点
结构简单 通信速度高
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片上多核处理器体系结构
CMP (Chip Multi-Processor)
将多个计算内核集成在一个处理器芯片中，从而提高 计算能力
同构多核
Intel，AMD
异构多核
Cell (主处理核+协处理核)
Qi Zhang, USTC
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核间通信
硬件结构必须支持核间通信
CMP处理器各核心执行的程序之间需要进行数据共 享和同步 高效的通信机制是CMP处理器高性能的重要保障
Qi Zhang, USTC
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如何有效地利用多核技术？
现状
客户端应用程序开发者多年来一直停留在单线程世界， 生产“顺序软件”。
多核时代到来后
软件开发者必须找出新的开发软件的方法，选择程序 执行模型。
Qi Zhang, USTC
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程序执行模型
编译器设计人员与系统实现人员之间的接口
提纲
Qi Zhang, USTC
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片上多核处理器
IBM
2001，双核RISC处理器Power4 2006，Cell处理器
HP
2004，PA-RISC8800双核处理器
SUN
2004，UltraSPARC IV双核处理器
AMD
2005，Opteron(酷龙，服务器和工作站) 2005，Athlon 64 X2双核系列(速龙，台式机) 2007，Barcelona四核(巴塞罗那)