Quartus II 时序约束方法

Tdata Tclk2
REG2 D SET Q
Q CLR
μTsu/μTh
Data Arrival Time = launch edge + Tclk1 + μTco +Tdata
© 2007 Altera Corporation—Confidential Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 12
D SET Q
Q CLR
μTsu/μTh
Tclk2 μTsu
Latch Edge
Data Required Time = Clock Arrival Time – μTsu
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Data Arrival Time
The time for data to arrive at a register’s D input
Launch Edge
CLK
Tclk1
REG1 D SET Q
Q CLR
μTco
CLK REG1.CLK REG1.Q REG2.D
Tclk1 μTco Tdata
Complex clocking schemes Source-synchronous designs
© 2007 Altera Corporation—Confidential Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 5
© 2007 Altera Corporation—Confidential Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 2
Quartus II Software Design Series: Timing Analysis
© 2007 Altera Corporation—Confidential
常见术语的中文翻译
Tsetup: 建立时间 Thold：保持时间 Skew：传输时差,时钟歪斜 Slack：余量 Fmax：最大频率 Input maximum delay：输入最大延时 Input minimum delay：输入最小延时 Output maximum delay：输出最大延时 Output minimum delay：输出最小延时 Max delay ：最大延时 Min Delay：最小延时 Recovery time：恢复时间 Removal time：移去时间 Jitter：抖动
Validating Performance with the TimeQuest Static Timing Analyzer
TimeQuest Terminology Review
© 2007 Altera Corporation—Confidential
TimeQuest Terminology Review
Latch Edge: Clock edge that activates the destination register
© 2007 Altera Corporation—Confidential Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 11
TimeQuest Timing Analyzer
New timing engine in Quartus II Provide timing analysis solution
meeting requirements of all users
FPGA design background ASIC design background
Launch & Latch Edges
CLK
Launch Edge
CLK
DATA
REG1
SET
DQ
CLR
Comb. Logic
Data Valid
REG2
SET
DQ
CLR
Latch Edge
Launch Edge: Latch Edge:
the edge which “launches” the data from source register
Together, the setup time and hold time form a Data Required Window, the time around a clock edge in which data must be stable.
© 2007 Altera Corporation—Confidential Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 9
Launch & Latch Edges
A
CLKA
B
CLKB
CLKA CLKB
The relationship between the edges is derived from the user-defined clock settings
ቤተ መጻሕፍቲ ባይዱ
Launch Edge: Clock edge that activates the source register in a register-to-register path
Setup & Hold
DATA CLK
PRE
D
Q
CLR
CLK DATA
Tsu Th
Valid
Setup:
The minimum time data signal must be stable BEFORE clock edge
Hold:
The minimum time data signal must be stable AFTER clock edge
TimeQuest Timing Analyzer (cont.)
More accurate analysis
rise/fall delays
SDC Support
More advanced & standardized constraint methodology
Easily supports more complex designs and analysis
Two types of Analysis: 1. Synchronous – clock & data paths 2. Asynchronous* – clock & async paths
*Asynchronous refers to signals feeding the asynchronous control ports of the registers
the edge which “latches” the data at destination register (with respect to the launch edge, typically 1 cycle)
© 2007 Altera Corporation—Confidential Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 10
Clock Arrival Time
The time for clock to arrive at a register’s clock input
CLK
Tclk1
REG1 D SET Q
Q CLR
μTco
CLK REG2.CLK
Tdata Tclk2
REG2 D SET Q
Q CLR
μTsu/μTh
Launch & latch edges Arrival time vs. required time
Setup & hold analysis
Slack SDC terminology
© 2007 Altera Corporation—Confidential Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 7
Tclk2
Latch Edge
Clock Arrival Time = latch edge + Tclk2
© 2007 Altera Corporation—Confidential Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 13
Easy-to-use interface
Standard reporting & constraint terminology
Scripting emphasis
© 2007 Altera Corporation—Confidential Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 4
Path & Analysis Types
Async Path
PRE
D
Q
Data Path
PRE
D
Q
CLR
Clock Paths
CLR
Async Path
Three types of Paths: 1. Clock Paths 2. Data Path 3. Asynchronous Paths*
Data Required Time - Setup
Time signal must arrive at destination register to be properly sampled
CLK
CLK
Tclk1
REG1
D SET Q
Q CLR
μTco
REG2.CLK
Tdata Tclk2
REG2
TimeQuest Agenda
Introduction to TimeQuest TimeQuest terminology review Using TimeQuest Example Application
© 2007 Altera Corporation—Confidential Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 3
© 2007 Altera Corporation—Confidential Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 8
Data Required Time - Hold
Earliest time signal can arrive at destination register and not interfere with data sampled on previous clock edge