第十三章数模混合IP

Schematic Design & Hspice Netlist Simulation Digital Design Flow Layout & Verification
Layout Integration
Post Simulation in Transistor Level
How SA ADC Function?
• Successive approximation algorithm • 6 bits converter data output • Two analog input selection • Low power with power down switch • Internal reference voltage generator • The flags of start of conversion and
Mixed-signal design for SoC
• Digital and analog parts integrated in
ONE chip • Benefits:


• Limits:

Reduce the system size Reduce the consideration on parasitic on PCB Reduce the IO driving currents and parasitic loads
Advantages:

Limits:


Enlarge the system size, not chip size More bad effect from parasitic in PCB between two parts More difficulties in the consideration on IO pads, driving and load
end of conversion
The General Structure of SAR ADC
dout_reg[5:0] VDDD VSSD pd
soc_digatal clk comp_sar soc reset eoc soc_analog
Pat Generator
pat_start
Control Logic
• • •
Digital part included in VLSI chips, analog part outside, connected with each other by IO pad

Example: USB PHY Easy design for chip Reduce the single chip size
• Newton Division • R-2R network
VDAC
2R R R R R
VREF ( DN 1 2 1 DN 2 2 2
R …… 2R
DN 1
R
R
2R
2R
DN 2
2R
D N 3 DN 4
2R
D3
2R
D2
2R
D1
2R
D0
……
V
SA ADC Specification
ADC Digital Part Backend Design
• Synthesis with Design Compiler • Floorplan

• CTS • Routing • LVS & DRC • Final netlist generated, Verilog gate
level view
Agenda
• Mixed-signal design or IP in SoC • Mixed-signal design flow • The mixed-signal design key for SoC • The Mixed-signal verification in SoC
Why need mixed-signal design?
ADC General Usage
• To convert the analog voltage or
current value into digital codes • For battery power capacitance detection • For key-board press detection • Etc.
ims
6 Bit Shifter
comp
Level Shift
comp D5~~D0
Comparator
DAC_vref VIN_Sampled
DAC
VREF
Reference Operator
Smaple-Hold
soc_analog VSSA
VIN
Analog Input Mux
VIN1 VIN2
• Some function cannot be implemented by
ONLY digital principle!!!
vi (t )
PD LF VCO
vo (t )
Porgrammable Devider
The conventional mixed-signal design operation
第十三章
数模混合IP的设计与集成
Outlines
• Mixed-signal design or IP in SoC • Mixed-signal design flow • The mixed-signal design key for SoC • The Mixed-signal verification in SoC
Conventional Mixed Signal Design Approach
Whole-chip Specification
Digital and Analog Module Definition Digital Sub-module Definition Analog Blocks Definition
May enlarge the chip size Increase process complexity Noise isolation carefully
Mixed-signal design for SoC
• The normal designdesign or IP or IP in SoC The mixed-signal
Analog Design
• Making the circuit
schematics • Standard alone simulation with netlist written in Spice with Hspice to check the function and performance
VIN1 VIN2
VDDA
ADC Digital Part Design
• Sub-module Definition, using Verilog RTL to
implement

Control Logic

Synchronize the input signal Send the soc flag to all module Generate the eoc flag and collect the converter data output to the system According to the soc flag to generate converter pat To Shift the pat for 6 cycles for each converter channel
SAR
B5~~B0 D5~~D0
ims
6 Bit Shifter
comp
Level Shift
comp D5~~D0
Comparator
DAC_vref VIN_Sampled
DAC
VREF
Reference Operator
Smaple-Hold
soc_analog VSSA
VIN
Analog Input Mux

• SDF from PT • Post simulation in VCS, etc.
Parasitic resistance and capacitance value Parasitic resistance and capacitance location Cell level, cell view
• Compare MSB first, then down to LSB • Example: 3-bit Successive approximation
Key Algorithm Implementation
VDAC VREF N ( D N 1 2 N 1 R D N 2 2 N 2 R 2 R D112 R D0 R) D 2 N 1 D0 2 N )

Pat Generator


6 Bit Shift

ADC Digital Part Design (cont)

SAR Successive approximation algorithm realization Control the binary switch of the DAC in analog part for each corresponding channel (bit) Lock the converter data To offer converter register data for output
Layout
• Manual layout for analog block • Digital block layout space left with
limited area specific pin direction assignment Powrt Layout Result
Parasitic Extraction
• For post simulation with SDF file • SPEF files generated
The General Structure of SAR ADC
dout_reg[5:0] VDDD VSSD pd
soc_digatal clk comp_sar soc reset eoc soc_analog
Pat Generator
pat_start
Control Logic
SAR
B5~~B0 D5~~D0
VDDA
ADC Analog Part Design
• Blocks Definition





Analog Input Mux Analog voltage input selection Sample-hold Analog sampling and voltage holding Reference Operator Standard reference voltage generator, bandgap bias generator for PMOS DAC Digital to analog converter, R-2R resistance network Comparator Comparing the sampled VIN with Vref from DAC

• The parts’ respective function

PLL ADC
Digital: Controlling logic and simple algorithm Analog: Communicating with external analog signal and dealing with the voltage outside the digital value margin
Agenda
• Mixed-signal design or IP in SoC • Mixed-signal design flow • The mixed-signal design key for SoC • The Mixed-signal verification in SoC

A 6-bit SA ADC Design