中科院研究生院课程VLSI测试与可测试性设计(精)
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VLSI Test Principles and Architectures
EE141
3
Logic & Fault Simulation
Logic and Fault Simulation
Introduction Simulation models Logic simulation Fault simulation Concluding remarks
zi: primary output (PO) yi: pseudo primary input (PPI)
y2
yl
Y2
Yl
clock
9
VLSI Test Principles and Architectures
EE141
Flip-Flops
Yi: pseudo primary output (PPO)
10
Logic & Fault Simulation
Example: A Full-Adder
a
c e d
f
b
HA
HA; inputs: a, b; outputs: c, f; AND: A1, (a, b), (c); AND: A2, (d, e), (f); OR: O1, (a, b), (d); NOT: N1, (c), (e);
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VLSI Test Principles and Architectures
EE141
4
Logic & Fault Simulation
Logic Simulation
Predict the behavior of a design prior to its physical realization Specification Design verification
9
Logic & Fault Simulation
A Positive Edge-Triggered D-FF
PresetB
PresetBk
QB
ClearB
D ClearB
10
VLSI Test Principles and Architectures
EE141
EE141
11
Logic & Fault Simulation
Logic Symbols
The most commonly used are 0, 1, u and Z 1 and 0
Manual design or via Synthesis Testbench Development
Circuit Description yes Bug? no Next Design Stage
VLSI Test Principles and Architectures
Input Stimuli
process imperfections
An important tool for test and diagnosis
Estimate fault coverage Fault simulator Test compaction Fault diagnosis
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VLSI Test Principles and Architectures
A B C
HA1
D E
HA2
F
Carry Sum
FA; inputs: A, B, C; outputs: Carry, Sum; HA: HA1, (A, B), (D, E); HA: HA2, (E, C), (F, Sum); OR: O2, (D, F), (Carry);
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VLSI Test Principles and Architectures
Chapter 3 Logic and Fault Simulation
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VLSI Test Principles and Architectures
EE141
2
Logic & Fault Simulation
About the Chapter
Circuit simulation models Logic simulation techniques Fault simulation techniques
EE141
6
Logic & Fault Simulation
Logic and Fault Simulation
Introduction Simulation models Logic simulation Fault simulation Concluding remarks
7
Expected Responses
Simulated Responses Response Analysis
5
5 Logic & Fault Simulation
EE141
Fault Simulation
Predicts the behavior of faulty circuits
As a consequence of inevitable fabrication
VLSI Test Principles and Architectures
EE141
7
Logic & Fault Simulation
Gate-Level Network
The interconnections of logic gates
A
G2
H
G4 L
K
B
C
G1
E
F
G3
J
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VLSI Test Principles and Architectures
EE141
8
Logic & Fault Simulation
Sequential Circuits
x1 z1 z2
The outputs depend on both the current and past input values
x2 xn
Combinational Logic
zm
y1
Y1
xi: primary input (PI)
中科院研究生院课程:VLSI测试与可测试性设计
第4讲 逻辑与故障模拟 李晓维
中科院计算技术研究所
Email: lxw@
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VLSI Test Principles and Architectures
EE141
1
Logic & Fault Simulation