【精品课件】静态时序分析基本原理和时序分析模型

8
Clock Arrival Time
The time for clock to arrive at destination register’s clock input
REG1
PRE
DQ
Comb. Logic
REG2
PRE
DQ
CLK
CLR
CLR
Tclk2
Tclk2
Latch Edge
REG2.CLK
Quartus® II Software Design Series: Timing Analysis
- Timing analysis basics
Objectives
Display a plete understanding of timing analysis
2
How does timing verification work?
Two types of Analysis: 1. Synchronous – clock & data paths 2. Asynchronous* – clock & async paths
*Asynchronous refers to signals feeding the asynchronous control ports of the registers
Clock Arrival Time = latch edge + Tclk2
9
Data Required Time - Setup
The minimum time required for the data to get latched into the destination
register
5
Launch & Latch Edges
CLK
Launch Edge
CLK
DATA
REG1
SET
DQ
CLR
Comb. Logic
Data Valid
REG2
SET
DQ
CLR
Latch Edge
Launch Edge: Latch Edge:
the edge which “launches” the data from source register
10
Data Required Time - Hold
The minimum time required for the data to get latched into the destination
the edge which “latches” the data at destination register (with respect to the launch edge, selected by timing analyzer; typically 1 cycle)
6
Setup & Hold
Together, the setup time and hold time form a Data Required Window, the time around a clock edge in which data must be stable.
7
Data Arrival Time
The time for data to arrive at destination register’s D input
DATA CLK
PRE
D
Q
CLR
CLK DATA
Tsu Th
Valid
Setup: Hold:
The minimum time data signal must be stable BEFORE clock edge
The minimum time data signal must be stable AFTER clock edge
Every device path in design must be analyzed with respect to timing specifications/requirements
Catch timing-related errors faster and easier than gate-level simulation & board testing
Designer must enter timing requirements & exceptions
Used to guide fitter during placement & routing Used to pare against actual results
IN CLK CLR
PRE
REG1
PRE
DQ
Comb. Logic
REG2
PRE
DQ
CLK
REG2.CLK REG2.D
CLR
Data must be valid here
Tclk2
CLR
Tsu
Tclk2
Tsu
Latch Edge
Data Valid
Data Required Time = Clock Arrival Time - Tsu - Setup Uncertainty
4
Path & Analysis Types
Async Path
PRE
D
Q
CLR
Clock Paths
Data Path
PRE
D
Q
CLR
Async Path
Three types of Paths: 1. Clock Paths 2. Data Path 3. Asynchronous Paths*
Launch Edge
Tclk1
REG1
PREΒιβλιοθήκη DQCLRTCOComb. Logic
Tdata
REG2
PRE
DQ
CLR
CLK REG1.CLK
REG1.Q
REG2.D
Tclk1 Tco
Tdata
Data Valid Data Valid
Data Arrival Time = launch edge + Tclk1 + Tco +Tdata
D
Q
CLR
PRE
D
Q
CLR
OUT
binational delays
3
Timing Analysis Basics
Launch vs. latch edges Setup & hold times Data & clock arrival time Data required time Setup & hold slack analysis I/O analysis Recovery & removal Timing models