LATTICE timing closure

Known Issue
BLOCK on individual net will not be reported in Trace report So – be careful with BLOCK NET
Timing Closure Training May 2014
Page: 10
Lattice Semiconductor Confidential
Timing Closure Training May 2014
Page: 5
Lattice Semiconductor Confidential
CHECKING PREFERENCES’ ACCURACY
Three most important items:
1. 2. 3. Pin Constraints Timing Constraints Other Constraints
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Reality:
Most designers prefer to concentrate on RTL and a simple push button flow Some designers are less dealing with the RTL for timing Some designers are against idea 3 for code portability
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Lattice’s Recommendation:
For timing closure for Lattice’s low cost FPGAs, # 3 is crucial and most effective Software algorithm issues are real Issues, more often “heuristic” usually takes long time to tune and resolve Spend more time on #3 is also a practical approach for AE/FAE.
Three Drivers to Successful FPGA Timing Closure:
1. 2. 3. RTL Software Tools and Silicon Good Correlation (“Conditioning”) of RTL to better fit both Software Tools and Silicon
Very useful to check that BLOCK is accurate ! If BLOCK covers paths you did not intend, PAR will ignore paths that need to meet a timing requirement, and Trace report will not show a timing violation if one actually exists
PREFERENCE: MULTICYCLE
Allows for relaxation of previously defined PERIOD or FREQUENCY constraints on a path.
Use MAXDELAY (instead of MULTICYCLE) for Paths that are not within the domain of the FREQUENCY/PERIOD
Tune RTL
Multiple PAR run
If the design is not routable
Relax constraint in Synthesis Reduce number of signal and number of connections
Timing Closure Training May 2014
Timing Closure Training May 2014
Page: 8
Lattice Semiconductor Confidential
PREFERENCE: BLOCK
Block timing analysis on nets, paths, buses, or component pins that are irrelevant to the timing of the design.
If a net is specified, the net and all paths through the specified net are blocked. If a bus is specified, the bus, all nets in the bus, and all paths through the nets defined by the bus are blocked.
MULTICYCLE FROM CLKNET "clka" TO CLKNET "clkb" 2.0 X ; MULTICYCLE FROM CELL "R_REG1" TO CELL "R_REG3" 3.0 X ; MULTICYCLE FROM CLKNET “clka” TO CLKNET “clkb” 0.75 X; MULTICYCLE FROM CLKNET “clka” CLKEN_NT “clken” TO CLKNET “clkb” 3.0 x MULTICYCLE FROM CLKNET “clka” TO CLKNET “clkb” 4.0 X_SOURCE;
Timing Closure Training May 2014
Page: 9
Lattice Semiconductor Confidential
WHAT PATHS COVERED BY BLOCK? 2.1 and Later
In General, Trace report will report paths covered by BLOCK
DSP related function use all three registers
Obvious register/pipelining opportunity
HDL changes to consider later
I/O timing, to use or not to use I/O registers Clock enable implementation Manual fanout control DSP block used to implement none arithmetic functions (ECP3)
Timing Closure Training May 2014 Page: 6 Lattice Semiconductor Confidential
TIMING CONSTRAINTS REVIEW
Create constraint:
FREQUENCY INPUT_SETUP CLOCK_TO_OUT MAXDELAY CLKSKEWDIFF
Take care of your Pin Constraints first
Timing results are useless if pinBiblioteka Baiduconstraints are incorrect Eliminates unnecessary run iterations
Other Constraints
RTL coding tricks Symptoms of root causes How to get the final 5%
Timing Closure Training May 2014
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Lattice Semiconductor Confidential
BASIC DRIVERS FOR SUCCESS
If the design is routable but did not achieve timing
Relax design goals (preference values) if possible Add relaxation preferences (BLOCK, MULTICYCLE) Always - check constraint coverage (eg clock domain transfer) Check potential timing preference “traps”
Timing Closure Training May 2014
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Lattice Semiconductor Confidential
STANDARD DESIGN TASKS
If the design is routable and achieved timing
Check preferences’ accuracy Check if coverage is enough Use the timing closure techniques to build margin
Location constraints of specific modules or instantiations must be followed if an IP or Application Notes require them Miscellaneous settings
Recommendation: Run your design without any timing constraints, but with the above constraints to make sure the constraints above are correct
Relax existing constraint:
MULTICYCLE BLOCK
Recommended default inclusion:
BLOCK RESETPATH
BLOCK ASYNCPATH
Timing Closure Training May 2014
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Lattice Semiconductor Confidential
TIMING CLOSURE
AGENDA Timing Closure
Introduction Basic Drivers for Success
HDL coding, Preference coverage
Preferences Timing traps from over-constraining Synthesis / MAP checkpoint Preparing for PAR PAR checkpoint
BLOCK PATH FROM PORT "L_CMD0" TO CELL "RAM_OE_N_REG";
BLOCK PATH FROM CLKNET "clknet_1 " TO CLKNET "clknet_2 ";
Two totally different uses for BLOCK
1. Relax constrained paths (e.g. false path) 2. Add unconstrained paths to “covered paths %” ( ­ Paths crossing between to unrelated clocks
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Lattice Semiconductor Confidential
CODING FOR TIMING CLOSURE Low Hanging Fruit
Upfront HDL for better performance
Shift register not using distributed RAM Block RAM related designs use the output register State machine encoding