MOS-Ch08-e3 《现代操作系统》Andreww S.Tanenbaum配套课件ppt
合集下载
相关主题
- 1、下载文档前请自行甄别文档内容的完整性，平台不提供额外的编辑、内容补充、找答案等附加服务。
- 2、"仅部分预览"的文档,不可在线预览部分如存在完整性等问题,可反馈申请退款(可完整预览的文档不适用该条件!)。
- 3、如文档侵犯您的权益，请联系客服反馈,我们会尽快为您处理(人工客服工作时间：9:00-18:30)。
Tanenbaum, Modern Operating Systems 3 e, (c) 2008 Prentice-Hall, Inc. All rights reserved. 0-13-6006639
Master-Slave Multiprocessors
Figure 8-8. A master-slave multiprocessor model.
Tanenbaum, Modern Operating Systems 3 e, (c) 2008 Prentice-Hall, Inc. All rights reserved. 0-13-6006639
Multiprocessor Synchronization (1)
Figure 8-10. The TSL instruction can fail if the bus cannot be locked. These four steps show a sequence of events where the failure is demonstrated.
Figure 8-5. An omega switching network.
Tanenbaum, Modern Operating Systems 3 e, (c) 2008 Prentice-Hall, Inc. All rights reserved. 0-13-6006639
NUMA Multiprocessors (1)
Figure 8-6. (a) A 256-node directory-based multiprocessor.
Tanenbaum, Modern Operating Systems 3 e, (c) 2008 Prentice-Hall, Inc. All rights reserved. 0-13-6006639
Tanenbaum, Modern Operating Systems 3 e, (c) 2008 Prentice-Hall, Inc. All rights reserved. 0-13-6006639
UMA Multiprocessors Using Multistage Switching Networks (2)
Tanenbaum, Modern Operating Systems 3 e, (c) 2008 Prentice-Hall, Inc. All rights reserved. 0-13-6006639
Symmetric Multiprocessors
Figuwk.baidu.come 8-9. The SMP multiprocessor model.
Each CPU Has Its Own Operating System
Figure 8-7. Partitioning multiprocessor memory among four CPUs, but sharing a single copy of the operating system code. The boxes marked Data are the operating system’s private data for each CPU.
UMA Multiprocessors with Bus-Based Architectures
Figure 8-2. Three bus-based multiprocessors. (a) Without caching. (b) With caching. (c) With caching and private memories.
NUMA Multiprocessors (3)
Figure 8-6. (b) Division of a 32-bit memory address into fields. (c) The directory at node 36.
Tanenbaum, Modern Operating Systems 3 e, (c) 2008 Prentice-Hall, Inc. All rights reserved. 0-13-6006639
Multiple Processor Systems
Figure 8-1. (a) A shared-memory multiprocessor. (b) A messagepassing multicomputer. (c) A wide area distributed system.
Tanenbaum, Modern Operating Systems 3 e, (c) 2008 Prentice-Hall, Inc. All rights reserved. 0-13-6006639
access to local memory.
Tanenbaum, Modern Operating Systems 3 e, (c) 2008 Prentice-Hall, Inc. All rights reserved. 0-13-6006639
NUMA Multiprocessors (2)
Characteristics of NUMA machines: 1. There is a single address space visible to all
CPUs. 2. Access to remote memory is via LOAD and
STORE instructions. 3. Access to remote memory is slower than
MODERN OPERATING SYSTEMS
Third Edition ANDREW S. TANENBAUM
Chapter 8 Multiple Processor Systems
Tanenbaum, Modern Operating Systems 3 e, (c) 2008 Prentice-Hall, Inc. All rights reserved. 0-13-6006639
Master-Slave Multiprocessors
Figure 8-8. A master-slave multiprocessor model.
Tanenbaum, Modern Operating Systems 3 e, (c) 2008 Prentice-Hall, Inc. All rights reserved. 0-13-6006639
Multiprocessor Synchronization (1)
Figure 8-10. The TSL instruction can fail if the bus cannot be locked. These four steps show a sequence of events where the failure is demonstrated.
Figure 8-5. An omega switching network.
Tanenbaum, Modern Operating Systems 3 e, (c) 2008 Prentice-Hall, Inc. All rights reserved. 0-13-6006639
NUMA Multiprocessors (1)
Figure 8-6. (a) A 256-node directory-based multiprocessor.
Tanenbaum, Modern Operating Systems 3 e, (c) 2008 Prentice-Hall, Inc. All rights reserved. 0-13-6006639
Tanenbaum, Modern Operating Systems 3 e, (c) 2008 Prentice-Hall, Inc. All rights reserved. 0-13-6006639
UMA Multiprocessors Using Multistage Switching Networks (2)
Tanenbaum, Modern Operating Systems 3 e, (c) 2008 Prentice-Hall, Inc. All rights reserved. 0-13-6006639
Symmetric Multiprocessors
Figuwk.baidu.come 8-9. The SMP multiprocessor model.
Each CPU Has Its Own Operating System
Figure 8-7. Partitioning multiprocessor memory among four CPUs, but sharing a single copy of the operating system code. The boxes marked Data are the operating system’s private data for each CPU.
UMA Multiprocessors with Bus-Based Architectures
Figure 8-2. Three bus-based multiprocessors. (a) Without caching. (b) With caching. (c) With caching and private memories.
NUMA Multiprocessors (3)
Figure 8-6. (b) Division of a 32-bit memory address into fields. (c) The directory at node 36.
Tanenbaum, Modern Operating Systems 3 e, (c) 2008 Prentice-Hall, Inc. All rights reserved. 0-13-6006639
Multiple Processor Systems
Figure 8-1. (a) A shared-memory multiprocessor. (b) A messagepassing multicomputer. (c) A wide area distributed system.
Tanenbaum, Modern Operating Systems 3 e, (c) 2008 Prentice-Hall, Inc. All rights reserved. 0-13-6006639
access to local memory.
Tanenbaum, Modern Operating Systems 3 e, (c) 2008 Prentice-Hall, Inc. All rights reserved. 0-13-6006639
NUMA Multiprocessors (2)
Characteristics of NUMA machines: 1. There is a single address space visible to all
CPUs. 2. Access to remote memory is via LOAD and
STORE instructions. 3. Access to remote memory is slower than
MODERN OPERATING SYSTEMS
Third Edition ANDREW S. TANENBAUM
Chapter 8 Multiple Processor Systems
Tanenbaum, Modern Operating Systems 3 e, (c) 2008 Prentice-Hall, Inc. All rights reserved. 0-13-6006639