MOS-Ch08-e3 《现代操作系统》Andreww S.Tanenbaum配套课件ppt
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Tanenbaum, Modern Operating Systems 3 e, (c) 2008 Prentice-Hall, Inc. All rights reserved. 0-13-6006639
Master-Slave Multiprocessors
Figure 8-8. A master-slave multiprocessor model.
Characteristics of NUMA machines: 1. There is a single address space visible to all
CPUs. 2. Access to remote memory is via LOAD and
STORE instructions. 3. Access to remote memory is slower than
Tanenbaum, Modern Operating Systems 3 e, (c) 2008 Prentice-Hall, Inc. All rights reserved. 0-13-6006639
Multiprocessor Synchronization (1)
Figure 8-10. The TSL instruction can fail if the bus cannot be locked. These four steps show a sequence of events where the failure is demonstrated.
Tanenbaum, Modern Operating Systems 3 e, (c) 2008 Prentice-Hall, Inc. All rights reserved. 0-13-6006639
Symmetric Multiprocessors
Figure 8-9. The SMP multiprocessor model.
Figure 8-5. An omega switching network.
Tanenbaum, Modern Operating Systems 3 e, (c) 2008 Prentice-Hall, Inc. All rights reserved. 0-13-6006639
NUMA Multiprocessors (1)
Tanenbaum, Modern Operating Systems 3 e, (c) 2008 Prentice-Hall, Inc. All rights reserved. 0-13-6006639
UMA Multiprocessors Using Multistage Switching Networks (2)
access to local memory.
Tanenbaum, Modern Operating Systems 3 e, (c) 2008 Prentice-Hall, Inc. All rights reserved. 0-13-6006639
NUMA Multiprocessors (2)
NUMA Multiprocessors (3)
Figure 8-6. (b) Division of a 32-bit memory address into fields. (c) The directory at node 36.
Tanenbaum, Modern Operating s 3 e, (c) 2008 Prentice-Hall, Inc. All rights reserved. 0-13-6006639
Figure 8-6. (a) A 256-node directory-based multiprocessor.
Tanenbaum, Modern Operating Systems 3 e, (c) 2008 Prentice-Hall, Inc. All rights reserved. 0-13-6006639
Each CPU Has Its Own Operating System
Figure 8-7. Partitioning multiprocessor memory among four CPUs, but sharing a single copy of the operating system code. The boxes marked Data are the operating system’s private data for each CPU.
MODERN OPERATING SYSTEMS
Third Edition ANDREW S. TANENBAUM
Chapter 8 Multiple Processor Systems
Tanenbaum, Modern Operating Systems 3 e, (c) 2008 Prentice-Hall, Inc. All rights reserved. 0-13-6006639
UMA Multiprocessors with Bus-Based Architectures
Figure 8-2. Three bus-based multiprocessors. (a) Without caching. (b) With caching. (c) With caching and private memories.
Multiple Processor Systems
Figure 8-1. (a) A shared-memory multiprocessor. (b) A messagepassing multicomputer. (c) A wide area distributed system.
Tanenbaum, Modern Operating Systems 3 e, (c) 2008 Prentice-Hall, Inc. All rights reserved. 0-13-6006639
Master-Slave Multiprocessors
Figure 8-8. A master-slave multiprocessor model.
Characteristics of NUMA machines: 1. There is a single address space visible to all
CPUs. 2. Access to remote memory is via LOAD and
STORE instructions. 3. Access to remote memory is slower than
Tanenbaum, Modern Operating Systems 3 e, (c) 2008 Prentice-Hall, Inc. All rights reserved. 0-13-6006639
Multiprocessor Synchronization (1)
Figure 8-10. The TSL instruction can fail if the bus cannot be locked. These four steps show a sequence of events where the failure is demonstrated.
Tanenbaum, Modern Operating Systems 3 e, (c) 2008 Prentice-Hall, Inc. All rights reserved. 0-13-6006639
Symmetric Multiprocessors
Figure 8-9. The SMP multiprocessor model.
Figure 8-5. An omega switching network.
Tanenbaum, Modern Operating Systems 3 e, (c) 2008 Prentice-Hall, Inc. All rights reserved. 0-13-6006639
NUMA Multiprocessors (1)
Tanenbaum, Modern Operating Systems 3 e, (c) 2008 Prentice-Hall, Inc. All rights reserved. 0-13-6006639
UMA Multiprocessors Using Multistage Switching Networks (2)
access to local memory.
Tanenbaum, Modern Operating Systems 3 e, (c) 2008 Prentice-Hall, Inc. All rights reserved. 0-13-6006639
NUMA Multiprocessors (2)
NUMA Multiprocessors (3)
Figure 8-6. (b) Division of a 32-bit memory address into fields. (c) The directory at node 36.
Tanenbaum, Modern Operating s 3 e, (c) 2008 Prentice-Hall, Inc. All rights reserved. 0-13-6006639
Figure 8-6. (a) A 256-node directory-based multiprocessor.
Tanenbaum, Modern Operating Systems 3 e, (c) 2008 Prentice-Hall, Inc. All rights reserved. 0-13-6006639
Each CPU Has Its Own Operating System
Figure 8-7. Partitioning multiprocessor memory among four CPUs, but sharing a single copy of the operating system code. The boxes marked Data are the operating system’s private data for each CPU.
MODERN OPERATING SYSTEMS
Third Edition ANDREW S. TANENBAUM
Chapter 8 Multiple Processor Systems
Tanenbaum, Modern Operating Systems 3 e, (c) 2008 Prentice-Hall, Inc. All rights reserved. 0-13-6006639
UMA Multiprocessors with Bus-Based Architectures
Figure 8-2. Three bus-based multiprocessors. (a) Without caching. (b) With caching. (c) With caching and private memories.
Multiple Processor Systems
Figure 8-1. (a) A shared-memory multiprocessor. (b) A messagepassing multicomputer. (c) A wide area distributed system.
Tanenbaum, Modern Operating Systems 3 e, (c) 2008 Prentice-Hall, Inc. All rights reserved. 0-13-6006639