THS4631D,THS4631DGN,THS4631DDA,THS4631DR,THS4631DRE4,THS4631DGN, 规格书,Datasheet 资料

DDA−8D−8λR LPhotodiode CircuitTHS4631SLOS451B –DECEMBER 2004–REVISED AUGUST 2011HIGH-VOLTAGE,HIGH SLEW RATE,WIDEBANDFET-INPUT OPERATIONAL AMPLIFIERCheck for Samples:THS4631FEATURESDESCRIPTIONThe THS4631is a high-speed,FET-input operational •High Bandwidth:amplifier designed for applications requiring wideband –325MHz in Unity Gainoperation,high-input impedance,and high-power –210MHz Gain Bandwidth Product supply voltages.By providing a 210-MHz gain bandwidth product,±15-V supply operation,and •High Slew Rate:100-pA input bias current,the THS4631is capable of –900V/µs (G =2)simultaneous wideband transimpedance gain and –1000V/µs (G =5)large output signal swing.The fast 1000V/µs slew rate allows for fast settling times and good harmonic •Low Distortion of –76dB,SFDR at 5MHz distortion at high frequencies.Low current and •Maximum Input Bias Current:100pA voltage noise allow amplification of extremely •Input Voltage Noise:7nV/√low-level input signals while still maintaining a large signal-to-noise ratio.•Maximum Input Offset Voltage:500µV at 25°C •Low Offset Drift:2.5µV/°C The characteristics of the THS4631make it ideally suited for use as a wideband photodiode amplifier.•Input Impedance:109||3.9pFPhotodiode output current is a prime candidate for •Wide Supply Range:±5V to ±15V transimpedance amplification as shown below.Other •High Output Current:95mApotential applications include test and measurement systems requiring high-input impedance,ADC and APPLICATIONSDAC buffering,high-speed integration,and active filtering.•Wideband Photodiode AmplifierThe THS4631is offered in an 8-pin SOIC (D),and •High-Speed Transimpedance Gain Stage the 8-pin SOIC (DDA)and MSOP (DGN)with •Test and Measurement Systems PowerPAD ™package.•Current-DAC Output Buffer Related FET Input Amplifier Products•Active FilteringSLEW VOLTAGE •High-Speed Signal Integrator V S GBWP MINIMUM DEVICE RATE NOISE (V)(MHz)GAIN(V/µS)(nV/√Hz)•High-Impedance BufferOPA656±523029071OPA657±51600700 4.87OPA627±151655 4.51THS4601±151801005.41Please be aware that an important notice concerning availability,standard warranty,and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.PowerPad is a trademark of Texas Instruments.THS4631SLOS451B–DECEMBER2004–REVISED This integrated circuit can be damaged by ESD.Texas Instruments recommends that all integrated circuits be handled with appropriate precautions.Failure to observe proper handling and installation procedures can cause damage.ESD damage can range from subtle performance degradation to complete device failure.Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.ABSOLUTE MAXIMUM RATINGSover operating free-air temperature range(unless otherwise noted)(1)UNITSV S Supply voltage,V S–to V S+33VV I Input voltage±V SI O(2)Output current150mAContinuous power dissipation See Dissipation Rating Table T J Maximum junction temperature(2)150°CT A Operating free-air temperature,continues operation,long-term reliability(2)125°CT stg Storage temperature range–65°C to150°CHBM1000V ESD ratings:CDM1500VMM100V(1)The absolute maximum ratings under any condition is limited by the constraints of the silicon process.Stresses above these ratings maycause permanent damage.Exposure to absolute maximum conditions for extended periods may degrade device reliability.These are stress ratings only,and functional operation of the device at these or any other conditions beyond those specified is not implied.(2)The maximum junction temperature for continuous operation is limited by package constraints.Operation above this temperature mayresult in reduced reliability and/or lifetime of the device.PACKAGE DISSIPATION RATINGSPOWER RATING(1)(T J=125°C) PACKAGEθJC(°C/W)θJA(°C/W)T A≤25°C T A=85°C D(8)(2)38.395 1.1W0.47WDDA(8)9.245.8 2.3W0.98WDGN(8) 4.758.4 2.14W 1.11W(1)Power rating is determined with a junction temperature of125°C.This is the point where distortion starts to substantially increase.Thermal management of the final PCB should strive to keep the junction temperature at or below125°C for best performance.(2)This data was taken using the JEDEC standard High-K test PCB.RECOMMENDED OPERATING CONDITIONSover operating free-air temperature range(unless otherwise noted)MIN MAX UNITSDual Supply±5±15V S Supply Voltage VSingle Supply1030T A Operating free-air temperature-4085°CV V V S+OUT−THS4631 SLOS451B–DECEMBER2004–REVISED AUGUST2011PACKAGE/ORDERING INFORMATIONPACKAGE DEVICES(1)PACKAGE TYPE SOIC–8TRANSPORT MEDIA,QUANTITY THS4631D Rails,75SOIC–8THS4631DR Tape and Reel,2500THS4631DDA Rails,75SOIC-PP–8(2)THS4631DDAR Tape and Reel,2500THS4631DGN Rails,100MSOP-PP–8(2)THS4631DGNR Tape and Reel,2500(1)For the most current package and ordering information,see the Package Option Addendum at the end of this document,or see the TIwebsite at .(2)PowerPad™is electrically isolated from all other pins.Connection of the PowerPAD to the PCB ground plane is recommended becausethe ground plane is typically the largest copper area on a PCB.However,connection of the PowerPAD to V S-up to V S+is allowed if desired.PIN ASSIGNMENTSTHS4631THS4631SLOS451B –DECEMBER 2004–REVISED AUGUST 2011ELECTRICAL CHARACTERISTICSV S =±15V,R F =499Ω,R L =1k Ω,and G =2(unless otherwise noted)TYPOVER TEMPERATUREPARAMETERTEST CONDITIONS0°C to –40°C to MIN/25°C25°CUNITS70°C85°CMAXAC PERFORMANCEG =1,R F =0Ω,V O =200mV PP325G =2,R F =499Ω,V O =200mV PP 105Small signal bandwidth,-3dBMHzG =5,R F =499Ω,V O =200mV PP 55G =10,R F =499Ω,V O =200mV PP25Gain bandwidth product G >20210MHz 0.1dB bandwidth flatness G =2,R F =499Ω,C F =8.2pF 38MHz Large-signal bandwidth G =2,R F =499Ω,V O =2V PP 105MHz G =2,R F =499Ω,V O =2-V step 550Slew rate G =2,R F =499Ω,V O =10-V step 900V/µs G =5,R F =499Ω,V O =10-V step 1000Rise and fall time 2-V step5ns 0.1%,G =-1,V O =2-V step,C F =4.7pF 40Settling timens 0.01%,G =-1,V O =2-V step,C F =4.7pF190HARMONIC DISTORTION R L =100Ω-65Second harmonic distortion dBc G =2,R L =1k Ω-76V O =2V PP ,R L =100Ω-62f =5MHz Third harmonic distortion dBc R L =1k Ω-94Input voltage noise f >10kHz 7nV/√Hz Input current noise f >10kHz 20fA/√Hz DC PERFORMANCE Open-loop gain R L =1k Ω80706565dB Min Input offset voltage (1)26050016002000µV Max V CM =0V Average offset voltage drift (1)25°C to 85°C ±2.5±10±12±12µV/°C Max Input bias current 5010015002000pA Max V CM =0VInput offset current251007001000pAMaxINPUT CHARACTERISTICS -12.5to Common-mode input range -13to 12-12to 11-9to 11V Min 11.5Common-mode rejection ratio V CM =10V95868080dB MinDifferential input resistance Ω||pF 109||3.9Common-mode input resistance Ω||pF109||3.9OUTPUT CHARACTERISTICS R L =100Ω±11±10±9.5±9.5Output voltage swingV Min R L =1k Ω±13.5±13±12.8±12.8Static output current (sourcing)R L =20Ω98908580mA Min Static output current (sinking)R L =20Ω95858080mA MinClosed loop output impedance G =1,f =1MHz0.1ΩPOWER SUPPLY±15±16.5±16.5±16.5V Max Specified operating voltage ±5±4±4±4V Min Maximum quiescent current 11.5131414mA Max Minimum quiescent current 11.51099mA Min Power supply rejection (PSRR +)V S+=15.5V to 14.5V,V S –=15V 95858080dB Min Power supply rejection (PSRR –)V S+=15V,V S –=-15.5V to -14..5V95858080dBMin(1)Input offset voltage is 100%tested at 25°C.It is specified by characterization and simulation over the listed temperature range.50 C F2 f − Frequency − Hz S i g n a l G a i n − d B100 k1 M 10 M 100 Mf − Frequency − HzS i g n a l G a i n − d Bf − Frequency − HzS i g n a l G a i n − d B012345 f − Frequency − HzS i g n a l G a i n − d Bf − Frequency − HzS i g n a l G a i n − d B12345678f − Frequency − Hz S ig n a l G a i n − d BTHS4631SLOS451B –DECEMBER 2004–REVISED AUGUST 2011TYPICAL CHARACTERISTICS (±15V GRAPHS)T A =25°C,G =2,R F =499Ω,R L =1k Ω,Unless otherwise noted.SMALL SIGNAL FREQUENCYSMALL SIGNAL FREQUENCYRESPONSERESPONSE0.1-dB FLATNESSFigure 1.Figure 2.Figure 3.FREQUENCY RESPONSESMALL SIGNAL FREQUENCYLARGE SIGNAL FREQUENCYvsRESPONSERESPONSECAPACiTIVE LOADFigure 4.Figure 5.Figure 6.-100-95-90-85-80-75-70-65-60-55-500.51 1.52 2.53 3.54H a r m o n i c D i s t o r t i o n - d BV O - Output Voltage Swing - V PP1 M 10 M100 M2n d O r d e r H a r m o n i c D i s t o r t i o n − d Bf − Frequency − Hz-110-100-90-80-70-60-50-40-30f - Frequency - Hz3r d O r d e r H a r m o n i c D i s t o r t i o n - d B−100102030405060708090 f − Frequency − HzO p e n −L o o p G a i n − d BP h a s e −5V O − Output Voltage − V PP S R− S l e w R a t e − V /µs7273747576777879808182−40−30−20−100102030405060708090T C − Case Temperature − °CO p e n -L o o p G a i n − dB− Q u i e s c e n t C u r r e n t − m AI Q V S − Supply Voltage − +Vn V /H zI n p u t V o l t a g e N o i s e −f − Frequency − Hz 0100200300400500600700800I I B − I n p u t B i a s C u r r e n t − p AT A − Free-Air Temperature − °CTHS4631SLOS451B –DECEMBER 2004–REVISED AUGUST 2011TYPICAL CHARACTERISTICS (±15V GRAPHS)(continued)T A =25°C,G =2,R F =499Ω,R L =1k Ω,Unless otherwise noted.SECOND ORDER THIRD ORDERHARMONIC DISTORTIONHARMONIC DISTORTIONHARMONIC DISTORTIONvsvsvsFREQUENCYFREQUENCYOUTPUT VOLTAGE SWINGFigure 7.Figure 8.Figure 9.SLEW RATEOPEN-LOOP GAINOPEN-LOOP GAIN AND PHASEvsvsvsOUTPUT VOLTAGETEMPERATUREFREQUENCYFigure 10.Figure 11.Figure 12.INPUT VOLTAGEQUIESCENT CURRENTINPUT BIAS CURRENTvsvsvsFREQUENCYTEMPERATUREFigure 13.Figure 14.Figure 15.I n p u t O f f s e t V o l t a g e − T A − Free-Air Temperature − °Cm V255075100125150175200225250−40−30−20−100102030405060708090I I O − I n p u t O f f s e t C u r r en t − p AT A − Free-Air Temperature − °C13.213.2513.313.3513.413.4513.513.55− O u t p u t V o l t a g e − |V |V O T C − Case Temperature − °C− O u t p u t V o l t a g e − m VVO −125−100−75−50−25025507510012501020304050607080t − Time− ns1020304050607080t − Time − ns − O u t p u t V o lt a g e − VV O I O − O u t p u t D r i v e C u r r e n t − |m A |T C − Case Temperature − °C-7-5-3-11357t - Time - ns - O u t p u t V o l t a g e - VV O -12-8-4048121062-2-6-10t - Time - ns- O u t p u t V o l t a g e - VVO − O u t p u t V o l t a g e − VV O t − Time− ns THS4631SLOS451B –DECEMBER 2004–REVISED AUGUST 2011TYPICAL CHARACTERISTICS (±15V GRAPHS)(continued)T A =25°C,G =2,R F =499Ω,R L =1k Ω,Unless otherwise noted.INPUT OFFSET CURRENTINPUT OFFSET VOLTAGEOUTPUT VOLTAGEvsvsvsTEMPERATURETEMPERATURETEMPERATUREFigure 16.Figure 17.Figure 18.STATIC OUTPUT DRIVE CURRENTvsSMALL SIGNAL TRANSIENTLARGE SIGNAL TRANSIENTTEMPERATURERESPONSERESPONSEFigure 19.Figure 20.Figure 21.LARGE SIGNAL TRANSIENTLARGE SIGNAL TRANSIENTLARGE SIGNAL TRANSIENTFigure 22.Figure 23.Figure 24.− O u t p u t V o l t a g e − VV O t − Time − ns−3−2.5−2−1.5−1−0.500.511.522.530510152025303540− O u t p u t V o l t a g e − VV O t − Time − nst − Time − m s− O u t p u t V o l t a g e − VV O − I n p u t V o l t a g e − V VI −4−3−2−101234t − Time − m s− O u t p u t V o l t a g e − VV O − I n p u t V o l t a g e − V VI −15−10−551015V ICR − Input Common-Mode Range − V C M R R − C o m m o n -M o d e R e j e c t i o n R a t i o − d Bf − Frequency − HzR e j e c t i o n R a t i o − d B10 M f − Frequency − Hz− O u t p u t I m p e d a n c e −Z o ΩTHS4631SLOS451B –DECEMBER 2004–REVISED AUGUST 2011TYPICAL CHARACTERISTICS (±15V GRAPHS)(continued)T A =25°C,G =2,R F =499Ω,R L =1k Ω,Unless otherwise noted.SETTLING TIMESETTLING TIMEOVERDRIVE RECOVERYFigure 25.Figure 26.Figure MON-MODE REJECTION RATIOREJECTION RATIOvsvsOVERDRIVE RECOVERYINPUT COMMON-MODE RANGEFigure 28.Figure 29.Figure 30.OUTPUT IMPEDANCEvsFREQUENCYFigure 31.λR LPhotodiode CircuitTHS4631SLOS451B –DECEMBER 2004–REVISED AUGUST 2011APPLICATION INFORMATIONThe large gain-bandwidth product of the THS4631INTRODUCTIONprovides the capability for simultaneously achieving both high-transimpedance gain,wide bandwidth,high The THS4631is a high-speed,FET-input operational slw rate,and low noise.In addition,the high-power amplifier.The combination of:high gain bandwidth supply rails provide the potential for a very wide product of 210MHz,high slew rate of 1000V/µs,and dynamic range at the output,allowing for the use of trimmed dc precision makes the device an excellent input sources which possess wide dynamic range.design option for a wide variety of applications,The combination of these characteristics makes the including test and measurement,optical monitoring,THS4631a design option for systems that require transimpedance gain circuits,and high-impedance transimpedance amplification of wideband,low-level buffers.The applications section of the data sheet input signals.A standard transimpedance circuit is discusses these particular applications in addition to shown in Figure 32.general information about the device and its featuresTRANSIMPEDANCE FUNDAMENTALSFET-input amplifiers are often used in transimpedance applications because of their extremely high input impedance.A transimpedance block accepts a current as an input and converts this current to a voltage at the output.The high-input impedance associated with FET-input amplifiers minimizes errors in this process caused by the input bias currents,IIB,of the amplifier.DESIGNING THE TRANSIMPEDANCE Figure 32.Wideband PhotodiodeCIRCUITTransimpedance AmplifierTypically,design of a transimpedance circuit is driven by the characteristics of the current source that As indicated,the current source typically sets the provides the input to the gain block.A photodiode is requirements for gain,speed,and dynamic range of the most common example of a capacitive current the amplifier.For a given amplifier and source source that interfaces with a transimpedance gain combination,achievable performance is dictated by block.Continuing with the photodiode example,the the following parameters:the amplifier system designer traditionally chooses a photodiode gain-bandwidth product,the amplifier input based on two opposing criteria:speed and sensitivity.capacitance,the source capacitance,the Faster photodiodes cause a need for faster gain transimpedance gain,the amplifier slew rate,and the stages,and more sensitive photodiodes require amplifier output swing.From this information,the higher gains in order to develop appreciable signal optimal performance of a transimpedance circuit levels at the output of the gain stage.using a given amplifier is determined.Optimal is These parameters affect the design of the defined here as providing the required transimpedance circuit in a few ways.First,the speed transimpedance gain with a maximized flat frequency of the photodiode signal determines the required response.bandwidth of the gain circuit.Second,the required For the circuit shown in Figure 32,all but one of the gain,based on the sensitivity of the photodiode,limits design parameters is known;the feedback capacitor the bandwidth of the circuit.Third,the larger (C F )must be determined.Proper selection of the capacitance associated with a more sensitive signal feedback capacitor prevents an unstable design,source also detracts from the achievable speed of the controls pulse response characteristics,provides gain block.The dynamic range of the input signal maximized flat transimpedance bandwidth,and limits also places requirements on the amplifier dynamic broadband integrated noise.The maximized flat range.Knowledge of the source output current levels,frequency response results with CF calculated as coupled with a desired voltage swing on the output,shown in Equation 1,where CF is the feedback dictates the value of the feedback resistor,RF.The capacitor,R F is the feedback resistor,CS is the total transfer function from input to output is VOUT =I IN R F .source capacitance (including amplifier input capacitance and parasitic capacitance at the inverting node),and GBP is the gain-bandwidth product of the amplifier in hertz.C F+1p R F G B P)ǒ1p R F G B PǓ2)4C S p R F G B PǸ2F*3dB+G BP2p R F ǒC S )C F ǓǸGainC S = C I(CM) + C I(DIFF) + C P + C DTHS4631SLOS451B –DECEMBER 2004–REVISED AUGUST 2011(1)Once the optimal feedback capacitor has been selected,the transimpedance bandwidth can be calculated with Equation 2.(2)Figure 34.Transimpedance Circuit Bode Plot The performance of the THS4631has been measured for a variety of transimpedance gains with a variety of source capacitances.The achievable bandwidths of the various circuit configurations are summarized numerically in Table 1.The frequency responses are presented in Figure 35,Figure 36,and Figure 37.A.The total source capacitance is the sum of Note that the feedback capacitances do not several distinct capacitances.correspond exactly with the values predicted by the Figure 33.Transimpedance Analysis Circuit equation.They have been tuned to account for the parasitic capacitance of the feedback resistor (typically 0.2pF for 0805surface mount devices)as Where:well as the additional capacitance associated with the C I(CM)is the common-mode input capacitance.PC board.The equation should be used as a starting C I(DIFF)is the differential input capacitance.point for the design,with final values for CF optimized in the laboratory.C D is the diode capacitance.C P is the parasitic capacitance at the inverting node.Table 1.Transimpedance Performance SummaryThe feedback capacitor provides a pole in the noise for Various Configurationsgain of the circuit,counteracting the zero in the noise gain caused by the source capacitance.The pole is SOURCE TRANS-FEEDBACK -3dB CAPACITANCEIMPEDANCE CAPACITANCEFREQUENCYset such that the noise gain achieves a 20-dB per (PF)GAIN (Ω)(PF)(MHZ)decade rate-of-closure with the open-loop gain 1810k 215.8response of the amplifier,resulting in a stable circuit.18100k 0.53As indicated,the formula given provides the feedback 181M 0 1.2capacitance for maximized flat bandwidth.Reduction in the value of the feedback capacitor can increase 4710k 2.28.4the signal bandwidth,but this occurs at the expense 47100k 0.7 2.1of peaking in the ac response.471M 0.20.5210010k 3 5.5100100k 1 1.41001M0.20.376570758085f − Frequency − HzT r a n s i m p e d a n c e G a i n − d BI OV S(s)+12RSǒ1)C1C2Ǔ(Above the Pole Frequency)I O V S (s)+s2R S ǒ1)C1C2Ǔs )12R S ǒC1)C2Ǔ859095100105f − Frequency − HzT r a n s i m p e d a n c e G a i n − d B12R S (C1)C2)12R S ǒ1)C1C2Ǔf − Frequency − HzT r a n s i m p e d a n c e G a i n − d BZ O (s)+C1)C2C1 C2ȧȱȲs )12R SǒC1)C2Ǔs ǒs )12R S C1ǓȧȳȴZ O [1sC2Table 1.Transimpedance Performance Summaryis difficult to measure the frequency response with for Various Configurations (continued)traditional laboratory equipment because the circuit requires a current as an input rather than a voltage.10-k ΩTRANSIMPEDANCE RESPONSESAlso,the capacitance of the current source has a direct effect on the frequency response.A simple interface circuit can be used to emulate a capacitive current source with a network analyzer.With this circuit,trans-impedance bandwidth measurements are simplified,making amplifier evaluation easier and faster.Figure 35.A.The interface network creates a capacitive,100-k ΩTRANSIMPEDANCE RESPONSESconstant current source from a network analyzer and properly terminates the network analyzer at high frequencies.Figure 38.Emulating a Capacitive Current SourceWith a Network Analyzer The transconductance transfer function of theinterface circuit is:(3)The transfer function contains a zero at dc and a poleFigure 36.1-M ΩTRANSIMPEDANCE RESPONSESat:.The transconductance is constantat:,above the pole frequency,providing a controllable ac-current source.This circuit also properly terminates the network analyzer with 50Ωat high frequencies.The second requirement for this current source is to provide the desired output impedance,emulating the output impedance of a photodiode or other current source.The output impedance of this circuit is given by:Figure 37.(4)Assuming C1>>C2,the equation reduces to:MEASURING TRANSIMPEDANCE BANDWIDTH,giving the appearance of a capacitive While there is no substitute for measuring the source at a higher frequency.performance of a particular circuit under the exact conditions that are used in the application,the Capacitor values should be chosen to satisfy two complete system environment often makes requirements.First,C2represents the anticipated measurements harder.For transimpedance circuits,itcapacitance of the true source.Second C1is chosenR EQ +R F 1ǒ1)R F2R F3ǓC λR L1C FEQ +1C F1ǒ1)C F3C F2ǓλR LλR LC such that the corner frequency of the transconductance network is much less than the transimpedance bandwidth of the circuit.Choosing (5)this corner frequency properly leads to more accurate measurements of the transimpedance bandwidth.If the interface circuit corner frequency is too close to the bandwidth of the circuit,determining the power level in the flatband is difficult.A decade or more of flat bandwidth provides a good basis for determining the proper transimpedance bandwidth.ALTERNATIVE TRANSIMPEDANCE CONFIGURATIONSOther transimpedance configurations are possible.Three possibilities are shown below.A.A resistive T-network enables high The first configuration is a slight modification of the transimpedance gain with reasonable basic transimpedance circuit.By splitting the resistor values.feedback resistor,the feedback capacitor value Figure 40.Alternative Transimpedancebecomes more manageable and easier to control.Configuration 2This type of compensation scheme is useful when the feedback capacitor required in the basic configuration The third configuration uses a capacitive T-network to becomes so small that the parasitic effects of the achieve fine control of the compensation capacitance.board and components begin to dominate the total The capacitor CF3can be used to tune the total feedback capacitance.By reducing the resistance effective feedback capacitance to a fine degree.This across the capacitor,the capacitor value can be circuit behaves the same as the basic increased.This mitigates the dominance of the transimpedance configuration,with the effective CF parasitic effects.given by Equation 6.(6)A.Splitting the feedback resistor enables useof a larger,more manageable feedback capacitor.Figure 39.Alternative TransimpedanceConfiguration 1The second configuration uses a resistive T-network A.A capacitive T-network enables fine control to achieve high transimpedance gains using relatively of the effective feedback capacitance using small resistor values.This topology can be useful relatively large capacitor values.when the desired transimpedance gain exceeds the Figure 41.Alternative Transimpedancevalue of available resistors.The transimpedance gain Configuration 3is given by Equation 5.4kT = 1.6E−20Jat 290KE OR E RSE O +ǒE 2NI )ǒI BN R S Ǔ2)4kTR S ǓNG 2)ǒI BI R f Ǔ2)4kTR f NGǸE N +E 2NI )ǒI BN R S Ǔ2)4kTR S )ǒI BI RfNGǓ2)4kTRfNGǸSUMMARY OF KEY DECISIONS IN feedback resistors this large or anticipate using an TRANSIMPEDANCE DESIGNexternal compensation scheme to stabilize the ing a simple capacitor in parallel with the feedback The following is a simplified process for basic resistor makes the amplifier more stable as shown in transimpedance circuit design.This process gives a the Typical Characteristics graphs.start to the design process,though it does ignore some aspects that may be critical to the circuit.NOISE ANALYSISSTEP 1:Determine the capacitance of the source.High slew rate,unity gain stable,voltage-feedback STEP 2:Calculate the total source capacitance,operational amplifiers usually achieve their slew rate including the amplifier input capacitance,C I(CM)at the expense of a higher input noise voltage.The and C I(DIFF).7nV/√Hz input voltage noise for the THS4631is,however,much lower than comparable amplifiers STEP 3:Determine the magnitude of the possiblewhile achieving high slew rates.The input-referred current output from the source,including the voltage noise,and the input-referred current noise minimum signal current anticipated and term,combine to give low output noise under a wide maximum signal current anticipated.variety of operating conditions.Figure 42shows the amplifier noise analysis model with all the noise terms STEP 4:Choose a feedback resistor value such thatincluded.In this model,all noise terms are taken to the input current levels create the desired be noise voltage or current density terms in either output signal voltages,andnV/√or fA/√ensure that the output voltages canaccommodate the dynamic range of the input signal.STEP 5:Calculate the optimum feedbackcapacitance using Equation 1.STEP 6:Calculate the bandwidth given theresulting component values.STEP 7:Evaluate the circuit to determine if all designgoals are satisfied.SELECTION OF FEEDBACK RESISTORSFeedback resistor selection can have a significant Figure 42.Noise Analysis Modeleffect on the performance of the THS4631in a given application,especially in configurations with low closed-loop gain.If the amplifier is configured for The total output noise voltage can be computed as unity gain,the output should be directly connected to the square root of all square output noise voltage the inverting input.Any resistance between these two contributors.Equation 7shows the general form for points interacts with the input capacitance of the the output noise voltage using the terms shown in amplifier and causes an additional pole in the Figure 42.frequency response.For nonunity gain configurations,low resistances are desirable for flat frequency response.However,care must be taken not to load the amplifier too heavily with the feedback network if (7)large output signals are expected.In most cases,a Dividing this expression by the noise gain [NG =(1+trade off is made between the frequency response R f /R g )]gives the equivalent input-referred spot noise characteristics and the loading of the amplifier.For a voltage at the noninverting input,as shown in gain of 2,a 499-Ω f eedback resistor is a suitable Equation 8:operating point from both perspectives.If resistor values are chosen too large,the THS4631is subject to oscillation problems.For example,an inverting amplifier configuration with a 5-k Ωg ain resistor and a 5-k Ωf eedback resistor develops an oscillation due to (8)the interaction of the large resistors with the input Using high resistor values can dominate the total capacitance.In low gain configurations,avoidequivalent input-referred ing a 3-k Ωsource-resistance (R S )value adds a voltage noise term of approximately 7nV/√This is equivalent to the amplifier voltage noise ing higher resistor。