MC1GU256NBCB-0QC00中文资料
金士顿e MMC 5.1嵌入式多媒体卡(e
Embedded Multi-Media Card(e•MMC™ 5.1)EMMC16G-IB29-PE90EMMC32G-IB29-PE90EMMC64G-IB29-PE90v1.0Product Features•Packaged managed NAND flash memory with e•MMC™ 5.1 interface•Backward compatible with all prior e•MMC™ specification revisions•153-ball JEDEC FBGA RoHS Compliant package•Operating voltage range:o VCCQ = 1.8 V/3.3 Vo VCC = 3.3 V•Operating Temperature (T case) - 40C to +85C•Storage Temperature -55C to +85C•Compliant with e•MMC™ 5.1 JEDEC Standard Number JESD84-B51•Factory configured with pseudo Single Level Cell (pSLC) mode for enhanced reliability and performance•Factory configured with reliable writee•MMC™ Specific Feature Support•High-speed e•MMC™ protocol•Variable clock frequencies of 0-200MHz•Ten-wire bus interface (clock, 1 bit command, 8 bit data bus) with an optional hardware reset •Supports three different data bus widths: 1 bit(default), 4 bits, 8 bits•Bus Modes:o Single data transfer rate: up to 52MB/s (using 8 parallel data lines at 52MHz)o Dual data rate mode (DDR-104) : up to 104MB/s @ 52MHzo High speed, single data rate mode (HS-200) : up to 200MB/s @ 200MHzo High speed, dual data rate mode (HS-400) : up to 400MB/s @ 200MHz•Supports alternate boot operation mode to provide a simple boot sequence methodo Supports SLEEP/AWAKE (CMD5)o Host initiated explicit sleep mode for power saving•Enhanced write protection with permanent and partial protection options•Multiple user data partition with enhanced attribute for increased reliability•Error free memory accesso Cyclic Redundancy Code (CRC) for reliable command and data communicationo Internal error correction code (ECC) for improved data storage integrityo Internal enhanced data management algorithmo Data protection for sudden power failure during program operations•Securityo Secure bad block erase commandso Enhanced write protection with permanent and partial protection options•Power off notification for sleep•Field firmware update (FFU)•Production state awareness•Device health report•Command queuing•Enhanced strobe•Cache flushing report•Cache barrier•Background operation control & High Priority Interrupt (HPI)•RPMB throughput improvement•Secure write protection•Pre EOL information•Optimal sizeProduct DescriptionKingston’s e•MMC™ products conform to the JEDEC e•MMC™ 5.1standard. These devices are an ideal universal storage solution for many commercial and industrial applications. In a single integrated packaged device, e•MMC™ combines triple-level cell (TLC) NAND flash memory with an onboard e•MMC™ controller, providing an industry standard interface to the host system. The integrated e•MMC™ controller directly manages NAND flash media which relieves the host processor of these tasks, including flash media error control, wear-leveling, NAND flash management and performance optimization. Future revision to the JEDEC e•MMC™ standard will always maintain backward compatibility. The industry standard interface to the host processor ensures compatibility across future NAND flash generations as well, easing product sustainment throughout the product life cycle. ConfigurationsKingston’s e•MMC™ products support a variety of configurations that allow the e•MMC™ device to be tailored to your specific application needs. The most popular configurations described below are each offered under standard part numbers.Standard TLC – By default the e•MMC™ device is configured with the NAND flash in a standard TLC mode. This configuration provides reasonable performance and reliability for many applications. Pseudo Single Level Cell (pSLC) – The TLC NAND flash in the Kingston e•MMC™ device can be configured to further improve device endurance, data retention, reliability and performance over the standard TLC configuration. This is done by converting the NAND TLC cells to a pseudo single level cell (SLC) configuration. In this configuration, along with the performance and reliability gains, the device capacity is reduced by 2/3 of the capacity. This one-time configuration is achieved by setting the e•MMC™ enhanced attribute for the hardware partition.Kingston e•MMC™ can be ordered preconfigured with the option of reliable write or pSLC at no additional cost. Standard TLC devices can also be one-time configured in-field by following the procedures outlined in the JEDEC e•MMC™ specification. The JEDEC e•MMC™ specification allows for many additional configurations such as up to 4 additional general purpose (GPn) hardware partitions each with the option to support pSLC and reliable write. Additionally, Kingston provides a content loading service that can streamline your product assembly while reducing production costs. For more information, contact your Kingston representative.Kingston e•MMC™ devices are fully compliant with the JEDEC Standard Specification No. JESD84-B51. This datasheet provides technical specifications for Kingston’s family of e•MMC™ devices. Refer to the JEDEC e•MMC™ standard for specific information related to e•MMC™ device function and operation. See: /sites/default/files/docs/JESD84-B51.pdfe•MMC™ Mode and ControllerTLC mode using PS8229 - Leading edge 3D NAND flash technology in TLC mode rated to 3,000 endurance cycles.- Strong data protection with LDPC Error control- Improved data integrity with end-to-end data protection.pSLC mode using PS8229 - Leading edge 3D NAND flash technology in pSLC mode.- Strong data protection with LDPC Error control- Improved data integrity with end-to-end data protection.Part NumberingFigure 1 – Part Number FormatEMMC 16G - xxxx - PE90A B C DPart Number FieldsA: Product Family : EMMCB: Device Capacity : Available capacities of 16GB – 64GBC: Hardware Revision and ConfigurationD: Device Firmware Revision and ConfigurationTable 1 - Device SummaryDevice PerformanceTable 2 below provides sequential read and write speeds for all capacities. Performance numbers can vary under different operating conditions. Values are given at HS400 bus mode. Contact your Kingston Representative for performance numbers using other bus modes.Power ConsumptionDevice current consumption for various device configurations is defined in the power class fields of the EXT_CSD register. Power consumption values are summarized in Table 3 below.Device and Partition CapacityThe device NAND flash capacity is divided across two boot partitions (2048 KB each), a Replay Protected Memory Block (RPMB) partition (512 KB), and the main user storage area. Four additional general purpose storage partitions can be created from the user partition. These partitions can be factory preconfigured or configured in-field by following the procedure outlined in section 6.2 of the JEDEC e•MMC™ specification JESD84-B51. A small portion of the NAND storage capacity is used for the storage of the onboard controller firmware and mapping tables. Additionally, several NAND blocks are held in reserve to boost performance and extend the life of the e•MMC™ device. Table 4 identifies the specific capacity of each partition. This information is reported in the device EXT_CSD register. The contents of this register are also listed in the Appendix.e•MMC™ Bus ModesKingston e•MMC™ devices support all bus modes defined in the JEDEC e•MMC™ 5.1 specification. These modes are summarized in Table 6 below.Signal DescriptionTable 7 - e•MMC™ Signals Name Type DescriptionCLK I Clock: Each cycle of this signal directs a one bit transfer on the command and either a one bit (1x) or a two bits transfer (2x) on all the data lines. The frequency may vary between zero and the maximum clock frequency.DAT[7:0] I/O/PP Data: These are bidirectional data channels. The DAT signals operate in push-pull mode. These bidirectional signals are driven by either the e•MMC™ device or the host controller. By default, after power up or reset, only DAT0 is used for data transfer. A wider data bus can be configured for data transfer, using either DAT0-DAT3 or DAT0-DAT7, by the e•MMC™ host controller. The e•MMC™ device includes internal pull-ups for data lines DAT1-DAT7. Immediately after entering the 4-bit mode, the device disconnects the internal pull ups of lines DAT1, DAT2, and DAT3. Correspondingly, immediately after entering to the 8-bit mode, the device disconnects the internal pull-ups of lines DAT1–DAT7.CMD I/O/PP/OD Command: This signal is a bidirectional command channel used for device initialization and transfer of commands. The CMD signal has two operation modes: open-drain for initialization mode, and push-pull for fast command transfer. Commands are sent from the e•MMC™ host controller to the e•MMC™ device and responses are sent from the device to the host.DS O This signal is generated by the device and used for output in HS400 mode. The frequency of this signal follows the frequency of CLK. For data output each cycle of this signal directs two bits transfer(2x) on the data - one bit for positive edge and the other bit for negative edge. For CRC status response output and CMD response output (enabled only HS400 enhanced strobe mode), the CRC status and CMD Response are latched on the positive edge only, and don't care on the negative edge.RST_n I Hardware Reset: By default, hardware reset is disabled and must be enabled in the EXT_CSD register if used. Otherwise, it can be left un-connected.RFU - Reserved for future use: These pins are not internally connected. Leave floatingNC - Not Connected: These pins are not internally connected. Signals can be routed through these balls to ease printed circuit board design. See Kingston’s Design Guidelines for further details.VSF - Vendor Specific Function: These pins are not internally connectedVddi - Internal Voltage Node: Note that this is not a power supply input. This pin provides access to the output of an internal voltage regulator to allow for the connection of an external Creg capacitor. See Kingston’s Design Guidelines for further details.Vcc S Supply voltage for core Vccq S Supply voltage for I/ODesign GuidelinesDesign guidelines are outlined in a separate document. Contact your Kingston Representative for more information.Package DimensionsFigure 2 – Package DimensionsFigure 3 – Ball Pattern DimensionsBall Assignment (153 ball)Table 8 – Ball Assignment, Top View (HS400)1 2 3 4 5 6 7 8 9 10 11 12 13 14A NC NC DAT0 DAT1 DAT2 Vss RFU NC NC NC NC NC NC NC AB NC DAT3 DAT4 DAT5 DAT6 DAT7 NC NC NC NC NC NC NC NC BC NC Vddi NC Vssq NC Vccq NC NC NC NC NC NC NC NC CD NC NC NC NC NC NC NC DE NC NC NC RFU Vcc Vss VSF VSF VSF NC NC NC EF NC NC NC Vcc VSF NC NC NC FG NC NC RFU Vss VSF NC NC NC GH NC NC NC DS Vss NC NC NC H J NC NC NC Vss Vcc NC NC NC J K NC NC NC RST_n RFU RFU Vss Vcc VSF NC NC NC K L NC NC NC NC NC NC L M NC NC NC Vccq CMD CLK NC NC NC NC NC NC NC NC M N NC Vssq NC Vccq Vssq NC NC NC NC NC NC NC NC NC N P NC NC Vccq Vssq Vccq Vssq RFU NC NC RFU NC NC NC NC P1 2 3 4 5 6 7 8 9 10 11 12 13 14 Note: VSF, RFU and NC balls are not electrically connected. RFU balls may be defined with functionality by the Joint Electron Device Engineering Council (JEDEC) in future revisions of the e•MMC™ standard. Please refer to Kingston’s design guidelines for more info.Device MarkingFigure 4 - EMMC Package Marking240xxxx-xxx.xxxxYYWW PPPPPPPPxxxxxxx-xxxx2xxxxxxTAIWANKingston Logo240xxxx-xxx.xxxx:Internal control numberYYWW:Date code (YY– Last 2 digits ofyear, WW- Work week)PPPPPPPP: Internal control numberxxxxxxx-xxxx Sales P/N2xxxxxx : Internal control numberCountry:TAIWANCard Identification Register (CID)The Card Identification (CID) register is a 128-bit register that contains device identification information used during the e•MMC™ protocol device identification phase. Refer to JEDEC Standard Specification No.JESD84-B51 for details.Field Byte ValueMID [127:120] 0x70reserved [119:114] 0x00CBX [113:112] 0x01OID [111:104] 0x00PNM [103:56 ] IB2916(16G) IB2932(32G) IB2964(64G)PRV [ 55:48 ] 0x90PSN [ 47:16 ] RandomMDT [ 15:8 ] month, yearCRC [ 7:1 ] Follows JEDEC Standard reserved [ 0:0 ] 0x01Card Specific Data Register [CSD]The Card-Specific Data (CSD) register provides information on how to access the contents stored in e•MMC™. The CSD registers are used to define the error correction type, maximum data access time, data transfer speed, data format…etc. For details, refer to section 7.3 of the JEDEC Standard Specification No.JESD84-B51.Field Byte ValueCSD_Structure [127:126] 0x03 (V2.0)SPEC_VER [125:122] 0x04 (V4.0~4.2)reserved [121:120] 0x00TAAC [119:112] 0x4F (40ms)NSAC [111:104] 0x01TRAN_SPEED [103:96 ] 0x32 (26Mbit/s)CCC [ 95:84 ] 0x0F5READ_BL_LEN [ 83:80 ] 0x09 (512 Bytes)READ_BL_PARTIAL [ 79:79 ] 0x00WRITE_BLK_MISALIGN [ 78:78 ] 0x00READ_BLK_MISALIGN [ 77:77 ] 0x00DSR_IMP [ 76:76 ] 0x00reserved [ 75:74 ] 0x00C_SIZE [ 73:62 ] 0xFFFVDD_R_CURR_MIN [ 61:59 ] 0x07 (100mA)VDD_R_CURR_MAX [ 58:56 ] 0x07 (200mA)VDD_W_CURR_MIN [ 55:53 ] 0x07 (100mA)VDD_W_CURR_MAX [ 52:50 ] 0x07 (200mA)C_SIZE_MULT [ 49:47 ] 0x07 (512 Bytes)ERASE_GRP_SIZE [ 46:42 ] 0x1FERASE_GRP_MULT [ 41:37 ] 0x1FWP_GRP_SIZE [ 36:32 ] 0x0FWP_GRP_ENABLE [ 31:31 ] 0x01DEFAULT_ECC [ 30:29 ] 0x00R2W_FACTOR [ 28:26 ] 0x02WRITE_BL_LEN [ 25:22 ] 0x09 (512 Bytes)WRITE_BL_PARTIAL [ 21:21 ] 0x00reserved [ 20:17 ] 0x00CONTENT_PROT_APP [ 16:16 ] 0x00FILE_FORMAT_GRP [ 15:15 ] 0x00COPY [ 14:14 ] 0x00PERM_WRITE_PROTECT [ 13:13 ] 0x00TMP_WRITE_PROTECT [ 12:12 ] 0x00FILE_FORMAT [ 11:10 ] 0x00Field Byte ValueECC [ 9:8 ] 0x00CRC [ 7:1 ] Follow JEDEC Standard reserved [ 0:0 ] 0x01Extended Card Specific Data Register [EXT_CSD]The Extended CSD register defines the Device properties and selected modes. It is 512 bytes long. The most significant 320 bytes are the Properties segment, which defines the Device capabilities and cannot be modified by the host. The lower 192 bytes are the Modes segment, which defines the configuration the Device is working in. These modes can be changed by the host by means of the SWITCH command. For details, refer to section 7.4 of the JEDEC Standard Specification No.JESD84-B51.Field Byte ValueReserved [511:506] 0EXT_SECURITY_ERR [505:505] 0x00S_CMD_SET [504:504] 0x01HPI_FEATURES [503:503] 0x01BKOPS_SUPPORT [502:502] 0x01MAX_PACKED_READS [501:501] 0x3CMAX_PACKED_WRITES [500:500] 0x20DATA_TAG_SUPPORT [499:499] 0x01TAG_UNIT_SIZE [498:498] 0x03TAG_RES_SIZE [497:497] 0x00CONTEXT_CAPABILITIES [496:496] 0x05LARGE_UNIT_SIZE_M1 [495:495] 0x17(16G) 0x2F(32G) 0x5F(64G)EXT_SUPPORT [494:494] 0x03 SUPPORTED_MODES [493:493] 0x01FFU_FEATURES [492:492] 0x00 OPERATION_CODE_TIMEOUT [491:491] 0x00FFU_ARG [490:487] 65535 BARRIER_SUPPORT [486:486] 0x01Reserved [485:309] 0CMDQ_SUPPORT [308:308] 0x01CMDQ_DEPTH [307:307] 0x0FReserved [306:306] 0x00 NUMBER_OF_FW_SECTORS_CORRECTLY_PROGRAMMED [305:302] 0 VENDOR_PROPRIETARY_HEALTH_REPORT [301:270] 0 DEVICE_LIFE_TIME_EST_TYP_B [269:269] 0x01DEVICE_LIFE_TIME_EST_TYP_A [268:268] 0x01PRE_EOL_INFO [267:267] 0x01 OPTIMAL_READ_SIZE [266:266] 0x01OPTIMAL_WRITE_SIZE [265:265] 0x08Field Byte Value OPTIMAL_TRIM_UNIT_SIZE [264:264] 0x01 DEVICE_VERSION [263:262] 0FIRMWARE_VERSION [261:254] 0x90 PWR_CL_DDR_200_360 [253:253] 0x00 CACHE_SIZE [252:249] 1024 GENERIC_CMD6_TIME [248:248] 0x32 POWER_OFF_LONG_TIME [247:247] 0xFF BKOPS_STATUS [246:246] 0x00 CORRECTLY_PRG_SECTORS_NUM [245:242] 0 INI_TIMEOUT_AP [241:241] 0x64 CACHE_FLUSH_POLICY [240:240] 0x01 PWR_CL_DDR_52_360 [239:239] 0x00 PWR_CL_DDR_52_195 [238:238] 0x00PWR_CL_200_195 [237:237] 0x00PWR_CL_200_130 [236:236] 0x00 MIN_PERF_DDR_W_8_52 [235:235] 0x00 MIN_PERF_DDR_R_8_52 [234:234] 0x00 Reserved [233:233] 0x00TRIM_MULT [232:232] 0x11(16G) 0x11(32G) 0x22(64G)SEC_FEATURE_SUPPORT [231:231] 0x55 SEC_ERASE_MULT [230:230] 0xF7 SEC_TRIM_MULT [229:229] 0xF7 BOOT_INFO [228:228] 0x07Reserved [227:227] 0x00 BOOT_SIZE_MULT [226:226] 0x20ACC_SIZE [225:225] 0x07(16G) 0x08(32G) 0x09(64G)HC_ERASE_GRP_SIZE [224:224] 0x01ERASE_TIMEOUT_MULT [223:223] 0x11(16G) 0x11(32G) 0x22(64G)REL_WR_SEC_C [222:222] 0x01HC_WP_GRP_SIZE [221:221] 0x10 S_C_VCC [220:220] 0x08S_C_VCCQ [219:219] 0x08 PRODUCTION_STATE_AWARENESS_TIMEOUT [218:218] 0x14 S_A_TIMEOUT [217:217] 0x15 SLEEP_NOTIFICATION_TIME [216:216] 0x0FField Byte ValueSEC_COUNT [215:212] 10207232 (16G) 20414464 (32G) 40828928 (64G)SECURE_WP_INFO [211:211] 0x01 MIN_PERF_W_8_52 [210:210] 0x08 MIN_PERF_R_8_52 [209:209] 0x08 MIN_PERF_W_8_26_4_52 [208:208] 0x08 MIN_PERF_R_8_26_4_52 [207:207] 0x08 MIN_PERF_W_4_26 [206:206] 0x08 MIN_PERF_R_4_26 [205:205] 0x08 Reserved [204:204] 0x00 PWR_CL_26_360 [203:203] 0x00 PWR_CL_52_360 [202:202] 0x00 PWR_CL_26_195 [201:201] 0x00 PWR_CL_52_195 [200:200] 0x00 PARTITION_SWITCH_TIME [199:199] 0xFF OUT_OF_INTERRUPT_TIME [198:198] 0xFF DRIVER_STRENGTH [197:197] 0x1F DEVICE_TYPE [196:196] 0x57 Reserved [195:195] 0x00 CSD_STRUCTURE [194:194] 0x02 Reserved [193:193] 0x00 EXT_CSD_REV [192:192] 0x08 CMD_SET [191:191] 0x00Reserved [190:190] 0x00 CMD_SET_REV [189:189] 0x00 Reserved [188:188] 0x00 POWER_CLASS [187:187] 0x00 Reserved [186:186] 0x00HS_TIMING [185:185] 0x01 STROBE_SUPPORT [184:184] 0x01 BUS_WIDTH [183:183] 0x02Reserved [182:182] 0x00 ERASED_MEM_CONT [181:181] 0x00 Reserved [180:180] 0x00 PARTITION_CONFIG [179:179] 0x00 BOOT_CONFIG_PROT [178:178] 0x00 BOOT_BUS_CONDITIONS [177:177] 0x00 Reserved [176:176] 0x00 ERASE_GROUP_DEF [175:175] 0x00 BOOT_WP_STATUS [174:174] 0x00C - 4Field Byte Value BOOT_WP [173:173] 0x00 Reserved [172:172] 0x00 USER_WP [171:171] 0x00 Reserved [170:170] 0x00 FW_CONFIG [169:169] 0x00 RPMB_SIZE_MULT [168:168] 0x20 WR_REL_SET [167:167] 0x00 WR_REL_PARAM [166:166] 0x15 SANITIZE_START [165:165] 0x00 BKOPS_START [164:164] 0x00 BKOPS_EN [163:163] 0x00 RST_n_FUNCTION[162:162] 0x00 HPI_MGMT[161:161] 0x00 PARTITIONING_SUPPORT [160:160] 0x07 MAX_ENH_SIZE_MULT [159:157] 623(16G) 1246(32G) 2492(64G) PARTITIONS_ATTRIBUTE[156:156] 0x01 PARTITION_SETTING_COMPLETED[155:155] 0x01 GP_SIZE_MULT_4 [154:152] 0 GP_SIZE_MULT_3 [151:149] 0 GP_SIZE_MULT_2 [148:146] 0 GP_SIZE_MULT_1[145:143] 0 ENH_SIZE_MULT[142:140] 623(16G) 1246(32G) 2492(64G)ENH_START_ADDR[139:136] 0 Reserved[135:135] 0x00 SEC_BAD_BLK_MGMNT[134:134] 0x00 PRODUCTION_STATE_AWARENESS[133:133] 0x00 TCASE_SUPPORT [132:132] 0x00 PERIODIC_WAKEUP[131:131] 0x00 PROGRAM _CID_CSD_DDR_SUPPORT[130:130] 0x01 Reserved[129:128] 0 VENDOR_SPECIFIC_FIELD[127:67 ] 538968064ERROR_CODE [ 66:65 ] 0 ERROR_TYPE[ 64:64 ] 0x00 NATIVE_SECTOR_SIZE [ 63:63 ] 0x00 USE_NATIVE_SECTOR [ 62:62 ] 0x00 DATA_SECTOR_SIZE [ 61:61 ] 0x00 INI_TIMEOUT_EMU[ 60:60 ] 0x00C - 5FieldByte Value CLASS_6_CTRL [ 59:59 ] 0x00 DYNCAP_NEEDED[ 58:58 ] 0x00 EXCEPTION_EVENTS_CTRL [ 57:56 ] 0 EXCEPTION_EVENTS_STATUS [ 55:54 ] 0 EXT_PARTITIONS_ATTRIBUTE[ 53:52 ] 0 CONTEXT_CONF[ 51:37 ] 0 PACKED_COMMAND_STATUS [ 36:36 ] 0x00 PACKED_FAILURE_INDEX [ 35:35 ] 0x00 POWER_OFF_NOTIFICATION[ 34:34 ] 0x00 CACHE_CTRL [ 33:33 ] 0x00 FLUSH_CACHE [ 32:32 ] 0x00 BARRIER_CTRL [ 31:31 ] 0x00 MODE_CONFIG[ 30:30 ] 0x00 MODE_OPERATION_CODES[ 29:29 ] 0x00 Reserved [ 28:27 ] 0 FFU_STATUS[ 26:26 ] 0x00 PRE_LOADING_DATA_SIZE [ 25:22 ] 0MAX_PRE_LOADING_DATA_SIZE[ 21:18 ] 3304106(16G) 6608213(32G) 13216426(64G)PRODUCT_STATE_AWARENESS_ENABLEMENT[ 17:17 ] 0x01 SECURE_REMOVAL_TYPE[ 16:16 ] 0x01 CMDQ_MODE_EN[ 15:15 ] 0x00 Reserved[ 14:0 ]。
PA2561L1-1(NEC)光耦规格书
DATA SHEETThe information in this document is subject to change without notice.©1992Document No. P12989EJ4V0DS00 (4th edition)(Previous No. LC-2225)Date Published August 1997 NS Printed in JapanPHOTOCOUPLERPS2561-1,-2, PS2561L-1,-2HIGH ISOLATION VOLTAGE SINGLE TRANSISTOR TYPE MULTI PHOTOCOUPLER SERIESThe mark shows major revised points.DESCRIPTIONThe PS2561-1, -2 and PS2561L-1, -2 are optically coupled isolators containing a GaAs light emitting diode and an NPN silicon phototransistor.PS2561-1, -2 are in a plastic DIP (Dual In-line Package) and PS2561L-1, -2 are lead bending type (Gull-wing) for surface mount.FEATURES•High isolation voltageBV = 5 000 Vr.m.s.: standard productsBV = 3 750 Vr.m.s.: VDE0884 approved products (Option)•High collector to emitter voltage (V CEO = 80 V)•High current transfer ratio (CTR = 200 % TYP.)•High-speed switching (t r = 3 µs TYP., t f = 5 µs TYP.)•UL approved (File No. E72422 (S) )•CSA approved (No. CA 101391)•BSI approved (BS415, BS7002) No. 7112•SEMKO approved (SS4410165) No. 9317144•NEMKO approved (NEK-HD 195S6) No. A21409•DEMKO approved (Section 101, 137) No. 300535•FIMKO approved (E69-89) No. 167265-08•VDE0884 approved (Option)APPLICATIONS•Power supply •Telephone/FAX.•FA/OA equipment•Programmable logic controller2PACKAGE DIMENSIONS (in millimeters)DIP Type5.1 MAX.6.53.8M A X .4.55M A X .2.8M I N .0.652.547.620.50 ± 0.100.25M4312PS2561-1 (New Package)10.2 MAX.1.25±0.156.53.8M A X .4.55M A X .2.8M I N .0.652.547.620.50 ± 0.100.25M871265340 to 15˚PS2561-20 to 15˚PS2561-14.6 ± 0.351.25±0.156.53.8M A X .4.55M A X .2.8M I N .0.650.50 ± 0.100.25M0 to 15˚7.622.5443121.25±0.15PS2561L1-15.1 MAX.6.53.8M A X .4.25M A X .2.8M I N .0.352.547.620.50 ± 0.100.25M0 to 15˚43121.25±0.1510.161. Anode 2. Cathode 3. Emitter 4. Collector 1, 3. Anode 2, 4. Cathode 5, 7. Emitter 6, 8. Collector1. Anode2. Cathode3. Emitter4. Collector 1. Anode 2. Cathode 3. Emitter 4. Collector Caution New package 1ch only3Lead Bending Type5.1 MAX.6.53.8M A X .2.547.620.25M4312PS2561L-1 (New Package)10.2 MAX.1.25±0.156.53.8M A X .2.547.6287126534PS2561L-2PS2561L-14.6 ± 0.351.25±0.156.53.8M A X .0.25M7.622.5443121.25±0.150.05 t o 0.29.60 ± 0.40.90 ± 0.250.05 t o 0.29.60 ± 0.40.90 ± 0.250.25M0.05 t o 0.29.60 ± 0.40.90 ± 0.255.1 MAX.6.53.8M A X .2.547.620.25MPS2561L2-143121.25±0.150.05 t o 0.210.160.9 ± 0.2512.0 MAX.1. Anode2. Cathode3. Emitter4. Collector1, 3. Anode 2, 4. Cathode 5, 7. Emitter 6, 8. Collector 1. Anode 2. Cathode 3. Emitter 4. Collector 1. Anode 2. Cathode 3. Emitter 4. Collector Caution New package 1ch only4ORDERING INFORMATIONPart NumberPackageSafety Standard ApprovalApplication partnumber *1PS2561-1PS2561L-1PS2561L1-1PS2561L2-14-pin DIP4-pin DIP (lead bending surface mount)4-pin DIP (for long distance)4-pin DIP (for long distance surfacemount)Standard products PS2561-1PS2561-2PS2561L-28-pin DIP8-pin DIP (lead bending surface mount)PS2561-2PS2561-1-V PS2561L-1-V PS2561L1-1-V PS2561L2-1-V 4-pin DIP4-pin DIP (lead bending surface mount)4-pin DIP (for long distance)4-pin DIP (for long distance surfacemount)VDE0884 approved products (Option)PS2561-1PS2561-2-V PS2561L-2-V8-pin DIP8-pin DIP (lead bending surface mount)PS2561-2*1 As applying to Safety Standard, following part number should be used.ABSOLUTE MAXIMUM RATINGS (T A = 25 °C, unless otherwise specified)ParameterSymbolRatingsUnitPS2561-1,PS2561L-1PS2561-2,PS2561L-2DiodeReverse Voltage V R 6V Forward Current (DC)I F80mAPower Dissipation Derating ∆P D /°C 1.5 1.2mW/°C Power Dissipation P D 150120mW/ch Peak Forward Current*1I FP 1A TransistorCollector to Emitter Voltage V CEO 80V Emitter to Collector Voltage V ECO 7V Collector CurrentI C50mA/chPower Dissipation Derating ∆P C /°C 1.5 1.2mW/°C Power DissipationP C 150120mW/ch Isolation Voltage*2BV5 0003 750*3Vr.m.s.Operating Ambient Temperature T A –55 to +100°C Storage TemperatureT stg–55 to +150°C*1PW = 100 µs, Duty Cycle = 1 %*2AC voltage for 1 minute at T A = 25 °C, RH = 60 % between input and output *3VDE0884 approved products (Option)•UL approved •CSA approved •BSI approved•NEMKO approved •DEMKO approved •SEMKO approved•FIMKO approved5ELECTRICAL CHARACTERISTICS (T A = 25 °C)ParameterSymbol Conditions MIN.TYP.MAX.Unit DiodeForward Voltage V F I F = 10 mA 1.171.4VReverse Current I R V R = 5 V5µA Terminal CapacitanceC t V = 0 V, f = 1.0 MHz 50pFTransistorCollector to Emitter Dark CurrentI CEOV CE = 80 V, I F = 0 mA100nACoupled Current Transfer Ratio *1CTR I F = 5 mA, V CE = 5 V 80200400%Collector Saturation VoltageV CE (sat)I F = 10 mA, I C = 2 mA0.3V Isolation Resistance R I-O V I-O = 1.0 kV 1011ΩIsolation Capacitance C I-O V = 0 V, f = 1.0 MHz0.5pFRise Time *2t r V CC = 10 V, I C = 2 mA, R L = 100 Ω3µsFall Time*2t f5*1CTR rank (only PS2561-1, PS2561L-1)*2Test circuit for switching timeL: 200 to 400 (%)M : 80 to 240 (%)D : 100 to 300 (%)H : 80 to 160 (%)W : 130 to 260 (%)V CCV OUTR L = 100 Ω50 ΩI F µPulse InputPW = 100 sDuty Cycle = 1/106TYPICAL CHARACTERISTICS (T A = 25 °C, unless otherwise specified)150100500255075100125150 1.5 mW/˚C1.2 mW/˚C15010050255075100125150010 0001001 000100101755025–25–50V CE = 80 V10 1.00.80.60.40.20510.50.110 m A401.5 mW/˚C1.2 mW/˚C20 m A 50 m A 2 m AI F = 1 mA5 m A 70260504030201004681020 m A I F = 5 mA10m A 50 m A 40 V 24 V 10 V 5 VPS2561-1PS2561L-1PS2561-2PS2561L-2PS2561-1PS2561L-1PS2561-2PS2561L-2100 1.51.41.31.21.11.00.90.80.75010510.50.10 ˚C –25 ˚C –55 ˚C+60 ˚C +25 ˚CT A = +100 ˚CD i o d e P o w e r D i s s i p a t i o n P D (m W )T r a n s i s t o r P o w e r D i s s i p a t i o n P C (m W )Ambient Temperature T A (˚C)F o r w a r d C u r r e n t I F (m A )Forward Voltage V F (V)C o l l e c t o r C u r r e n t I C (m A )Collector to Emitter Voltage V CE (V)C o l l e c t o r t o E m i t t e rD a r k C u r r e n t I CE O (n A )Collector Saturation Voltage V CE(sat) (V)Ambient Temperature T A (˚C)Ambient Temperature T A (˚C)DIODE POWER DISSIPATION vs.AMBIENT TEMPERATURETRANSISTOR POWER DISSIPATION vs. AMBIENT TEMPERATUREFORWARD CURRENT vs.FORWARD VOLTAGECOLLECTOR CURRENT vs.COLLECTOR TO EMITTER VOLTAGECOLLECTOR TO EMITTER DARKCURRENT vs. AMBIENT TEMPERATURECOLLECTOR CURRENT vs.COLLECTOR SATURATION VOLTAGEC o l l e c t o r C u r r e n t I C (m A )7PS2561-1,-2,PS2561L-1,-21.2–501.00.80.60.40.20–252550751004504003503002502001501005000.050.10.5151050501010.110 k5 k 1 k50010050101 000100101100 k50 k 10 k5 k 1 k5001000–5–10–15–200.5125102050100200500I C = 2 mA,V CC = 10 V,CTR = 290 %t f t rt dt sI F = 5 mA,V CC = 5 V,CTR = 290 %t st dt rt fI F = 5 mA,V CE = 5 V100 Ω300 ΩR L = 1 k ΩI F = 5 mA T A = 25 ˚CI F = 5 mA T A = 60 ˚C 1.21.00.80.60.40.2102103104105Normalized to 1.0at T A = 25 ˚C,I F = 5 mA, V CE = 5 VForward Current I F (mA)Ambient Temperature T A (˚C)Load Resistance R L (Ω)Frequency f (kHz)N o r m a l i z e d C u r r e n t T r a n s f e r R a t i o C T RC u r r e n t T r a n s f e r R a t i o C T R (%)N o r m a l i z e d G a i n G VLoad Resistance R L (Ω)S w i t c h i n g T i m e t ( s )µNORMALIZED CURRENT TRANSFER RATIO vs. AMBIENT TEMPERATURECURRENT TRANSFER RATIO vs.FORWARD CURRENTSWITCHING TIME vs.LOAD RESISTANCESWITCHING TIME vs.LOAD RESISTANCEFREQUENCY RESPONSELONG TIME CTR DEGRADATIONS w i t c h i n g T i m e t ( s )µTYP.Time (Hr)C T R (R e l a t i v e V a l u e )8TAPING SPECIFICATIONS (in millimeters)Taping DirectionPS2561L-1-E3PS2561L-1-F3PS2561L-1-E4PS2561L-1-F4Outline and Dimensions (Tape)1.55±0.12.0±0.14.0±0.11.55±0.11.75±0.14.3±0.210.3±0.10.37.5±0.116.0±0.35.6±0.18.0±0.1Outline and Dimensions (Reel)Packing: PS2561L-1-E3, E4 1 000 pcs/reel2.0±0.5R 1.013.0±0.5φ21.0±0.8φ16.4+2.0–0.0P S 2561L -1-E 3, E 4: 250P S 2561L -1-F 3, F 4: 330φ80.0±5.0φφPS2561L-1-F3, F4 2 000 pcs/reel9Taping DirectionPS2561L-2-E3PS2561L-2-E4Outline and Dimensions (Tape)1.55±0.12.0±0.14.0±0.11.55±0.11.75±0.14.3±0.210.3±0.10.37.5±0.116.0±0.310.4±0.112.0±0.1Outline and Dimensions (Reel)Packing: 1 000 pcs/reel16.4+2.0–0.080.0±5.0φ330φ2.0±0.5R 1.013.0±0.5φ21.0±0.8φ10RECOMMENDED SOLDERING CONDITIONS(1) Infrared reflow soldering • Peak reflow temperature235 °C (package surface temperature)• Time of temperature higher than 210 °C 30 seconds or less • Number of reflows Three• FluxRosin flux containing small amount of chlorine (The flux with a maximum chlorine content of 0.2 Wt % is recommended.)60 to 90 s (preheating)210 ˚C120 to 160 ˚CP a c k a g e S u r f a c e T e m p e r a t u r e T (˚C )Time (s)(heating)to 10 sto 30 s235 ˚C (peak temperature)Recommended Temperature Profile of Infrared ReflowPeak temperature 235 ˚C or belowCaution Please avoid to removed the residual flux by water after the first reflow processes.(2) Dip soldering • Temperature 260 °C or below (molten solder temperature)• Time10 seconds or less • Number of times One• FluxRosin flux containing small amount of chlorine (The flux with a maximum chlorine content of 0.2 Wt % is recommended.)11SPECIFICATION OF VDE MARKS LICENSE DOCUMENT (VDE0884)ParameterSymbolSpeckUnitApplication classification (DIN VDE 0109)for rated line voltages ≤ 300 Vr.m.s.for rated line voltages ≤ 600 Vr.m.s.IV III Climatic test class (DIN IEC 68 Teil 1/09.80)55/100/21Dielectric strength maximum operating isolation voltageTest voltage (partial discharge test procedure a for type test and random test)U pr = 1.2 × U IORM , P d < 5 pCU IORM U pr 8901 068V peak V peakTest voltage (partial discharge test procedure b for random test)U pr = 1.6 × U IORM , P d < 5 pC U pr 1 424V peakHighest permissible overvoltage U TR 6 000V peakDegree of pollution (DIN VDE 0109)2Clearance distance > 7.0mm Creepage distance> 7.0mmComparative tracking index (DIN IEC 112/VDE 0303 part 1)CTI 175Material group (DIN VDE 0109)III a Storage temperature range T stg –55 to +150°C Operating temperature rangeT A –55 to +100°C Isolation resistance, minimum value V IO = 500 V dc at T A = 25 °CV IO = 500 V dc at T A MAX. at least 100 °CRis MIN.Ris MIN.10121011ΩΩSafety maximum ratings (maximum permissible in case of fault, see thermal derating curve)Package temperatureCurrent (input current I F , Psi = 0)Power (output or total power dissipation)Isolation resistanceV IO = 500 V dc at T A = 175 °C (Tsi)Tsi Isi Psi Ris MIN.175********9°C mA mW ΩCAUTIONWithin this device there exists GaAs (Gallium Arsenide) material which is aharmful substance if ingested. Please do not under any circumstances break thehermetic seal.No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document.NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others.While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features.NEC devices are classified into the following three quality grades:"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application.Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronicequipment and industrial robotsSpecial: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designedfor life support)Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc.The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance.Anti-radioactive design is not implemented in this product.M4 96. 5。
Eaton Moeller NZM型号熔断器产品说明说明书
Eaton 281306Eaton Moeller series NZM - Molded Case Circuit Breaker. Circuit-breaker, 3p, 100A, H2-M100Allgemeine spezifikationEaton Moeller series NZM molded case circuit breaker thermo-magnetic281306149 mm184 mm 105 mm 2.323 kg RoHS conform IEC/EN 60947 IEC4015082813062NZMH2-M100Product NameCatalog NumberProduct Length/Depth Product Height Product Width Product Weight Compliances Certifications EANModel Code100 AIs the panel builder's responsibility. The specifications for the switchgear must be observed.5 kA130 kAMeets the product standard's requirements.Is the panel builder's responsibility. The specifications for the switchgear must be observed.Built-in device fixed built-in techniqueFixed100 ADoes not apply, since the entire switchgear needs to be evaluated.Max. 10 segments of 24 mm x 0.8 mm at rear-side connection (punched)Min. 2 segements of 16 mm x 0.8 mm at rear-side connection (punched)Max. 10 segments of 16 mm x 0.8 mm at box terminalMax. 8 segments of 24 mm x 1 mm (2x) at box terminal Min. 2 segments of 9 mm x 0.8 mm at box terminalRocker leverMeets the product standard's requirements.40 °C eaton-circuit-breaker-let-through-current-nzm-mccb-characteristic-curve-005.epseaton-circuit-breaker-characteristic-power-defense-mccb-characteristic-curve-037.epsMH2-M100il01206006z2015_11.pdfDas neue digitale NZM-Sortiment - In Kurze verfugbar DE Vorstellung des neuen digitalen Leistungsschalter NZMDA-CD-nzm2_3pDA-CS-nzm2_3peaton-manual-motor-starters-starter-nzm-mccb-wiring-diagram.eps eaton-manual-motor-starters-starter-msc-r-reversing-starter-wiring-diagram.epseaton-nzm-technical-information-sheeteaton-circuit-breaker-nzm-mccb-dimensions-019.epsRated operational current for specified heat dissipation (In) 10.11 Short-circuit ratingRated short-circuit breaking capacity Ics (IEC/EN 60947) at 690 V, 50/60 HzRated short-circuit breaking capacity Icu (IEC/EN 60947) at 400/415 V, 50/60 Hz10.4 Clearances and creepage distances10.12 Electromagnetic compatibilityMounting MethodAmperage Rating10.2.5 LiftingTerminal capacity (copper strip)Handle type10.2.3.1 Verification of thermal stability of enclosuresAmbient storage temperature - min Characteristic curveeCAD model Installationsanleitung Installationsvideos mCAD modelSchaltpläneTechnische Datenblätter ZeichnungenFitted with:Thermal protectionProtection against direct contactFinger and back-of-hand proof to VDE 0106 part 100Terminal capacity (copper busbar)M8 at rear-side screw connectionMax. 24 mm x 8 mm direct at switch rear-side connectionMin. 16 mm x 5 mm direct at switch rear-side connection10.8 Connections for external conductorsIs the panel builder's responsibility.Special featuresMaximum back-up fuse, if the expected short-circuit currents at the installation location exceed the switching capacity of the circuit breaker (Rated short-circuit breaking capacity Icn) Rated current = rated uninterrupted current: 100 A Tripping class 10 A IEC/EN 60947-4-1, IEC/EN 60947-2 The circuit-breaker fulfills all requirements for AC-3 switching category.Ambient operating temperature - max70 °CClimatic proofingDamp heat, constant, to IEC 60068-2-78Damp heat, cyclic, to IEC 60068-2-30Terminal capacity (aluminum stranded conductor/cable)25 mm² - 185 mm² (1x) at tunnel terminal25 mm² - 50 mm² (1x) direct at switch rear-side connection25 mm² - 50 mm² (2x) direct at switch rear-side connectionTerminal capacity (copper stranded conductor/cable)25 mm² - 185 mm² (1x) at 1-hole tunnel terminal25 mm² - 185 mm² (1x) at box terminal25 mm² - 185 mm² (1x) direct at switch rear-side connection25 mm² - 70 mm² (2x) at box terminal25 mm² - 70 mm² (2x) direct at switch rear-side connectionLifespan, electrical5000 operations at 690 V AC-36500 operations at 415 V AC-37500 operations at 690 V AC-110000 operations at 400 V AC-16500 operations at 400 V AC-310000 operations at 415 V AC-1Electrical connection type of main circuitScrew connectionShort-circuit total breaktime< 10 msRated impulse withstand voltage (Uimp) at main contacts8000 VRated short-circuit breaking capacity Ics (IEC/EN 60947) at 400/415 V, 50/60 Hz130 kA10.9.3 Impulse withstand voltageIs the panel builder's responsibility.Utilization categoryA (IEC/EN 60947-2)Number of polesThree-poleAmbient operating temperature - min-25 °C10.6 Incorporation of switching devices and componentsDoes not apply, since the entire switchgear needs to be evaluated.10.5 Protection against electric shockDoes not apply, since the entire switchgear needs to be evaluated.Terminal capacity (control cable)0.75 mm² - 1.5 mm² (2x)0.75 mm² - 2.5 mm² (1x)Equipment heat dissipation, current-dependent25.65 WInstantaneous current setting (Ii) - min800 A10.13 Mechanical functionThe device meets the requirements, provided the information in the instruction leaflet (IL) is observed.10.2.6 Mechanical impactDoes not apply, since the entire switchgear needs to be evaluated.10.9.4 Testing of enclosures made of insulating materialIs the panel builder's responsibility.Rated operational current99 A (400 V AC-3)Rated short-circuit breaking capacity Ics (IEC/EN 60947) at 230 V, 50/60 Hz150 kAApplicationUse in unearthed supply systems at 690 V10.3 Degree of protection of assembliesDoes not apply, since the entire switchgear needs to be evaluated.Rated short-circuit making capacity Icm at 240 V, 50/60 Hz330 kARated short-circuit breaking capacity Ics (IEC/EN 60947) at 440 V, 50/60 Hz130 kADegree of protection (IP), front sideIP40 (with insulating surround)IP66 (with door coupling rotary handle)Rated short-circuit making capacity Icm at 525 V, 50/60 Hz105 kARated short-circuit making capacity Icm at 690 V, 50/60 Hz40 kAInstantaneous current setting (Ii) - max1250 AOverload current setting (Ir) - min80 A10.2.3.2 Verification of resistance of insulating materials to normal heatMeets the product standard's requirements.10.2.3.3 Resist. of insul. mat. to abnormal heat/fire by internal elect. effectsMeets the product standard's requirements.Lifespan, mechanical20000 operationsOverload current setting (Ir) - max100 AVoltage rating690 V - 690 VTerminal capacity (copper solid conductor/cable)6 mm² - 16 mm² (2x) at box terminal10 mm² - 16 mm² (1x) direct at switch rear-side connection6 mm² - 16 mm² (2x) direct at switch rear-side connection16 mm² (1x) at tunnel terminal10 mm² - 16 mm² (1x) at box terminalDegree of protection (terminations)IP00 (terminations, phase isolator and strip terminal)IP10 (tunnel terminal)10.9.2 Power-frequency electric strengthIs the panel builder's responsibility.Short-circuit release non-delayed setting - min800 ADegree of protectionIP20 (basic degree of protection, in the operating controls area) IP20Overvoltage categoryIIIRated short-time withstand current (t = 1 s)1.9 kARated impulse withstand voltage (Uimp) at auxiliary contacts 6000 VTerminal capacity (aluminum solid conductor/cable)10 mm² - 16 mm² (1x) direct at switch rear-side connection10 mm² - 16 mm² (2x) direct at switch rear-side connection16 mm² (1x) at tunnel terminalSwitch off techniqueThermomagneticRated short-time withstand current (t = 0.3 s)1.9 kAAmbient storage temperature - max70 °CRated short-circuit breaking capacity Ics (IEC/EN 60947) at 525 V, 50/60 Hz37.5 kAOptional terminalsBox terminal. Connection on rear. Tunnel terminalRelease systemThermomagnetic releasePollution degree310.7 Internal electrical circuits and connectionsIs the panel builder's responsibility.Rated operating power at AC-3, 230 V30 kW10.10 Temperature riseThe panel builder is responsible for the temperature rise calculation. Eaton will provide heat dissipation data for the devices.FunctionsMotor protectionShort-circuit release non-delayed setting - max1400 AStandard terminalsScrew terminalRated short-circuit making capacity Icm at 400/415 V, 50/60 Hz 330 kARated operating power at AC-3, 400 V55 kWTypeCircuit breaker10.2.2 Corrosion resistanceMeets the product standard's requirements.10.2.4 Resistance to ultra-violet (UV) radiationMeets the product standard's requirements.10.2.7 InscriptionsMeets the product standard's requirements.Rated short-circuit making capacity Icm at 440 V, 50/60 Hz 286 kAIsolation500 V AC (between auxiliary contacts and main contacts)300 V AC (between the auxiliary contacts)Number of operations per hour - max120Circuit breaker frame typeNZM2Direction of incoming supplyAs requiredShock resistance20 g (half-sinusoidal shock 20 ms)Eaton Konzern plc Eaton-Haus30 Pembroke-Straße Dublin 4, Irland © 2023 Eaton. Alle Rechte vorbehalten. Eaton ist eine eingetrageneMarke.Alle anderen Warenzeichen sindEigentum ihrer jeweiligenBesitzer./socialmedia1000 VRated insulation voltage (Ui)。
毛斯(Moxa)UC-8200系列双核ARM Cortex-A7 1GHz IIoT网关产品说明书
UC-8200SeriesArm Cortex-A7dual-core1GHz IIoT gateways with built-in LTE Cat.4,1mini PCIe expansion slot for a Wi-Fi module,1CAN port,4DIs,4DOsFeatures and Benefits•Armv7Cortex-A7dual-core1GHz•ISASecure IEC62443-4-2Security Level2certified with Moxa IndustrialLinux3Secure•Moxa Industrial Linux with10-year superior long-term support•LTE-ready computer with Verizon/AT&T certification and industrial-grade CE/FCC/UL certifications•Dual-SIM slots•2auto-sensing10/100/1000Mbps Ethernet ports•Integrated LTE Cat.4module with US/EU/APAC band support•1CAN port supports CAN2.0A/B•microSD socket for storage expansion•-40to85°C wide temperature range and-40to70°C with LTE enabledCertificationsIntroductionThe UC-8200computing platform is designed for embedded data acquisition applications.The computer comes with dual RS-232/422/485serial ports,dual10/100/1000Mbps Ethernet ports,and one CAN port as well as dual Mini PCIe socket to support Wi-Fi/cellular modules.These versatile capabilities let users efficiently adapt the UC-8200to a variety of complex communications solutions.The UC-8200is built around a Cortex-A7dual core processor that has been optimized for use in energy monitoring systems,but is widely applicable to a variety of industrial solutions.With flexible interfacing options,this tiny embedded computer is a reliable and secure gateway for data acquisition and processing at field sites as well as a useful communications platform for many other large-scale deployments.Wide temperature LTE-enabled models are available for extended temperature applications.All units are thoroughly tested in a testing chamber, guaranteeing that the LTE-enabled computing platforms are suitable for wide-temperature applications.AppearanceUC-8210UC-8220SpecificationsComputerCPU Armv7Cortex-A7dual-core1GHzDRAM2GB DDR3LSupported OS Moxa Industrial Linux1(Debian9,kernel4.4),2027EOLMoxa Industrial Linux31(Debian11,kernel5.10),2031EOLSee /MILStorage Pre-installed8GB eMMCExpansion Slots MicroSD(SD3.0)socket x13OS is selectable via Moxa Computer Configuration System(CCS)for CTO models.For the model names,see the Ordering Information section of thedatasheet PDF file.Computer InterfaceEthernet Ports Auto-sensing10/100/1000Mbps ports(RJ45connector)x2 Serial Ports RS-232/422/485ports x2,software selectable(DB9male) CAN Ports CAN2.0A/B x1(DB9male)Digital Input DIs x4Digital Output DOs x4USB2.0USB2.0hosts x1,type-A connectorsWi-Fi Antenna Connector UC-8220Models:RP-SMA x2Cellular Antenna Connector UC-8220Models:SMA x2GPS Antenna Connector UC-8220Models:SMA x1Expansion Slots UC-8220-T-LX:mPCIe slot x2UC-8220-T-LX US/EU/AP Models:mPCIe slot x1SIM Format UC-8220Models:NanoNumber of SIMs UC-8220Models:2Buttons Programmable buttonTPM TPM v2.0Ethernet InterfaceMagnetic Isolation Protection 1.5kV(built-in)Security FunctionsHardware-based Security TPM2.0Hardware Root of Trust Secure BootIntrusion Detection Host-based Intrusion DetectionSecurity Tools Security Diagnostic ToolSecurity Event AuditingSecure UpdateDisk Protection LUKS Disk EncryptionRecovery One-step recovery to the last known secure stateDual-system design with automatic failbackReliability Network Keep AliveNetwork Failover and FailbackSerial InterfaceBaudrate300bps to921.6kbpsData Bits7,8Stop Bits1,2Parity None,Even,Odd,Space,MarkFlow Control RTS/CTS,XON/XOFFADDC(automatic data direction control)for RS-485RTS Toggle(RS-232only)Console Port1x4-pin header to DB9console portRS-232TxD,RxD,RTS,CTS,DTR,DSR,DCD,GNDRS-422Tx+,Tx-,Rx+,Rx-,GNDRS-485-2w Data+,Data-,GNDCAN InterfaceNo.of Ports1Connector DB9maleBaudrate10to1000kbpsIndustrial Protocols CAN2.0ACAN2.0BIsolation2kV(built-in)Signals CAN_H,CAN_L,CAN_GND,CAN_SHLD,CAN_V+,GNDDigital InputsConnector Screw-fastened Euroblock terminalDry Contact Off:openOn:short to GNDIsolation3K VDCSensor Type Wet contact(NPN)Dry contactWet Contact(DI to COM)On:10to30VDCOff:0to3VDCDigital OutputsConnector Screw-fastened Euroblock terminalCurrent Rating200mA per channelI/O Type SinkVoltage24VDC nominal,open collector to30VDCCellular InterfaceCellular Standards LTE Cat.4Band Options US Models:LTE Band2(1900MHz)/LTE Band4(1700MHz)/LTE Band5(850MHz)/LTE Band13(700MHz)/LTE Band17(700MHz)UMTS/HSPA850MHz/1900MHzCarrier Approval:Verizon,AT&TEU Models:LTE Band1(2100MHz)/LTE Band3(1800MHz)/LTE Band5(850MHz)/LTE Band7(2600MHz)/LTE Band8(900MHz)/LTE Band20(800MHz)UMTS/HSPA850MHz/900MHz/1900MHz/2100MHzAP Models:LTE Band1(2100MHz)/LTE Band3(1800MHz)/LTE Band5(850MHz)/LTE Band7(2600MHz)/LTE Band8(900MHz)/LTE Band28(700MHz)UMTS/HSPA850MHz/900MHz/1900MHz/2100MHzReceiver Types GPS/GLONASS/GalileoState-of-the-art GNSS solutionAccuracy Position:2.0m@CEP50Acquisition Hot starts:1.1secCold starts:29.94secSensitivity Cold starts:-145dBmTracking:-160dBmTime Pulse0.25Hz to10MHzLED IndicatorsSystem Power x2Programmable x1SIM card indicator x1Wireless Signal Strength Cellular/Wi-Fi x6Power ParametersNo.of Power Inputs Redundant dual inputsInput Voltage12to48VDCPower Consumption10WInput Current0.8A@12VDCReliabilityAlert Tools External RTC(real-time clock)Automatic Reboot Trigger External WDT(watchdog timer)Physical CharacteristicsDimensions UC-8220Models:141.5x120x39mm(5.7x4.72x1.54in)UC-8210Models:141.5x120x27mm(5.7x4.72x1.06in)141.5x120x27mm(5.7x4.72x1.06in)Weight UC-8210Models:560g(1.23lb)UC-8220Models:750g(1.65lb)Housing SECCMetalIP Rating IP30Installation DIN-rail mountingWall mounting(with optional kit)Environmental LimitsOperating Temperature-40to70°C(-40to158°F)Storage Temperature(package included)-40to85°C(-40to185°F)Ambient Relative Humidity5to95%(non-condensing)Shock IEC60068-2-27Vibration2Grms@IEC60068-2-64,random wave,5-500Hz,1hr per axis(without USB devicesattached)Standards and CertificationsEMC EN55032/35EN61000-6-2/-6-4EMI CISPR32,FCC Part15B Class AEMS IEC61000-4-2ESD:Contact:4kV;Air:8kVIEC61000-4-3RS:80MHz to1GHz:10V/mIEC61000-4-4EFT:Power:2kV;Signal:1kVIEC61000-4-6CS:10VIEC61000-4-8PFMFIEC61000-4-5Surge:Power:0.5kV;Signal:1kV Industrial Cybersecurity IEC62443-4-1IEC62443-4-2Hazardous Locations Class I Division2ATEXIECExCarrier Approvals VerizonAT&TSafety UL62368-1EN62368-1Green Product RoHS,CRoHS,WEEEMTBFTime UC-8210-T-LX-S:708,581hrsUC-8220-T-LX:650,836hrsUC-8220-T-LX-US-S/EU-S/AP-S:528,574hrs Standards Telcordia(Bellcore)Standard TR/SRWarrantyWarranty Period5yearsDetails See /warrantyPackage ContentsDevice1x UC-8200Series computerDocumentation1x quick installation guide1x warranty cardInstallation Kit1x DIN-rail kit(preinstalled)1x power jack6x M2.5mounting screws for the cellular module Cable1x console cableDimensions UC-8210UC-8220Ordering Information12UC-8210-T-LX-SDefault:MIL1(-Debian9),2027EOLOrder WithModel UC-8210-T-LX-S(CTO):MIL3(Debian11)Secure/Standard,2031EOLWith MIL3Secure1GHzDual CoreBuilt in––-40to85°CUC-8220-T-LXDefault:MIL1(-Debian9),2027EOLOrder WithModel UC-8220-T-LX(CTO):MIL3(Debian11)Secure/Standard,2031EOLWith MIL3Secure1GHzDual CoreBuilt in Reserved Reserved-40to70°CUC-8220-T-LX-US-SDefault:MIL1(-Debian9),2027EOLOrder WithModel UC-8220-T-LX-US-S(CTO):MIL3(Debian11)Secure/Standard,2031EOLWith MIL3Secure1GHzDual CoreBuilt inUS region LTEmodulepreinstalledReserved-40to70°CUC-8220-T-LX-EU-SDefault:MIL1(-Debian9),2027EOLOrder WithModel UC-8220-T-LX-EU-S(CTO):MIL3(Debian11)Secure/Standard,2031EOLWith MIL3Secure1GHzDual CoreBuilt inEurope regionLTE modulepreinstalledReserved-40to70°CUC-8220-T-LX-AP-SDefault:MIL1(-Debian9),2027EOLOrder WithModel UC-8220-T-LX-AP-S(CTO):MIL3(Debian11)Secure/Standard,2031EOLWith MIL3Secure1GHzDual CoreBuilt inAPAC regionLTE modulepreinstalledReserved-40to70°CUC-8210-T-LX-S(CTO)MIL3(Debian11)Secure orStandard,2031EOLWith MIL3Secure1GHzDual CoreBuilt in––-40to85°CUC-8220-T-LX(CTO)MIL3(Debian11)Secure orStandard,2031EOLWith MIL3Secure1GHzDual Core–Reserved Reserved-40to70°CUC-8220-T-LX-US-S (CTO)MIL3(Debian11)Secure orStandard,2031EOLWith MIL3Secure1GHzDual CoreBuilt inUS region LTEmodulepreinstalledReserved-40to70°C12UC-8220-T-LX-EU-S (CTO)MIL3(Debian11)Secure orStandard,2031EOLWith MIL3Secure1GHzDual CoreBuilt inEurope regionLTE modulepreinstalledReserved-40to70°CUC-8220-T-LX-AP-S (CTO)MIL3(Debian11)Secure orStandard,2031EOLWith MIL3Secure1GHzDual CoreBuilt inAPAC regionLTE modulepreinstalledReserved-40to70°CAccessories(sold separately)Power AdaptersPWR-12150-EU-SA-T Locking barrel plug,12VDC,1.5A,100to240VAC,EU plug,-40to75°C operating temperature PWR-12150-UK-SA-T Locking barrel plug,12VDC,1.5A,100to240VAC,UK plug,-40to75°C operating temperature PWR-12150-USJP-SA-T Locking barrel plug,12VDC1.5A,100to240VAC,US/JP plug,-40to75°C operating temperature PWR-12150-AU-SA-T Locking barrel plug,12VDC,1.5A,100to240VAC,AU plug,-40to75°C operating temperature PWR-12150-CN-SA-T Locking barrel plug,12VDC,1.5A,100to240VAC,CN plug,-40to75°C operating temperature Power WiringCBL-PJTB-10Non-locking barrel plug to bare-wire cableCablesCBL-F9DPF1x4-BK-100Console cable with4-pin connector,1mWi-Fi Wireless ModulesUC-8200-WLAN22-AC Wireless package for UC-8200V2.0or later with Wi-Fi module,2screws,2spacers,1heat sink,1pad AntennasANT-LTEUS-ASM-01GSM/GPRS/EDGE/UMTS/HSPA/LTE,1dBi,omnidirectional rubber-duck antennaANT-LTE-ASM-04BK704to960/1710to2620MHz,LTE omnidirectional stick antenna,4.5dBiANT-LTE-OSM-03-3m BK700-2700MHz,multiband antenna,specifically designed for2G,3G,and4G applications,3m cable ANT-LTE-ASM-05BK704-960/1710-2620MHz,LTE stick antenna,5dBiANT-LTE-OSM-06-3m BK MIMO Multiband antenna with screw-fastened mounting option for700-2700/2400-2500/5150-5850MHzfrequenciesANT-WDB-ARM-02022dBi at2.4GHz or2dBi at5GHz,RP-SMA(male),dual-band,omnidirectional antennaDIN-Rail Mounting KitsUC-8210DIN-rail Mounting Kit DIN-rail mounting kit for UC-8210with4M3screwsUC-8220DIN-rail Mounting Kit DIN-rail mounting kit for UC-8220with4M3screwsWall-Mounting KitsUC-8200Wall-mounting Kit Wall-mounting kit for UC-8200with4M3screws©Moxa Inc.All rights reserved.Updated Jul18,2023.This document and any portion thereof may not be reproduced or used in any manner whatsoever without the express written permission of Moxa Inc.Product specifications subject to change without notice.Visit our website for the most up-to-date product information.。
宏碁笔记本的技术参数
品牌宏碁 Acer型号AO531H-0CR颜色靓丽红平台Intel软件操作系统Linpus Linux BE 操作系统处理器CPU类型Atom凌动速度N270(1.60GHz)系统总线533MHz二级缓存512KB芯片组芯片组Intel 945GSE内存内存容量1GB内存类型DDR2 667插槽数量 1 x SO-DIMM最大支持容量2GB硬盘硬盘容量250GB转速5400转/分钟接口类型SATA 串行显卡类型集成显卡显示芯片Intel GMA950显存容量共享系统内存(集成)显示器屏幕尺寸10.1英寸显示比例宽屏物理分辨率1024 x 600屏幕类型LED背光特征丽镜宽屏,支持 Acer CrystalBrite技术光驱光驱类型无光驱通信调制解调器modem 无内置蓝牙无局域网10/100Mbps无线局域网802.11b/g无线模块内置3G 无端口PC卡插槽无USB 3 个IEEE 1394 无音频端口 1 x 麦克风接口; 1 x 音频接口显示端口VGA x 1音效系统扬声器双立体声音箱内置麦克风有输入设备键盘ASOne专用键盘,89%标准尺寸触摸板多触点触控板其它设备网络摄像头有摄像头像素30万指纹识别无读卡器 5 in 1读卡器电源电池3芯锂离子电池续航时间2-3小时, 具体时间视使用环境而定电源适配器100-240V自适应交流电源适配器机器规格尺寸255 (W) x 183 (D) x 19/26.9 (H) mm重量 1 kg(含3芯电池)特性特性描述支持Acer Recovery 还原管理软件电池x1 电源适配器x1 说明书x1本产品全国联保,享受三包服务,质保期为:三年有限质保,全球联保一年;笔记本电脑:整机三包有效期1年。
保修36个月的硬件包括:CPU、内存。
保修24个月的硬件包括:主板、显卡、LCD屏、硬盘、电源适配器、键盘、鼠标模块。
保修12个月的硬件包括:LCD之附件、光驱、DVD、CDR/W、软驱、Modem卡、网卡、摄像头等其余功能模块和部件。
莫加 UC 系列产品说明书
Entry-level Arm-based 64-bit ComputersDual-core, 2-GB RAMCompact Dual-core, 2-GB RAM Built-in LTEValue-added Arm-based 64-bit ComputersQuad-core, 4-GB RAMQuad-core, 4-GB RAM5G/CAN/serial IsolationBuilt-in LTEMoxa Industrial LinuxMoxa's Debian-based industrial-grade stable Linux distribution for long-term projectsFeatures and Benefits5Debian-based distribution that can use all standard Debian packages5Developed as per IEC 62443-4-1 and compliant with IEC 62443-4-2 industrialcybersecurity standards (Moxa Industrial Linux 3 Secure)5Long-term support until 2027 for Moxa Industrial Linux 1 and 2031 for MoxaIndustrial Linux 35Wireless connection management utility with automatic network keep alive andfailover5Ready-to-use APIs and library to ease access to hardware and I/O interfaces5Crash-free robust file system5Over-the air (OTA) software updatesWireless-ready Arm-based 32-bit Computers Built-in cellular or Wi-Fi module, RF type approvals, and carrier approvalsBuilt-in LTE Cat.1Built-in LTECat.1 and Wi-FiBuilt-in LTECat.1 and Wi-FiBuilt-in LTECat.4 with Wi-Fi expansion1. Wireless module is built-in. Refer to the Wireless Connection and Expansion Modules section for details.2. Wireless module must be purchased separately. Refer to the Wireless Connection and Expansion Modules section for details.1 mPCIe for cellular/Wi-Fi1 mPCIe forcellular/Wi-Fi1 mPCIe forcellular/Wi-Fi1 mPCIe forcellular/Wi-Fi1 mPCIe for cellular 1mPCIe for Wi-Fi1 mPCIe forcellular/Wi-FiArm-based 32-bit Computers With Wireless Options Flexibility to add cellular or Wi-Fi capability when needed1. Wireless module must be purchased separately. Refer to the Wireless Connection and Expansion Modules section for details.1 LAN,1 serial2 LAN 2 LAN,2 serial2 LAN,2 serial2 LAN,4 serial2 LAN,4 serial2 LAN,1 serial2 LAN,2 serial3 LAN,8 serialStandard Arm-based 32-bit Computers Low power consumption and small form factorWireless Connectivity and Expansion Modules* Details of cellular and Wi-Fi support with a list of wireless accessory models* Antennas must be purchased separatelyLast updated: Aug. 15, 2023. All specifications are subject to change without notice.。
芝加哥热点6系列60x60厨具,黑色HRG579BB6B说明书
Series 6, Built-in oven with addedsteam function, 60 x 60 cm, BlackHRG579BB6BIncluded accessories2 x combination grid, 1 x universal panOptional accessoriesHEZ317000 Pizza pan, enamelled, HEZ327000 Pizza stone,HEZ333001 Lid for professional pan, HEZ530000 Half tray,HEZ531000 Baking tray, enamelled, HEZ531010 Baking tray,non-stick ceramic coated, HEZ915003 Glass roasting dish, 5,4 L, HEZ532000 Multipurpose pan, enamelled, HEZ532010 Universal pan, non-stick ceramic coated, HEZ533000 Professional pan, enamelled, HEZ538000 1fold telescopic rail, level independent, HEZ629070 Air Fry & Grill tray, HEZ633001 Lid for professional pan, enamelled, HEZ633070 Professional pan, enamelled, HEZ634000 Baking and roasting grid (standard), HEZ636000 Glass pan, HEZ638000 Full ext rails, level independent, HEZ660050 Cover Strip, HEZ664000 Baking and roasting grid (steam)The built-in oven with added steam: achieve delicious baking results thanks to hotair steam heating mode.• AutoPilot 40: every dish is a perfect success thanks to 40 pre-set automatic programmes.• TFT display control: easy-to-use thanks to display with full text and symbols.• Pop-out controls: Make the front of the oven easy to clean and give it a sleek look.• Pyrolytic self-cleaning: Automatically cleans the oven, just wipe out the ash.• Cleaning Assistance: less cleaning effort thanks to the new cleaning option, which can be especially used for cleaning of light soiling.Technical DataInstallation type: ......................................................................Built-in Integrated Cleaning system: ................................Pyrolytic+Hydrolytic Min. required niche size for installation (HxWxD): 585-595 x 560-568 x 550 mmDimensions: ........................................................595 x 594 x 548 mm Dimensions of the packed product (HxWxD): .....675 x 690 x 660 mm Control Panel Material: ..............................................................Glass Door Material: ............................................................................Glass Net weight: ..............................................................................38.6 kg Usable volume of cavity: ...............................................................71 l Cooking method: .......Defrost, Full width grill, Hotair gentle, Hot Air, Intensive heat, Half width grill, Conventional heat, Pizza setting, low temperature cooking, Bottom heat, Hot air grilling, pre-heating, warmingFirst cavity material: ..................................................................Other Oven control: ......................................................................electronic Number of interior lights: .. (1)Length of electrical supply cord: ..........................................120.0 cm EAN code: (4242005332151)Number of cavities (2010/30/EC): (1)Energy efficiency rating: ....................................................................A Energy consumption per cycle conventional (2010/30/EC): ........0.99 kWh/cycleEnergy consumption per cycle forced air convection (2010/30/EC):0.81 kWh/cycleEnergy efficiency index (2010/30/EC): .....................................95.3 % Connection rating: ..................................................................2990 W Fuse protection: ...........................................................................13 A Voltage: ...............................................................................220-240 V Frequency: ...........................................................................50; 60 Hz Plug type: .....................no plug (electrical connection by electrician) Included accessories: .............2 x combination grid, 1 x universal panSeries 6, Built-in oven with addedsteam function, 60 x 60 cm, BlackHRG579BB6BThe built-in oven with added steam: achieve delicious baking results thanks to hotair steam heating mode.Features- Oven with 14 heating methods: 3D Hotair, conventional top and bottom heat, Hotair grilling, full width variable grill, half width grill, pizza function, bottom heat, intensive heat, low temperature cooking, defrost, plate warming, keep warm, Hotair gentle, hot air and steam combined- Temperature range 30 °C - 275 °C- Cavity volume: 71 litre capacityLevel independent telescopic rails- 5 shelf positions- Available as an additional accessoryDesign- Rotary dial, Retractable control dials, round- Extra large capacity oven with grey enamelCleaning- Pyrolytic self-cleaning function- Cleaning Assistance: hydrolyse manual- Full glass inner doorProgrammes/functions- BE54- Electronic clock timer- Digital temperature display with proposal- Actual temperature display Heating-up indicator AutoPilot Automatic start- AutoPilot, 40- Drop down door, SoftClose, SoftOpen- Straight bar handle- Automatic programmes- Fast pre-heating function- Interior halogen light, Light on/off when oven door opened/closed - Water bowl with a volume of 250 ml- Integral cooling fan- Info buttonAccessories- 2 x combination grid, 1 x universal panFeatures- Maximum window temperature 30° C- Low door temperature during pyrolitic cleaning- Electronic door lock- Control panel lock Automatic safety switch off Residual heat indicator Door contact switchTechnical information- 120 cm Cable length- Nominal voltage: 220 - 240 V- Total connected load electric: 2.99 KW - Energy efficiency rating (acc. EU Nr. 65/2014): A- Energy consumption per cycle in conventional mode:0.99 kWh- Energy consumption per cycle in fan-forced convection mode:0.81 kWh- Number of cavities: Main cavity Heat source: electrical Cavity volume:71 litre capacityPerformance/technical information- Appliance dimension (hxwxd): 595 mm x 594 mm x 548 mm- Niche dimension (hxwxd): 585 mm - 595 mm x 560 mm - 568 mm x 550 mm- Please refer to the dimensions provided in the installation manual - We recommend you to choose complementary products within SER6, in order to assure an optimal design combination of your Built-In appliances.。
AT25640B中文资料
Features
• Serial Peripheral Interface (SPI) Compatible • Supports SPI Modes 0 (0,0) and 3 (1,1)
– Datasheet Describes Mode 0 Operation • Low-voltage and Standard-voltage Operation
Output Leakage Input Low-voltage Input High-voltage
VIN = 0V to VCC, TAC = 0°C to 70°C
–3.0 –0.6 VCC x 0.7
3.0
µA
VCC x 0.3
V
VCC + 0.5
V
VOL1 VOH1
Output Low-voltage 4.5V ≤ VCC ≤ 5.5V
2 AT25320B/640B
8535B–SEEPR–7/08
元器件交易网
Figure 0-1. Block Diagram
AT25320B/640B
Table 0-2. Pin Capacitance(1)
Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +5.0V (unless otherwise noted)
Data Protection • Self-timed Write Cycle (5 ms max) • High Reliability
– Endurance: One Million Write Cycles – Data Retention: 100 Years • Automotive Devices Available • 8-lead JEDEC PDIP, 8-lead JEDEC SOIC, 8-lead Ultra Thin Mini-MAP (MLP 2x3), 8-lead TSSOP and 8-lead Ultra Lead Frame Land Grid Array (ULA) Packages • Die Sales: Wafer Form, Tape and Reel, and Bumped Wafers
ATMEGA2561V资料
Features•High Performance, Low Power AVR® 8-Bit Microcontroller •Advanced RISC Architecture–135 Powerful Instructions – Most Single Clock Cycle Execution –32 x 8 General Purpose Working Registers–Fully Static Operation–Up to 16 MIPS Throughput at 16 MHz–On-Chip 2-cycle Multiplier•Non-volatile Program and Data Memories–64K/128K/256K Bytes of In-System Self-Programmable FlashEndurance: 10,000 Write/Erase Cycles–Optional Boot Code Section with Independent Lock BitsIn-System Programming by On-chip Boot ProgramTrue Read-While-Write Operation–4K Bytes EEPROMEndurance: 100,000 Write/Erase Cycles–8K Bytes Internal SRAM–Up to 64K Bytes Optional External Memory Space–Programming Lock for Software Security•JTAG (IEEE std. 1149.1 compliant) Interface–Boundary-scan Capabilities According to the JTAG Standard–Extensive On-chip Debug Support–Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface •Peripheral Features–Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode–Four 16-bit Timer/Counter with Separate Prescaler, Compare- and Capture Mode –Real Time Counter with Separate Oscillator–Four 8-bit PWM Channels–Six/Twelve PWM Channels with Programmable Resolution from 2 to 16 Bits(ATmega1281/2561, ATmega640/1280/2560)–Output Compare Modulator–8/16-channel, 10-bit ADC (ATmega1281/2561, ATmega640/1280/2560)–Two/Four Programmable Serial USART (ATmega1281/2561,ATmega640/1280/2560)–Master/Slave SPI Serial Interface–Byte Oriented 2-wire Serial Interface–Programmable Watchdog Timer with Separate On-chip Oscillator–On-chip Analog Comparator–Interrupt and Wake-up on Pin Change•Special Microcontroller Features–Power-on Reset and Programmable Brown-out Detection–Internal Calibrated Oscillator–External and Internal Interrupt Sources–Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby, and Extended Standby•I/O and Packages–54/86 Programmable I/O Lines (ATmega1281/2561, ATmega640/1280/2560)–64-pad QFN/MLF, 64-lead TQFP (ATmega1281/2561)–100-lead TQFP, 100-ball CBGA (ATmega640/1280/2560)–RoHS/Fully Green•Temperature Range:–-40°C to 85°C Industrial•Ultra-Low Power Consumption–Active Mode: 1 MHz, 1.8V: 510 µA–Power-down Mode: 0.1 µA at 1.8V•Speed Grade (see “Maximum speed vs. VCC” on page 377):–ATmega640V/ATmega1280V/ATmega1281V:0 - 4 MHz @ 1.8 - 5.5V, 0 - 8 MHz @ 2.7 - 5.5V–ATmega2560V/ATmega2561V:0 - 2 MHz @ 1.8 - 5.5V, 0 - 8 MHz @ 2.7 - 5.5V–ATmega640/ATmega1280/ATmega1281:0 - 8 MHz @ 2.7 - 5.5V, 0 - 16 MHz @ 4.5 - 5.5V–ATmega2560/ATmega2561:0 - 16 MHz @ 4.5 - 5.5V 8-bit Microcontroller64K/128K/256K Bytes In-System ProgrammableATmega640/V ATmega1280/V ATmega1281/V2ATmega640/1280/1281/2560/25612549KS–AVR–01/07Pin ConfigurationsFigure 1. TQFP-pinout ATmega640/1280/25603ATmega640/1280/1281/2560/25612549KS–AVR–01/07Figure 2. CBGA-pinout ATmega640/1280/2560Table 1. CBGA-pinout ATmega640/1280/2560.12345678910A G N D AREF PF0PF2PF5PK0PK3PK6G N D VCC B AVCC PG5PF1PF3PF6PK1PK4PK7PA0PA2C PE2PE0PE1PF4PF7PK2PK5PJ7PA1PA3D PE3PE4PE5PE6PH2PA4PA5PA6PA7PG2E PE7PH0PH1PH3PH5PJ6PJ5PJ4PJ3PJ2F VCC PH4PH6PB0PL4PD1PJ1PJ0PC7G N D G G N D PB1PB2PB5PL2PD0PD5PC5PC6VCC H PB3PB4RESET PL1PL3PL7PD4PC4PC3PC2J PH7PG3PB6PL0XT AL2PL6PD3PC1PC0PG1KPB7PG4VCCG N DXT AL1PL5PD2PD6PD7PG04ATmega640/1280/1281/2560/25612549KS–AVR–01/07Figure 3. Pinout ATmega1281/2561N ote:The large center pad underneath the QF N /MLF package is made of metal and internally connected to G N D. It should be soldered or glued to the board to ensure good mechani-cal stability. If the center pad is left unconnected, the package might loosen from the board.DisclaimerTypical values contained in this datasheet are based on simulations and characteriza-tion of other AVR microcontrollers manufactured on the same process technology. Min.and Max values will be available after the device is characterized.5ATmega640/1280/1281/2560/25612549KS–AVR–01/07OverviewThe ATmega640/1280/1281/2560/2561 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega640/1280/1281/2560/2561 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.Block DiagramFigure 4. Block Diagram6ATmega640/1280/1281/2560/25612549KS–AVR–01/07The AVR core combines a rich instruction set with 32 general purpose working registers.All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.The ATmega640/1280/1281/2560/2561 provides the following features: 64K/128K/256K bytes of In-System Programmable Flash with Read-W hile-W rite capabilities, 4K bytes EEPROM, 8K bytes SRAM, 54/86 general purpose I/O lines, 32 general purpose work-ing registers, Real Time Counter (RTC), six flexible Timer/Counters with compare modes and P W M, 4 USARTs, a byte oriented 2-wire Serial Interface, a 16-channel, 10-bit ADC with optional differential input stage with programmable gain, programmable W atchdog Timer with Internal Oscillator, an SPI serial port, IEEE std. 1149.1 compliant JTAG test interface, also used for accessing the On-chip Debug system and program-ming and six software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscilla-tor, disabling all other chip functions until the next interrupt or Hardware Reset. In Power-save mode, the asynchronous timer continues to run, allowing the user to main-tain a timer base while the rest of the device is sleeping. The ADC N oise Reduction mode stops the CPU and all I/O modules except Asynchronous Timer and ADC, to min-imize switching noise during ADC conversions. In Standby mode, the Crystal/Resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low power consumption. In Extended Standby mode, both the main Oscillator and the Asynchronous Timer continue to run.The device is manufactured using Atmel’s high-density nonvolatile memory technology.The On-chip ISP Flash allows the program memory to be reprogrammed in-system through an SPI serial interface, by a conventional nonvolatile memory programmer, or by an On-chip Boot program running on the AVR core. The boot program can use any interface to download the application program in the application Flash memory. Soft-ware in the Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-W hile-W rite operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega640/1280/1281/2560/2561 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications.The ATmega640/1280/1281/2560/2561 AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits.7ATmega640/1280/1281/2560/25612549KS–AVR–01/07Comparison Between ATmega1281/2561 and ATmega640/1280/2560Each device in the ATmega640/1280/1281/2560/2561 family differs only in memory size and number of pins. Table 2 summarizes the different configurations for the six devices.Pin DescriptionsVCC Digital supply voltage.GNDGround.Port A (PA7..PA0)Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running.P o r t A a l s o s e r v e s t h e f u n c t i o n s o f v a r i o u s s p e c i a l f e a t u r e s o f t h e ATmega640/1280/1281/2560/2561 as listed on page 91.Port B (PB7..PB0)Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running.Port B has better driving capabilities than the other ports.P o r t B a l s o s e r v e s t h e f u n c t i o n s o f v a r i o u s s p e c i a l f e a t u r e s o f t h e ATmega640/1280/1281/2560/2561 as listed on page 92.Port C (PC7..PC0)Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running.P o r t C a l s o s e r v e s t h e f u n c t i o n s o f s p e c i a l f e a t u r e s o f t h e ATmega640/1280/1281/2560/2561 as listed on page 95.Port D (PD7..PD0)Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will sourceTable 2. Configuration SummaryDevice Flash EEPROM RAM GeneralPurpose I/O pins16 bits resolution PWM channelsSerial USARTsADC ChannelsA Tmega64064KB 4KB 8KB 8612416A Tmega1280128KB 4KB 8KB 8612416A Tmega1281128KB 4KB 8KB 54628A Tmega2560256KB 4KB 8KB 8612416A Tmega2561256KB4KB8KB546288ATmega640/1280/1281/2560/25612549KS–AVR–01/07current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running.P o r t D a l s o s e r v e s t h e f u n c t i o n s o f v a r i o u s s p e c i a l f e a t u r e s o f t h e ATmega640/1280/1281/2560/2561 as listed on page 97.Port E (PE7..PE0)Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port E output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up resistors are activated. The Port E pins are tri-stated when a reset condition becomes active, even if the clock is not running.P o r t E a l s o s e r v e s t h e f u n c t i o n s o f v a r i o u s s p e c i a l f e a t u r e s o f t h e ATmega640/1280/1281/2560/2561 as listed on page 99.Port F (PF7..PF0)Port F serves as analog inputs to the A/D Converter.Port F also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used.Port pins can provide internal pull-up resistors (selected for each bit). The Port F output buffers have symmetrical drive characteristics with both high sink and source capability.As inputs, Port F pins that are externally pulled low will source current if the pull-up resistors are activated. The Port F pins are tri-stated when a reset condition becomes active, even if the clock is not running. If the JTAG interface is enabled, the pull-up resis-tors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will be activated even if a reset occurs.Port F also serves the functions of the JTAG interface.Port G (PG5..PG0)Port G is a 6-bit I/O port with internal pull-up resistors (selected for each bit). The Port G output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port G pins that are externally pulled low will source current if the pull-up resistors are activated. The Port G pins are tri-stated when a reset condition becomes active, even if the clock is not running.P o r t G a l s o s e r v e s t h e f u n c t i o n s o f v a r i o u s s p e c i a l f e a t u r e s o f t h e ATmega640/1280/1281/2560/2561 as listed on page 105.Port H (PH7..PH0)Port H is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port H output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port H pins that are externally pulled low will source current if the pull-up resistors are activated. The Port H pins are tri-stated when a reset condition becomes active, even if the clock is not running.P o r t H a l s o s e r v e s t h e f u n c t i o n s o f v a r i o u s s p e c i a l f e a t u r e s o f t h e ATmega640/1280/2560 as listed on page 107.Port J (PJ7..PJ0)Port J is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port J output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port J pins that are externally pulled low will source current if the pull-up resistors are activated. The Port J pins are tri-stated when a reset condition becomes active, even if the clock is not running.P o r t J a l s o s e r v e s t h e f u n c t i o n s o f v a r i o u s s p e c i a l f e a t u r e s o f t h e ATmega640/1280/2560 as listed on page 109.Port K (PK7..PK0)Port K serves as analog inputs to the A/D Converter.9ATmega640/1280/1281/2560/25612549KS–AVR–01/07Port K is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port K output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port K pins that are externally pulled low will source current if the pull-up resistors are activated. The Port K pins are tri-stated when a reset condition becomes active, even if the clock is not running.P o r t K a l s o s e r v e s t h e f u n c t i o n s o f v a r i o u s s p e c i a l f e a t u r e s o f t h e ATmega640/1280/2560 as listed on page 111.Port L (PL7..PL0)Port L is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port L output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port L pins that are externally pulled low will source current if the pull-up resistors are activated. The Port L pins are tri-stated when a reset condition becomes active, even if the clock is not running.P o r t L a l s o s e r v e s t h e f u n c t i o n s o f v a r i o u s s p e c i a l f e a t u r e s o f t h e ATmega640/1280/2560 as listed on page 113.Reset input. A low level on this pin for longer than the minimum pulse length will gener-ate a reset, even if the clock is not running. The minimum pulse length is given in Table 26 on page 58. Shorter pulses are not guaranteed to generate a reset.XTAL1Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.XTAL2Output from the inverting Oscillator amplifier.AVCCAVCC is the supply voltage pin for Port F and the A/D Converter. It should be externally connected to V CC , even if the ADC is not used. If the ADC is used, it should be con-nected to V CC through a low-pass filter.AREFThis is the analog reference pin for the A/D Converter.ResourcesA comprehensive set of development tools and application notes, and datasheets are available for download on /avr.10ATmega640/1280/1281/2560/25612549KS–AVR–01/07Register SummaryAddressNameBit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0Page(0x1FF)Reserved --------...Reserved --------(0x13F)Reserved (0x13E)Reserved (0x13D)Reserved (0x13C)Reserved (0x13B)Reserved (0x13A)Reserved (0x139)Reserved (0x138)Reserved (0x137)Reserved (0x136)UDR3 USART3 I/O Data Registerpage 227(0x135)UBRR3H ----USART3 Baud Rate Register High Bytepage 231(0x134)UBRR3L USART3 Baud Rate Register Low Bytepage 231(0x133)Reserved --------(0x132)UCSR3C UMSEL31UMSEL30UPM31UPM30USBS3UCSZ31UCSZ30UCPOL3page 244(0x131)UCSR3B RXCIE3TXCIE3UDRIE3RXE N 3TXE N 3UCSZ32RXB83TXB83page 243(0x130)UCSR3A RXC3TXC3UDRE3FE3DOR3UPE3U2X3MPCM3page 242(0x12F)Reserved --------(0x12E)Reserved --------(0x12D)OCR5CH Timer/Counter5 - Output Compare Register C High Byte page 167(0x12C)OCR5CL Timer/Counter5 - Output Compare Register C Low Byte page 167(0x12B)OCR5BH Timer/Counter5 - Output Compare Register B High Byte page 167(0x12A)OCR5BL Timer/Counter5 - Output Compare Register B Low Byte page 167(0x129)OCR5AH Timer/Counter5 - Output Compare Register A High Byte page 167(0x128)OCR5AL Timer/Counter5 - Output Compare Register A Low Byte page 167(0x127)ICR5H Timer/Counter5 - Input Capture Register High Byte page 168(0x126)ICR5L Timer/Counter5 - Input Capture Register Low Byte page 168(0x125)TC N T5H Timer/Counter5 - Counter Register High Byte page 165(0x124)TC N T5L Timer/Counter5 - Counter Register Low Bytepage 165(0x123)Reserved --------(0x122)TCCR5C FOC5A FOC5B FOC5C-----page 164(0x121)TCCR5B IC N C5ICES5-W GM53W GM52CS52CS51CS50page 162(0x120)TCCR5A COM5A1COM5A0COM5B1COM5B0COM5C1COM5C0W GM51W GM50page 160(0x11F)Reserved --------(0x11E)Reserved --------(0x11D)Reserved --------(0x11C)Reserved --------(0x11B)Reserved --------(0x11A)Reserved --------(0x119)Reserved --------(0x118)Reserved --------(0x117)Reserved --------(0x116)Reserved --------(0x115)Reserved --------(0x114)Reserved --------(0x113)Reserved --------(0x112)Reserved --------(0x111)Reserved --------(0x110)Reserved --------(0x10F)Reserved --------(0x10E)Reserved --------(0x10D)Reserved --------(0x10C)Reserved --------(0x10B)PORTL PORTL7PORTL6PORTL5PORTL4PORTL3PORTL2PORTL1PORTL0page 118(0x10A)DDRL DDL7DDL6DDL5DDL4DDL3DDL2DDL1DDL0page 118(0x109)PI N L PI N L7PI N L6PI N L5PI N L4PI N L3PI N L2PI N L1PI N L0page 118(0x108)PORTK PORTK7PORTK6PORTK5PORTK4PORTK3PORTK2PORTK1PORTK0page 118(0x107)DDRK DDK7DDK6DDK5DDK4DDK3DDK2DDK1DDK0page 118(0x106)PI N K PI N K7PI N K6PI N K5PI N K4PI N K3PI N K2PI N K1PI N K0page 118(0x105)PORTJ PORTJ7PORTJ6PORTJ5PORTJ4PORTJ3PORTJ2PORTJ1PORTJ0page 118(0x104)DDRJ DDJ7DDJ6DDJ5DDJ4DDJ3DDJ2DDJ1DDJ0page 118(0x103)PI N J PI N J7PI N J6PI N J5PI N J4PI N J3PI N J2PI N J1PI N J0page 118(0x102)PORTHPORTH7PORTH6PORTH5PORTH4PORTH3PORTH2PORTH1PORTH0page 117ATmega640/1280/1281/2560/2561Address Name Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0Page(0x101)DDRH DDH7DDH6DDH5DDH4DDH3DDH2DDH1DDH0page 117(0x100)PI N H PI N H7PI N H6PI N H5PI N H4PI N H3PI N H2PI N H1PI N H0page 117 (0xFF)Reserved--------(0xFE)Reserved--------(0xFD)Reserved--------(0xFC)Reserved--------(0xFB)Reserved--------(0xFA)Reserved--------(0xF9)Reserved--------(0xF8)Reserved--------(0xF7)Reserved--------(0xF6)Reserved--------(0xF5)Reserved--------(0xF4)Reserved--------(0xF3)Reserved--------(0xF2)Reserved--------(0xF1)Reserved--------(0xF0)Reserved--------(0xEF)Reserved--------(0xEE)Reserved--------(0xED)Reserved--------(0xEC)Reserved--------(0xEB)Reserved-------(0xEA)Reserved--------(0xE9)Reserved--------(0xE8)Reserved--------(0xE7)Reserved-------(0xE6)Reserved--------(0xE5)Reserved--------(0xE4)Reserved--------(0xE3)Reserved-------(0xE2)Reserved--------(0xE1)Reserved-------(0xE0)Reserved-------(0xDF)Reserved--------(0xDE)Reserved--------(0xDD)Reserved-------(0xDC)Reserved--------(0xDB)Reserved--------(0xDA)Reserved--------(0xD9)Reserved-------(0xD8)Reserved--------(0xD7)Reserved--------(0xD6)UDR2 USART2 I/O Data Register page 227 (0xD5)UBRR2H----USART2 Baud Rate Register High Byte page 231 (0xD4)UBRR2L USART2 Baud Rate Register Low Byte page 231 (0xD3)Reserved--------(0xD2)UCSR2C UMSEL21UMSEL20UPM21UPM20USBS2UCSZ21UCSZ20UCPOL2page 244 (0xD1)UCSR2B RXCIE2TXCIE2UDRIE2RXE N2TXE N2UCSZ22RXB82TXB82page 243 (0xD0)UCSR2A RXC2TXC2UDRE2FE2DOR2UPE2U2X2MPCM2page 242 (0xCF)Reserved--------(0xCE)UDR1 USART1 I/O Data Register page 227 (0xCD)UBRR1H----USART1 Baud Rate Register High Byte page 231 (0xCC)UBRR1L USART1 Baud Rate Register Low Byte page 231 (0xCB)Reserved--------(0xCA)UCSR1C UMSEL11UMSEL10UPM11UPM10USBS1UCSZ11UCSZ10UCPOL1page 244 (0xC9)UCSR1B RXCIE1TXCIE1UDRIE1RXE N1TXE N1UCSZ12RXB81TXB81page 243 (0xC8)UCSR1A RXC1TXC1UDRE1FE1DOR1UPE1U2X1MPCM1page 242 (0xC7)Reserved--------(0xC6)UDR0 USART0 I/O Data Register page 227 (0xC5)UBRR0H----USART0 Baud Rate Register High Byte page 231 (0xC4)UBRR0L USART0 Baud Rate Register Low Byte page 231 (0xC3)Reserved--------(0xC2)UCSR0C UMSEL01UMSEL00UPM01UPM00USBS0UCSZ01UCSZ00UCPOL0page 244 (0xC1)UCSR0B RXCIE0TXCIE0UDRIE0RXE N0TXE N0UCSZ02RXB80TXB80page 243 (0xC0)UCSR0A RXC0TXC0UDRE0FE0DOR0UPE0U2X0MPCM0page 243Address Name Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0Page (0xBF)Reserved--------(0xBE)Reserved--------(0xBD)T W AMR T W AM6T W AM5T W AM4T W AM3T W AM2T W AM1T W AM0-page 274 (0xBC)T W CR T W I N T T W EA T W STA T W STO T WW C T W E N-T W IE page 271 (0xBB)T W DR 2-wire Serial Interface Data Register page 273 (0xBA)T W AR T W A6T W A5T W A4T W A3T W A2T W A1T W A0T W GCE page 273 (0xB9)T W SR T W S7T W S6T W S5T W S4T W S3-T W PS1T W PS0page 272 (0xB8)T W BR2-wire Serial Interface Bit Rate Register page 271 (0xB7)Reserved--------(0xB6)ASSR-EXCLK AS2TC N2UB OCR2AUB OCR2BUB TCR2AUB TCR2BUB page 188 (0xB5)Reserved--------(0xB4)OCR2B Timer/Counter2 Output Compare Register B page 195 (0xB3)OCR2A Timer/Counter2 Output Compare Register A page 195 (0xB2)TC N T2 Timer/Counter2 (8 Bit)page 195 (0xB1)TCCR2B FOC2A FOC2B--W GM22CS22CS21CS20page 194 (0xB0)TCCR2A COM2A1COM2A0COM2B1COM2B0--W GM21W GM20page 195 (0xAF)Reserved--------(0xAE)Reserved--------(0xAD)OCR4CH Timer/Counter4 - Output Compare Register C High Byte page 167 (0xAC)OCR4CL Timer/Counter4 - Output Compare Register C Low Byte page 167 (0xAB)OCR4BH Timer/Counter4 - Output Compare Register B High Byte page 166 (0xAA)OCR4BL Timer/Counter4 - Output Compare Register B Low Byte page 166 (0xA9)OCR4AH Timer/Counter4 - Output Compare Register A High Byte page 166 (0xA8)OCR4AL Timer/Counter4 - Output Compare Register A Low Byte page 166 (0xA7)ICR4H Timer/Counter4 - Input Capture Register High Byte page 168 (0xA6)ICR4L Timer/Counter4 - Input Capture Register Low Byte page 168 (0xA5)TC N T4H Timer/Counter4 - Counter Register High Byte page 165 (0xA4)TC N T4L Timer/Counter4 - Counter Register Low Byte page 165 (0xA3)Reserved--------(0xA2)TCCR4C FOC4A FOC4B FOC4C-----page 164 (0xA1)TCCR4B IC N C4ICES4-W GM43W GM42CS42CS41CS40page 162 (0xA0)TCCR4A COM4A1COM4A0COM4B1COM4B0COM4C1COM4C0W GM41W GM40page 160 (0x9F)Reserved--------(0x9E)Reserved--------(0x9D)OCR3CH Timer/Counter3 - Output Compare Register C High Byte page 166 (0x9C)OCR3CL Timer/Counter3 - Output Compare Register C Low Byte page 166 (0x9B)OCR3BH Timer/Counter3 - Output Compare Register B High Byte page 166 (0x9A)OCR3BL Timer/Counter3 - Output Compare Register B Low Byte page 166 (0x99)OCR3AH Timer/Counter3 - Output Compare Register A High Byte page 166 (0x98)OCR3AL Timer/Counter3 - Output Compare Register A Low Byte page 166 (0x97)ICR3H Timer/Counter3 - Input Capture Register High Byte page 168 (0x96)ICR3L Timer/Counter3 - Input Capture Register Low Byte page 168 (0x95)TC N T3H Timer/Counter3 - Counter Register High Byte page 165 (0x94)TC N T3L Timer/Counter3 - Counter Register Low Byte page 165 (0x93)Reserved--------(0x92)TCCR3C FOC3A FOC3B FOC3C-----page 164 (0x91)TCCR3B IC N C3ICES3-W GM33W GM32CS32CS31CS30page 162 (0x90)TCCR3A COM3A1COM3A0COM3B1COM3B0COM3C1COM3C0W GM31W GM30page 160 (0x8F)Reserved--------(0x8E)Reserved--------(0x8D)OCR1CH Timer/Counter1 - Output Compare Register C High Byte page 166 (0x8C)OCR1CL Timer/Counter1 - Output Compare Register C Low Byte page 166 (0x8B)OCR1BH Timer/Counter1 - Output Compare Register B High Byte page 166 (0x8A)OCR1BL Timer/Counter1 - Output Compare Register B Low Byte page 166 (0x89)OCR1AH Timer/Counter1 - Output Compare Register A High Byte page 166 (0x88)OCR1AL Timer/Counter1 - Output Compare Register A Low Byte page 166 (0x87)ICR1H Timer/Counter1 - Input Capture Register High Byte page 168 (0x86)ICR1L Timer/Counter1 - Input Capture Register Low Byte page 168 (0x85)TC N T1H Timer/Counter1 - Counter Register High Byte page 165 (0x84)TC N T1L Timer/Counter1 - Counter Register Low Byte page 165 (0x83)Reserved--------(0x82)TCCR1C FOC1A FOC1B FOC1C-----page 164 (0x81)TCCR1B IC N C1ICES1-W GM13W GM12CS12CS11CS10page 162 (0x80)TCCR1A COM1A1COM1A0COM1B1COM1B0COM1C1COM1C0W GM11W GM10page 160 (0x7F)DIDR1------AI N1D AI N0D page 278 (0x7E)DIDR0ADC7D ADC6D ADC5D ADC4D ADC3D ADC2D ADC1D ADC0D page 300ATmega640/1280/1281/2560/2561Address Name Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0Page (0x7D)DIDR2ADC15D ADC14D ADC13D ADC12D ADC11D ADC10D ADC9D ADC8D page 300 (0x7C)ADMUX REFS1REFS0ADLAR MUX4MUX3MUX2MUX1MUX0page 294 (0x7B)ADCSRB-ACME--MUX5ADTS2ADTS1ADTS0page 277,295,,299 (0x7A)ADCSRA ADE N ADSC ADATE ADIF ADIE ADPS2ADPS1ADPS0page 297 (0x79)ADCH ADC Data Register High byte page 298 (0x78)ADCL ADC Data Register Low byte page 298 (0x77)Reserved--------(0x76)Reserved--------(0x75)XMCRB XMBK----XMM2XMM1XMM0page 36 (0x74)XMCRA SRE SRL2SRL1SRL0SR W11SR W10SR W01SR W00page 34 (0x73)TIMSK5--ICIE5-OCIE5C OCIE5B OCIE5A TOIE5page 169 (0x72)TIMSK4--ICIE4-OCIE4C OCIE4B OCIE4A TOIE4page 169 (0x71)TIMSK3--ICIE3-OCIE3C OCIE3B OCIE3A TOIE3page 169 (0x70)TIMSK2-----OCIE2B OCIE2A TOIE2page 197 (0x6F)TIMSK1--ICIE1-OCIE1C OCIE1B OCIE1A TOIE1page 169 (0x6E)TIMSK0-----OCIE0B OCIE0A TOIE0page 135 (0x6D)PCMSK2PCI N T23PCI N T22PCI N T21PCI N T20PCI N T19PCI N T18PCI N T17PCI N T16page 81 (0x6C)PCMSK1PCI N T15PCI N T14PCI N T13PCI N T12PCI N T11PCI N T10PCI N T9PCI N T8page 81 (0x6B)PCMSK0PCI N T7PCI N T6PCI N T5PCI N T4PCI N T3PCI N T2PCI N T1PCI N T0page 82 (0x6A)EICRB ISC71ISC70ISC61ISC60ISC51ISC50ISC41ISC40page 79 (0x69)EICRA ISC31ISC30ISC21ISC20ISC11ISC10ISC01ISC00page 78 (0x68)PCICR-----PCIE2PCIE1PCIE0page 80 (0x67)Reserved--------(0x66)OSCCAL Oscillator Calibration Register page 48 (0x65)PRR1--PRTIM5PRTIM4PRTIM3PRUSART3PRUSART2PRUSART1page 56 (0x64)PRR0PRT W I PRTIM2PRTIM0-PRTIM1PRSPI PRUSART0PRADC page 55 (0x63)Reserved--------(0x62)Reserved--------(0x61)CLKPR CLKPCE---CLKPS3CLKPS2CLKPS1CLKPS0page 48 (0x60)W DTCSR W DIF W DIE W DP3W DCE W DE W DP2W DP1W DP0page 660x3F (0x5F)SREG I T H S V N Z C page 120x3E (0x5E)SPH SP15SP14SP13SP12SP11SP10SP9SP8page 140x3D (0x5D)SPL SP7SP6SP5SP4SP3SP2SP1SP0page 140x3C (0x5C)EI N D-------EI N D0page 150x3B (0x5B)RAMPZ------RAMPZ1RAMPZ0page 150x3A (0x5A)Reserved--------0x39 (0x59)Reserved--------0x38 (0x58)Reserved--------0x37 (0x57)SPMCSR SPMIE R WW SB SIGRD R WW SRE BLBSET PG W RT PGERS SPME N page 3400x36 (0x56)Reserved--------0x35 (0x55)MCUCR JTD--PUD--IVSEL IVCE page 66,76,115,3140x34 (0x54)MCUSR---JTRF W DRF BORF EXTRF PORF page 3140x33 (0x53)SMCR----SM2SM1SM0SE page 510x32 (0x52)Reserved--------0x31 (0x51)OCDR OCDR7OCDR6OCDR5OCDR4OCDR3OCDR2OCDR1OCDR0page 3070x30 (0x50)ACSR ACD ACBG ACO ACI ACIE ACIC ACIS1ACIS0page 2770x2F (0x4F)Reserved--------0x2E (0x4E)SPDR SPI Data Register page 2080x2D (0x4D)SPSR SPIF W COL-----SPI2X page 2070x2C (0x4C)SPCR SPIE SPE DORD MSTR CPOL CPHA SPR1SPR0page 2060x2B (0x4B)GPIOR2General Purpose I/O Register 2page 340x2A (0x4A)GPIOR1General Purpose I/O Register 1page 340x29 (0x49)Reserved--------0x28 (0x48)OCR0B Timer/Counter0 Output Compare Register B page 1340x27 (0x47)OCR0A Timer/Counter0 Output Compare Register A page 1340x26 (0x46)TC N T0 Timer/Counter0 (8 Bit)page 1340x25 (0x45)TCCR0B FOC0A FOC0B--W GM02CS02CS01CS00page 1330x24 (0x44)TCCR0A COM0A1COM0A0COM0B1COM0B0--W GM01W GM00page 1300x23 (0x43)GTCCR TSM-----PSRASY PSRSY N C page 173, 1980x22 (0x42)EEARH----EEPROM Address Register High Byte page 320x21 (0x41)EEARL EEPROM Address Register Low Byte page 320x20 (0x40)EEDR EEPROM Data Register page 320x1F (0x3F)EECR--EEPM1EEPM0EERIE EEMPE EEPE EERE page 320x1E (0x3E)GPIOR0General Purpose I/O Register 0page 340x1D (0x3D)EIMSK I N T7I N T6I N T5I N T4I N T3I N T2I N T1I N T0page 790x1C (0x3C)EIFR I N TF7I N TF6I N TF5I N TF4I N TF3I N TF2I N TF1I N TF0page 80。
HMC200-256盒式AC产品手册 V2.0
HMC200-256小容量AC 产品手册北京汉铭通信有限公司2010年8月手册说明本文档用于介绍HMC200-256小容量AC的外观、规格及配件。
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目标读者本文档的目标读者为合作伙伴、代理商的技术支持人员及工程调试人员。
内容简介本文档各章节内容如下。
1产品概述 (4)1.1 产品简介 (4)1.2 产品特点 (4)2产品外观、接口及配件 (6)2.1 产品外观 (6)2.2 产品接口 (6)2.3 产品配件清单 (8)3产品规格参数 (9)3.1 硬件规格 (9)3.2 技术参数 (10)1 产品概述1.1 产品简介HMC200-256小容量AC(AC,Access Controller,接入控制器)是本公司自主开发的高可靠、高性能的无线接入控制器产品,具备功能全面、性能稳定、业务丰富等特点,提供强大的WLAN接入管理与控制能力,提供VLAN、Qos、DHCP等业务支持能力,提供用户接入管理与控制能力,支持用户漫游及切换等功能,支持鉴权与记费用接口。
HMC200-256采用了集成的软硬件一体化设计,与本公司的系列无线接入点设备(AP,Access Point)产品配套使用,支持最多256线AP接入与管理,支持4K个用户接入网络,支持最大512Mbps的数据吞吐量。
1.2 产品特点●集中的无线网络管理HMC200系列AC可以根据容量需求独立部署,也可以与GM200网管平台配套部署,提供电信级的网络管理,可以对AP进行管理,也可以对用户进行管理,简化了运营网络的部署和维护。
●集中的无线网络安全无线网络安全支持WEP/WPA/WAP2/802.1x方式,支持无线IPS/IDS,支持二层用户的隔离,支持集中的ACL控制。
支持多种认证方式:支持802.1x认证,支持MAC地址认证,Portal认证,PPPoE认证与WAPI方式认证。
支持非法AP检测及后续处理,支持无线攻击防御,支持静态黑白名单,减少非法用户对无线网络冲击。
XGB系列产品说明书
No. NameDescriptions① LED IndicatorsShows the operation status②RS-232C Connector The connector for external connection③ RS-422/RS-485 ConnectorThe connector for external connectionNo. Switch status Switch status descriptions④All on Normal operatingAll off OS Download Mode (If you want to OS Download, Please contact us)LED NameLED Descriptions LED status LED status descriptions On Normal operating(a) How to connect RS-232C connector to the external modemCnet I/F module can communicate with devices of long distance through a modem at this time modem and channel RS-232C must be connected as shown in below tableCnet(9-PIN) Connection No. and Signal DirectionModem Pin No. Name Name 1 CDCD 2 RXD RXD 3 TXD TXD 4 DTR DTR 5 SG SG 6 DSR DSR 7 RTS RTS 8 CTS CTS 9 RI RI(b) How to connect RS-232C connector in null modem mode.In null modem mode, connector is able to be connected in 3-line (without handshake) type. Cnet(9-PIN) Connection No. and Signal DirectionComputer /Communicationdevice Pin No. Name Name 1 CDCD 2 RXD RXD 3 TXD TXD 4 DTR DTR 5 SG SG 6 DSR DSR 7 RTS RTS 8 CTS CTS 9RIRI(2) RS-422/485 Interface (XBL-C41A)RS-422 channel uses 5-pin terminal block for communication with external devices. Thenames and functions of pins, and data directions are as shown in the following table. Pin No. Name Signal direction (Cnet<-->External device) Function 1 TX+ Transmitted data (+) 2 TX- Transmitted data (-) 3 RX+ Received data (+) 4 RX- Received data (-) 5 SG Signal ground line [Pin assignment of RS-422 5-pin connector]RS-422 channel makes connection external devices and RS-422 and RS-485(Multi-drop)possible. When RS-422 channel is used as multi-drop, set channel RS-422 to RS-485communication in setting menu of RS-422 communication type of XG-PD, and connect the terminal of RS-422 as shown in the [RS-485 connection] table. Cnet Signal direction(Cnet<--->External device) External device Pin No. Name1 TX+ RX+2 TX- RX-3 RX+ TX+4 RX- TX-5 SG SG [RS-422 connection] Cnet Signal direction (Cnet<--->External device) External devicePin No. Name1 TX+ RX+2 TX- RX-3 RX+ TX+4 RX- TX-5 SG SG [RS-485 connection]Above figure shows how to connect RS-485 multi-drop communication. In the case of RS-485 communication, the TX+ and RX+ terminals should be shortened and TX- and RX- terminals should be shortened, then connected to the other devices. At this time,RS-485 should be selected by using the XG-PD. (3) Terminator (RS-422/485)(a) When the communication via channel RS-422 terminal resistor from external must beconnected. (b) Terminal resistor has the function to prevent distortion of signal by reflected wave of cable when long distance communication, the same resistor (1/2W) as characteristic impedance of cable must be connected to terminal of network.(c) When using the recommended cable in the section 3, connect terminal resistor ofusing another cable than recommended one, the same resistor (1/2W) as characteristic impedance of cable must be connected to both ends of cable.(e) How to connect terminal resistor [RS-485 connection]6. Cautions for system and network connection(1) All the stations in whole network should not have duplicated station number. Otherwise,it can cause serious communication error.(2) Use cable complying with specification in this data sheet. Otherwise, it can serious communication error.8. Warranty(1) Warranty periodLSIS provides an 18-month-warranty from the date of the production. (2) Warranty conditionsFor troubles within the warranty period, LSIS will replace the entire PLC or repair the troubled parts free of charge except the following cases.(a) The troubles caused by improper condition, environment or treatment exceptthe instructions of LSIS.(b) The troubles caused by external devices.(c) The troubles caused by remodeling or repairing based on the user’s owndiscretion.(d) The troubles caused by improper usage of the product.(e) The troubles caused by the reason which exceeded the expectation fromscience and technology level when LSIS manufactured the product. (f) The troubles caused by natural disaster.(3) This warranty is limited to the PLC itself only. It is not valid for the whole systemwhich the PLC is attached to.Be sure to check the rated voltage and terminal arrangement for the► The symbols which are indicated in the PLC and User’s Manual mean as follows. This symbol means paying attention because of danger of electric shock.Store this datasheet in a safe place so that you can take it out and read it whenever necessary. Always forward it to the end user Do not contact the terminals while the power is applied.Warning Caution ∙ HEAD OFFICELS Tower, 127, LS-ro, Dongan-gu, Anyang-si,Gyeonggi-do, 431-848, Korea Tel: 82-2-2034-4870 Fax: (82-2)2034-4648 e-mail: ****************∙ LSIS(ME) FZE _ Dubai, U.A.E. Tel: 971-4-886-5360 Fax: 971-4-886-5361 e-mail: ******************∙ LSIS Tokyo Office _ Tokyo, Japan Tel: 81-3-3582-9128 Fax: 81-3-3582-2667 e-mail: ****************∙ LSIS Shanghai Office _ Shanghai, ChinaTel: 86-21-5237-9977(609) Fax: 89-21-5237-7189 e-mail: ***************.cn∙ LSIS Beijing Office _ Beijing, ChinaTel: 86-10-5825-6027(666) Fax: 86-10-5825-6028 e-mail: **************.cn∙ LSIS Guangzhou Office _ Guangzhou, China Tel: 86-20-8328-6754 Fax: 86-20-8326-6287 e-mail: ***************.cn∙ LSIS Chengdu Office _ Chengdu, China Tel: 86-20-8328-6754 Fax: 86-20-8326-6287 e-mail: ***************∙ LSIS Qingdao Office _ Qingdao, China Tel: 86-532-8501-6068 Fax: 86-532-8501-6057 e-mail: ***************.cn∙ LSIS Europe B.V., Netherlands Tel: +31 (0)20 654 1420 Fax: +31(0)20 654 1429 e-mail: ******************- When using LSIS equipment, thoroughly read this datasheet and associated manuals introduced in thisdatasheet. Also pay careful attention to safety and handle the module properly.- Store this datasheet in a safe place so that you can take it out and read it whenever necessary..。
CAV25256-EEPROM中文资料
CAV25256是256Kb CMOS的EEPROM,SPI总线通信。
有片选/CS,时钟输入SCK,数据输入SI,数据输出SO./HOLD是暂停CAV25256的通信。
引脚描述:SI:数据输入引脚,包括引导码,地址,数据。
在SPI(0,0)和(1,1)模式下,输入数据在SCK的上升沿锁存输入。
SO:器件的数据输出引脚,在SPI(0,0)和(1,1)模式下,数据在SCK的下降沿输出。
SCK:器件时钟输入,被主机提供,用来与CAV25256同步通信/CS:CAV25256的片选引脚,当CS=1,SO输出是高阻抗状态,且器件在稳定模式(除非内部写操作正在进行中)。
每次主机与CAV25256通信之前,必须经过该脚从高到低的过渡。
在CS低到高过渡完结束通信。
/WP:写保护引脚为高时,允许器件所有的写操作。
当WP=0,并且状态寄存器中的WPEN=1,写状态寄存器失效。
/HOLD:HOLD输入用来暂停主机与CAV25256之间的通信,无需之后重传整个序列。
要想暂停,HOLD=0,SCK输入低时,恢复HOLD=1。
当不需要暂停时,HOLD直接或者通过电阻连接到VCC。
功能描述:CAV25256支持SPI总线控制,(0,0)和(1,1)模式。
器件有8位指令寄存器。
读取CAV25256存储的数据只要提供READ指令和地址。
写数据到CAV25256,需要WRITE 指令,地址和数据。
还需要通过置位状态寄存器包含的对应为来使能器件的写操作。
CS引脚从高到低转换后,CAV25256将接收列表6条指令中的任何一条。
不会理财任何其他可能的组合。
当状态寄存器的IPL=1,CAV25256额外的识别页(64Kb)可以接收读写操作。
用户可以选择用户还可以选择进行识别页永久写保护。
状态寄存器:状态寄存器包含了很多状态与控制位/RDY位指示器件当前是否正在进行写操作。
当内部写操作正在进行,该位自动置位。
当器件准备好接收命令时,该位复位。
IOGEAR GWU625 无线N USB适配器商品说明书
GWU625Compact Wireless N USB AdaptorIoGear Part #: GWU625The new IOGEAR Compact Wireless-N USB Adapter allows you to connect your laptop or desktop to any Wireless-N network in your home or office. The Wireless-N (IEEE™ 802.11n) USB 2.0 Adapter is the perfect solution for those users who want to upgrade older computers to the next generation of wireless technology.Product DescriptionUsing dual antennas (1T2R) this product provides data rates up to 300Mbps and reduces Wi-Fi dead zones in your wireless environment. This new standard supplies sufficient bandwidth for faster file transfer, music downloads, video streaming, on-line gaming & HD multi-media applications. In addition to the increased speed and coverage, you will be pleased to know that it is compatible with your existing 802.11b and 802.11g routers and access points. The unit also features a WPS (Wi-Fi Protected Setup) button. This button assures quick and secure network setup.Enjoy improved range, speed and reliability today with the Compact Wireless-N USB Adapter from IOGEAR!∙Add high-speed Wireless-N (802.11n) Internet access to any USB enabled computer ∙1T2R multiple radio technology improves effective throughput and range over existing 802.11 b/g products∙Compact and portable adapter plugs into your computer’s USB port∙Compatible Network Standards: IEEE 802.11n (up to 300Mbps) IEEE 802.11g (up to 54Mbps) IEEE 802.11b (up to 11Mbps)∙Push-button Wi-Fi Protected Setup™ (WPS) simplifies secure and easy wireless configuration∙WEP,TKZP, AES, WPA and WPA2 hardware encryption schemes∙Frequency Band Modulation Method: QPSK / BPSK / 16-QAM / 64-QAM∙Supports Ad Hoc and Infrastructure modes∙Supports USB 2.0 with up to 300Mbps transfer rate; backward compatible to USB 1.1 and 1.2∙Compatible with Microsoft Windows, Mac or Linux OSSystem Requirements∙Operating Systemo Windows XP, Windows Vista, Windows 7o Mac OS X v10.4 and aboveo Linux Fedora 10(Kernel: 2.6.27.5-117)∙Available USB port∙Wireless networkPackage Contents∙ 1 x Wireless-N USB 2.0 Adapter∙ 1 x Driver CD∙ 1 x Quick Start Guide∙ 1 x Warranty / Registration CardFor use with Raspberry PiThe standard Raspbian OS for Raspberry Pi has the driver for this wireless adapter built-in, but Raspbian does not include a graphical WiFi interface. The following instructions allow you to install the graphical user interface for network connections.Connected to wired EthernetThe easiest way to install the Network Manager is to connect the Raspberry Pi to a wired network (this only has to be done once). Once connected, from the command prompt or terminal window of the desktop, type the following command: sudo apt-get install wicd -y and press Enter. When the install is complete there will be a networking icon in the lower right hand corner of the desktop.Connect over WirelessIf you do not have a wired connection, you can manually set up a wireless connection the first time, then install the Network Manager. First, type sudo nano /etc/network/interfaces and press Enter. This will open a text editor. Add the following text to the end of the file:auto wlan0iface wlan0 inet dhcpwpa-ssid "SSID"(Keep quotes, replace SSID with the SSID of your wireless network)wpa-psk "PASS"(Keep quotes, replace PASS with the network password)Once typed, press Ctrl and X together, press Y to confirm saving, and press Enter. Then type ifup wlan0. This will activate the wireless interface and connect to the network. Once the network is up and connected to the Internet, type sudo apt-get install wicd -y and press Enter. When this is done, type sudo nano /etc/network/interfaces and remove all text that was previously added. Press Ctrl and X, then Y, then Enter to exit. Reboot the Raspberry Pi and the Network Manager will be present at the bottom corner of the desktop.SpecificationsPower Consumption Transmit : < 380mA. ; Receive: < 250mA. Operating Temperature0 ~ 50 celsiusStorage Temperature-10 ~ 70 celsiusUSB Specification USB 2.0Humidity 5 ~ 90% (non-condensing) Transmission Power17 dBmFrequency Band 2.4GHz ~ 2.483GHz unlicensed ISM band Modulation IEEE 802.11n: BPSK, QPSK, 16-QAM, 64-QAMData Rate IEEE 802.11n : 6, 9, 12, 18, 24, 36, 48, 54, 60, 90, 120, 180, 240, 270 and up to 300MbpsInterface USB 2.0Security64-bit or 128-bit WEP/WPA TKIPManagement Windows-based UtilityOperating Range100 -400m, depending on surrounding environment Encryption64 bit / 128 bit WEP, TKIP, AESAntenna Type On board chip antennaRange Up to 320 ftChipset RTL8191SUDimensions GWU625Unit DimensionsWidth2"Height1"Depth0.25"Unit Package DimensionsWidth5"Height7.75"Depth1"WeightUnit Pack Wt.0.15 lbUnit Wt.0.30 ozGWU625。
莫悟 UC-8200 系列双核麒麟A7 1GHz IIoT 网关说明书
UC-8200SeriesArm Cortex-A7dual-core1GHz IIoT gateways with built-in LTE Cat.4,1mini PCIe expansion slot for a Wi-Fi module,1CAN port,4DIs,4DOsFeatures and Benefits•Armv7Cortex-A7dual-core1GHz•Moxa Industrial Linux with10-year superior long-term support•LTE-ready computer with Verizon/AT&T certification and industrial-grade CE/FCC/UL certifications•Dual-SIM slots•2auto-sensing10/100/1000Mbps Ethernet ports•Integrated LTE Cat.4module with US/EU/APAC band support•1CAN port supports CAN2.0A/B•microSD socket for storage expansion•Programmable LEDs and a programmable button for easy installation andmaintenance•-40to85°C wide temperature range and-40to70°C with LTE enabledCertificationsIntroductionThe UC-8200computing platform is designed for embedded data acquisition applications.The computer comes with dual RS-232/422/485serial ports,dual10/100/1000Mbps Ethernet ports,and one CAN port as well as dual Mini PCIe socket to support Wi-Fi/cellular modules.These versatile capabilities let users efficiently adapt the UC-8200to a variety of complex communications solutions.The UC-8200is built around a Cortex-A7dual core processor that has been optimized for use in energy monitoring systems,but is widely applicable to a variety of industrial solutions.With flexible interfacing options,this tiny embedded computer is a reliable and secure gateway for data acquisition and processing at field sites as well as a useful communications platform for many other large-scale deployments.Wide temperature LTE-enabled models are available for extended temperature applications.All units are thoroughly tested in a testing chamber, guaranteeing that the LTE-enabled computing platforms are suitable for wide-temperature applications.AppearanceUC-8210UC-8220SpecificationsComputerCPU Armv7Cortex-A7dual-core1GHzDRAM2GB DDR3LStorage Pre-installed8GB eMMCPre-installed OS Moxa Industrial Linux(Debian9,Kernel4.4)See /MILExpansion Slots MicroSD(SD3.0)socket x1Computer InterfaceTPM UC-8210-T-LX-S:TPM v2.0UC-8220-T-LX-AP-S:TPM v2.0UC-8220-T-LX-EU-S:TPM v2.0UC-8220-T-LX-US-S:TPM v2.0Ethernet Ports Auto-sensing10/100/1000Mbps ports(RJ45connector)x2 Serial Ports RS-232/422/485ports x2,software selectable(DB9male) CAN Ports CAN2.0A/B x1(DB9male)Digital Input DIs x4Digital Output DOs x4USB2.0USB2.0hosts x1,type-A connectorsWi-Fi Antenna Connector RP-SMA x2(UC-8220only)Cellular Antenna Connector SMA x2(UC-8220only)GPS Antenna Connector SMA x1(UC-8220only)Expansion Slots mPCIe slot x2(UC-8220-T-LX)mPCIe slot x1(UC-8220-T-LX US/EU/AP models)SIM Format Nano(UC-8220only)Number of SIMs2(UC-8220only)Buttons Programmable buttonEthernet InterfaceMagnetic Isolation Protection 1.5kV(built-in)Serial InterfaceConsole Port1x4-pin header to DB9console portData Bits5,6,7,8Parity None,Even,Odd,Space,MarkStop Bits1,1.5,2Serial SignalsRS-232TxD,RxD,RTS,CTS,DTR,DSR,DCD,GNDRS-422Tx+,Tx-,Rx+,Rx-,GNDRS-485-2w Data+,Data-,GNDRS-485-4w Tx+,Tx-,Rx+,Rx-,GNDCAN InterfaceNo.of Ports1Connector DB9maleBaudrate10to1000kbpsIndustrial Protocols CAN2.0A,CAN2.0BIsolation2kV(built-in)Signals CAN_H,CAN_L,CAN_GND,CAN_SHLD,CAN_V+,GNDDigital InputsConnector Screw-fastened Euroblock terminalDry Contact Off:openOn:short to GNDIsolation3K VDCSensor Type Wet contact(NPN)Dry contactWet Contact(DI to COM)On:10to30VDCOff:0to3VDCDigital OutputsConnector Screw-fastened Euroblock terminalCurrent Rating200mA per channelI/O Type SinkVoltage24VDC nominal,open collector to30VDCCellular InterfaceCellular Standards LTE CAT-4Band Options US model:LTE Bands:Band2(1900MHz)/Band4(1700MHz)/Band5(850MHz)/Band13(700MHz)/Band14(700MHz)UMTS Bands:Band2(1900MHz)/Band5(850MHz)Carrier Approval:Verizon,AT&TEU model:LTE Bands:Band1(2100MHz)/Band3(1800MHz)/Band5(850MHz)/Band7(2600MHz)/Band8(900MHz)/LTE Band20(800MHz)UMTS Bands:Band1(2100MHz)/Band2(1900MHz)/Band5(850MHz)/Band8(900MHz)AP model:LTE Bands:Band1(2100MHz)/Band3(1800MHz)/Band5(850MHz)/Band7(2600MHz)/Band8(900MHz)/Band28(700MHz)UMTS Bands:Band1(2100MHz)/Band2(1900MHz)/Band5(850MHz)/Band8(900MHz)GPS InterfaceReceiver Types72-channel u-blox M8engineGPS/GLONASS/GalileoAccuracy Position:2.5m CEPSBAS:2.0m CEPAcquisition Aided starts:3secCold starts:26secSensitivity Cold starts:-148dBmTracking:-164dBmTime Pulse0.25Hz to10MHzLED IndicatorsSystem Power x2Programmable x1SIM card indicator x1Wireless Signal Strength Cellular/Wi-Fi x6Power ParametersNo.of Power Inputs Redundant dual inputsInput Voltage12to48VDCPower Consumption10WInput Current0.8A@12VDCReliabilityAlert Tools External RTC(real-time clock)Automatic Reboot Trigger External WDT(watchdog timer)Physical CharacteristicsDimensions141.5x120x39mm(5.7x4.72x1.54in)for UC-8220141.5x120x27mm(5.7x4.72x1.06in)for UC-8210Housing SECCMetalInstallation DIN-rail mounting,Wall mounting(with optional kit)IP Rating IP30Weight UC-8210:560g(1.23lb)UC-8220:750g(1.65lb)Environmental LimitsAmbient Relative Humidity5to95%(non-condensing)Operating Temperature UC-8210-T-LX:-40to85°C(-40to185°F)UC-8210-T-LX-S:-40to85°C(-40to185°F)UC-8220-T-LX:-40to70°C(-40to158°F)UC-8220-T-LX-US-S:-40to70°C(-40to158°F)UC-8220-T-LX-EU-S:-40to70°C(-40to158°F)UC-8220-T-LX-AP-S:-40to70°C(-40to158°F)Storage Temperature(package included)-40to85°C(-40to185°F)Shock IEC60068-2-27Vibration2Grms@IEC60068-2-64,random wave,5-500Hz,1hr per axis(without USB devicesattached)Standards and CertificationsSafety UL62368-1,EN62368-1EMC EN55032/35,EN61000-6-2/-6-4EMI CISPR32,FCC Part15B Class AEMS IEC61000-4-2ESD:Contact:4kV;Air:8kVIEC61000-4-3RS:80MHz to1GHz:10V/mIEC61000-4-4EFT:Power:2kV;Signal:1kVIEC61000-4-6CS:10VIEC61000-4-8PFMFIEC61000-4-5Surge:Power:0.5kV;Signal:1kVHazardous Locations Class I Division2,ATEXCarrier Approvals VerizonAT&TGreen Product RoHS,CRoHS,WEEEMTBFTime UC-8210-T-LX:716,739hrsUC-8210-T-LX-S:708,581hrsUC-8220-T-LX:650,836hrsUC-8220-T-LX-US-S:528,574hrsUC-8220-T-LX-EU-S:528,574hrsUC-8220-T-LX-AP-S:528,574hrsStandards Telcordia(Bellcore)Standard TR/SRWarrantyWarranty Period5yearsDetails See /warrantyPackage ContentsDevice1x UC-8200Series computerDocumentation1x quick installation guide1x warranty cardInstallation Kit1x DIN-rail kit(preinstalled)1x power jack6x M2.5mounting screws for the cellular module Cable1x console cableDimensionsUC-8210UC-8220Ordering InformationModel Name CPU RAM Storage TPM mPCIe Slot1forLTE ModulemPCIe Slot2forWi-Fi ModuleOperatingTemperatureUC-8210-T-LX1GHz Dual Core2GB8GB–––-40to85°C UC-8210-T-LX-S1GHz Dual Core2GB8GB Built-in––-40to85°C UC-8220-T-LX1GHz Dual Core2GB8GB–Reserved Reserved-40to70°CUC-8220-T-LX-US-S 1GHz Dual Core2GB8GB Built-inUS region LTEmodulepreinstalledReserved-40to70°CUC-8220-T-LX-EU-S 1GHz Dual Core2GB8GB Built-inEurope regionLTE modulepreinstalledReserved-40to70°CUC-8220-T-LX-AP-S 1GHz Dual Core2GB8GB Built-inAPAC region LTEmodulepreinstalledReserved-40to70°CAccessories(sold separately)Power AdaptersPWR-12150-EU-SA-T Locking barrel plug,12VDC,1.5A,100to240VAC,Continental Europe(EU)plug,-40to75°Coperating temperaturePWR-12150-UK-SA-T Locking barrel plug,12VDC,1.5A,100to240VAC,United Kingdom(UK)plug,-40to75°C operatingtemperaturePWR-12150-USJP-SA-T Locking barrel plug,12VDC1.5A,100to240VAC,United States/Japan(US/JP)plug,-40to75°Coperating temperaturePWR-12150-AU-SA-T Locking barrel plug,12VDC,1.5A,100to240VAC,Australia(AU)plug,-40to75°C operatingtemperaturePWR-12150-CN-SA-T Locking barrel plug,12VDC,1.5A,100to240VAC,China(CN)plug,-40to75°C operatingtemperaturePower WiringCBL-PJTB-10Non-locking barrel plug to bare-wire cableCablesCBL-F9DPF1x4-BK-100Console cable with4-pin connector,1mWi-Fi Wireless ModulesUC-8200WiFi-AC Wi-Fi package for UC-8200,includes Wi-Fi module,6screws,1heat sink,1padAntennasANT-LTEUS-ASM-01GSM/GPRS/EDGE/UMTS/HSPA/LTE,omni-directional rubber duck antenna,1dBiANT-LTE-ASM-04BK704-960/1710-2620MHz,LTE omni-directional stick antenna,4.5dBiANT-LTE-OSM-03-3m BK700-2700MHz,multi-band antenna,specifically designed for2G,3G,and4G applications,3m cable ANT-LTE-ASM-05BK704-960/1710-2620MHz,LTE stick antenna,5dBiANT-LTE-OSM-06-3m BK MIMO Multiband antenna with screw-fastened mounting option for700-2700/2400-2500/5150-5850MHzfrequenciesANT-WDB-ARM-0202 2.4/5GHz,panel antenna,2/2dBi,RP-SMA(male)DIN-Rail Mounting KitsUC-8220DIN-rail Mounting Kit DIN-rail mounting kit for UC-8220with4M3screwsWall-Mounting KitsUC-8200Wall-mounting Kit Wall-mounting kit for UC-8200with4M3screws©Moxa Inc.All rights reserved.Updated Jun29,2021.This document and any portion thereof may not be reproduced or used in any manner whatsoever without the express written permission of Moxa Inc.Product specifications subject to change without notice.Visit our website for the most up-to-date product information.。
MC14106B中文资料
MC14106B 中文资料目录元件的最大额定值 (1)MC14106B功能介绍 (1)电气特性 (3)芯片转换特性 (4)芯片应用举例 (4)应用1 按键防抖 (4)应用2 积分电路 (5)MC14106B封装信息 (6)PDIP-14封装 (6)SOIC-14封装 (7)TSSOP-14封装 (8)元件的最大额定值条件之上进行功能操作。
长期暴露在高于推荐工作条件的环境下可能会影响器件的可靠性。
表中的电压值均为对地电压。
MC14106B功能介绍MC14106B共14个引脚,其中14号引脚为VDD(+),7号引脚为VSS (-),其余引脚为输入输出引脚,1,3,5,9,11,13号引脚为输入引脚,2,4,6,8,10,12号引脚为输出引脚。
内部逻辑如图1如所示,从图1中我们可以看出,MC14106B内部共有6组相同功能施密特触发器,每组施密特触发器的逻辑如图2所示。
图1图2下面通过图3所示施密特触发器讲解其工作过程。
其工作时序如图4所示。
当输入端输入低电平(VSS)时,输出端输出高电平(V OH)。
当输入端电平变为高电平(VDD)时,输出端电平经过一小段时间后也会发生变化,变为低电平(V OL)。
当输入端电平由VDD变为VSS后,一小段时间后,输出端电平变为高电平(V OH)。
施密特触发器最重要的是以下几个参数:从输入端电平由低到高变化到50%时,至输出端电平由高到低变化变化至50%时的时间记做t PHL;从输入端电平由高到低变化到50%时,至输出端电平由低到高变化变化至50%时的时间记做t PLH。
当输出端产生下调沿时,电平从90%变化至10%所用的时间t f;当输出端产生上跳沿时,电平从10%变化至90%所用的时间t r。
这些参数主要与VDD有关,可以通过下面提供的电气特性表格查出典型值。
图3图4通过图5进一步讲解施密特触发器的工作流程。
当输入端的电平达到V T+之后,输出端电平才会发生负跳变,当输入端平超过V T+之后,即使略低于该值,输出端不会发生负跳变,直到当输入端电平低于V T-,输出端才会发生正跳变。
MC1GU256NCVB-0QC00中文资料
MultiMediaCard SpecificationVersion : Ver. 0.9Date 4 – June - 2004Samsung Electronics Co., LTDSemiconductor Flash Memory Product Planning & Applications1 Introduction to the MultiMediaCard ----------------------------------------------------------- 51.1 System Features ----------------------------------------------------------------------------------------- 5-------------------------------------------------------------------------------------- 51.2 ProductModel2 Function Description ------------------------------------------------------------------------------- 72.1 Flash Technology Independence ------------------------------------------------------------------ 72.2 Defect and Error Management --------------------------------------------------------------------- 72.3 Endurance ----------------------------------------------------------------------------------------------- 72.4 Automatic Sleep Mode ------------------------------------------------------------------------------- 72.5 Hot Insertion -------------------------------------------------------------------------------------------- 82.6 MultiMediaCard Mode -------------------------------------------------------------------------------- 82.6.1 MultiMediaCard Standard Compliance ----------------------------------------------------------- 82.6.2 Negotiation Operation Conditions ----------------------------------------------------------------- 82.6.3 Card Acquisition and Identification ---------------------------------------------------------------- 82.6.4 Card Status ---------------------------------------------------------------------------------------------- 82.6.5 Memory Array Partitioning --------------------------------------------------------------------------- 92.6.6 Read and Write Operations ------------------------------------------------------------------------- 92.6.7 Data Transfer Rate ------------------------------------------------------------------------------------102.6.8 Data Protection in the Flash Card -----------------------------------------------------------------10-----------------------------------------------------------------------------------------------------10 2.6.9 Erase2.6.10 Write Protection ----------------------------------------------------------------------------------------102.6.11 Copy Bit ------------------------------------------------------------------------------------------------- 102.6.12 The CSD Register ------------------------------------------------------------------------------------ 112.7 SPI Mode ----------------------------------------------------------------------------------------------- 112.7.1 Negotiating Operation Conditions ---------------------------------------------------------------- 112.7.2 Card Acquisition and Identification --------------------------------------------------------------- 112.7.3 Card Status --------------------------------------------------------------------------------------------- 112.7.4 Memory Array Partitioning -------------------------------------------------------------------------- 112.7.5 Read and Write Operations ------------------------------------------------------------------------- 112.7.6 Data Transfer Rate ------------------------------------------------------------------------------------ 112.7.7 Data Protection in the MultiMediaCard ----------------------------------------------------------- 1212-----------------------------------------------------------------------------------------------------2.7.8 Erase2.7.9 Write Protection ---------------------------------------------------------------------------------------- 123 Product Specifications ----------------------------------------------------------------------------- 133.1 Recommended Operating Conditions ------------------------------------------------------------------------- 133.2 Operating Characteristis ----------------------------------------------------------------- 143.3 System Environmental Specifications ----------------------------------------------------------------- 153.4 System Reliability and Maintenance -------------------------------------------------------------- 153.5 Physical Specifications ------------------------------------------------------------------------------- 164 MultiMediaCard Interface Description --------------------------------------------------------- 174.1 Pin Assignments in MultiMediaCard Mode ------------------------------------------------------- 174.2 Pin Assignments in SPI Mode ---------------------------------------------------------------------- 184.3 MultiMediaCard Bus Topology ---------------------------------------------------------------------- 184.4 SPI Bus Topology -------------------------------------------------------------------------------------------------- 194.4.1 SPI Interface Concept ------------------------------------------------------------------------------------------- 194.4.2 SPI Bus Topology ------------------------------------------------------------------------------------------------ 1920------------------------------------------------------------------------------------------------- 4.5 Registers4.5.1 Operation Condition Register (OCR) ---------------------------------------------------------------------------204.5.2 Card Identification (CID) ------------------------------------------------------------------------------214.5.3 Relative Card Address (RCA) ----------------------------------------------------------------------- 21 4.5.4 Card Specific Data (CSD) ---------------------------------------------------------------------------- 22 4.6 MultiMediaCard Communication -------------------------------------------------------------------- 3030----------------------------------------------------------------------------------------------- 4.6.1 Commands4.7 Read, Write and Erase Time-out Conditions ----------------------------------------------------- 33 4.8 Card Identification Mode ------------------------------------------------------------------------------ 34 4.8.1 Operating Voltage Range Validation --------------------------------------------------------------- 35 4.9 Data Transfer Mode ------------------------------------------------------------------------------------ 35 4.9.1 Block Read ----------------------------------------------------------------------------------------------- 37 4.9.2 Block Write ----------------------------------------------------------------------------------------------- 3738------------------------------------------------------------------------------------------------------ 4.9.3 Erase4.9.4 Write Protect Management -------------------------------------------------------------------------- 38 4.9.5 Card Lock/Unlock Operation ------------------------------------------------------------------------ 38----------------------------------------------------------------------------------------------- 41 4.9.6 Responses4.9.7 Status ------------------------------------------------------------------------------------------------------ 42 4.9.8 Command Response Timing ------------------------------------------------------------------------ 4448 4.9.9 Reset------------------------------------------------------------------------------------------------------ 4.10 SPI Communication ----------------------------------------------------------------------------------- 49 4.10.1 Mode Selection ----------------------------------------------------------------------------------------- 49 4.10.2 Bus Transfer Protection ------------------------------------------------------------------------------ 49 4.10.3 Data Read Overview ---------------------------------------------------------------------------------- 50 4.10.4 Data Write Overview ---------------------------------------------------------------------------------- 51 4.10.5 Erase and Write Protect Management ----------------------------------------------------------- 52 4.10.6 Reading CID/CSD Registers ------------------------------------------------------------------------ 53 4.10.7 Reset Sequence --------------------------------------------------------------------------------------- 53 4.10.8 Error Conditions ---------------------------------------------------------------------------------------- 53 4.10.9 Memory Array Partitioning --------------------------------------------------------------------------- 53 4.10.10 Card Lock/Unlock -------------------------------------------------------------------------------------- 53 4.10.11 Commands ----------------------------------------------------------------------------------------------- 54 4.10.12 Responses ----------------------------------------------------------------------------------------------- 56 4.10.13 Data Tokens --------------------------------------------------------------------------------------------- 58 4.10.14 Data Error Token --------------------------------------------------------------------------------------- 59 4.10.15 Clearing Status Bits ------------------------------------------------------------------------------------ 60 4.11 SPI Bus Timing ----------------------------------------------------------------------------------------- 61 4.12 Error Handling ------------------------------------------------------------------------------------------ 64 4.12.1 Error Correction Code (ECC) ----------------------------------------------------------------------- 64 4.12.2 Cyclic Redundancy Check (CRC) ----------------------------------------------------------------- 642 Function Description2.1 Flash Technology IndependenceThe 512 byte sector size of the MultiMediaCard is the same as that in an IDE magnetic disk drive. To write or read a sector (or multiple sectors), the host computer software simply issues a Read or Write command to the MultiMediaCard. This command contains the address and the number of sectors to write/read. The host software then waits for the command to complete. The host software does not get involved in the details of how the flash memory is erased, programmed or read. This is extremely important as flash devices are expected to get more and more complex in the future. Because the MultiMediaCard uses an intelligent on-board controller, the host system software will not require changing as new flash memory evolves. In other words, systems that support the MultiMediaCard today will be able to access future MultiMediaCards built with new flash technology without having to update or change host software.2.2 Defect and Error ManagementMultiMediaCards contain a sophisticated defect and error management system. This system is analogous to the systems found in magnetic disk drives and in many cases offers enhancements. For instance, disk drives do not typically perform a read after write to confirm the data is written correctly because of the performance penalty that would be incurred. MultiMediaCards do a read after write under margin conditions to verify that the data is written correctly (except in the case of a Write without Erase Command). In the rare case that a bit is found to be defective, MultiMediaCards replace this bad bit with a spare bit within the sector header. If necessary, MultiMediaCards will even replace the entire sector with a spare sector. This is completely transparent to the host and does not consume any user data space.The MultiMediaCards soft error rate specification is much better than the magnetic disk drive specification. In the extremely rare case a read error does occur, MultiMediaCards have innovative algorithms to recover the data. This is similar to using retries on a disk drive but is much more sophisticated. The last line of defense is to employ powerful ECC to correct the data. If ECC is used to recover data, defective bits are replaced with spare bits to ensure they do not cause any future problems.These defect and error management systems coupled with the solid-state construction give MultiMediaCards unparalleled reliability2.3 EnduranceMultiMediaCards have an endurance specification for each sector of 1,000,000 writes (reading a logical sector is unlimited). This is far beyond what is needed in nearly all applications of MultiMediaCards. Even very heavy use of the MultiMediaCard in cellular phones, personal communicators, pagers and voice recorders will use only a fraction of the total endurance over the typical device’s five year lifetime. For instance, it would take over 100 years to wear out an area on the MultiMediaCard on which a files of any size (from 512 bytes to capacity) was rewritten 3 times per hour, 8 hours a day, 365 days per year.With typical applications the endurance limit is not of any practical concern to the vast majority of users.2.4 Automatic Sleep ModeAn important feature of the MultiMediaCard is automatic entrance and exit from sleep mode. Upon completion of an operation, the MultiMediaCard will enter the sleep mode to conserve power if no further commands are received within 5 msec The host does not have to take any action for this to occur. In most systems, the MultiMediaCard is in sleep mode except when the host is accessing it, thus conserving power. When the host is ready to access the MultiMediaCard and it is in sleep mode, any command issued to the MultiMediaCard will cause it to exit sleep and respond. The host does not have to issue a reset first. It may do this if desired, but it is not needed. By not issuing the reset, performance is improved through the reduction of overhead.2.5 Hot InsertionSupport for hot insertion will be required on the host but will be supported through the connector. Connector manufacturers will provide connectors that have power pins long enough to be powered before contact is made with the other pins. Please see connector data sheets for more details. This approach is similar to that used in PCMCIA to allow for hot insertion. This applies to both MultiMediaCard and SPI modes.2.6 MultiMediaCard Mode2.6.1 MultiMediaCard Standard ComplianceThe MultiMediaCard is fully compliant with MultiMediaCard standard specification V3.31.The structure of the Card Specific Data (CSD) register is compliant with CSD structure V1.2.2.6.2 Negotiating Operation ConditionsThe MultiMediaCard supports the operation condition verification sequence defined in the MultiMediaCard standard specifications. The MultiMediaCard host should define an operating voltage range that is not supported by the MultiMediaCard. It will put itself in an inactive state and ignore any bus communication. The only way to get the card out of the inactive state is by powering it down and up again. In addition the host can explicitly send the card to the inactive state by using the GO_INACTIVE_STATE command.2.6.3 Card Acquisition and IdentificationThe MultiMediaCard bus is a single master (MultiMediaCard host) and multi-slaves (cards) bus. The host can query the bus and find out how many cards of which type are currently connected. The MultiMediaCard’s CID register is pre-programmed with a unique card identification number which is used during the acquisition and identification procedureIn addition, the MultiMediaCard host can read the card’s CID register using the READ_CID MultiMediaCard command. The CID register is programmed during the MultiMediaCard testing and formatting procedure, on the manufacturing floor. The MultiMediaCard host can only read this register and not write to it.2.6.4 Card StatusMultiMediaCard status is stored in a 32 bit status register which is sent as the data field in the card respond to host commands. Status register provides information about the card’s current state and completion codes for the last host command. The card status can be explicitly read (polled) with the SEND_STATUS command.2.6.7 Data Protection in the Flash CardEvery sector is protected with an Error Correction Code (ECC). The ECC is generated (in the memory card) when the sectors are written and validated when the data is read. If defects are found, the data is corrected prior to transmission to the host.The MultiMediaCard can be considered error free and no additional data protection is needed. However, if an application uses additional, external, ECC protection, the data organization is defined in the user writeable section of the CSD register2.6.8 EraseThe smallest erasable unit in the MultiMediaCard is a erase group. In order to speed up the erase procedure, multiple erase groups can be erased in the same time. The erase operation is divided into two stages.Tagging - Selecting the Sectors for ErasingTo facilitate selection, a first command with the starting address is followed by a second command with the final address, and all erase groups within this range will be selected for erase.Erasing - Starting the Erase ProcessTagging can address erase groups. An arbitrary selection of erase groups may be erased at one time. Tagging and erasing must follow a strict command sequence (refer to the MultiMediaCard standard specification for details).2.6.9 Write ProtectionThe MultiMediaCard erase groups are grouped into write protection groups. Commands are provided for limiting and enabling write and erase privileges for each group individually. The current write protect map can be read using SEND_WRITE_PROT command.In addition two, permanent and temporary, card levels write protection options are available.Both can be set using the PROGRAM_CSD command (see below). The permanent write protect bit, once set, cannot be cleared.The One Time Programmable (OTP) characteristic of the permanent write protect bit is implemented in the MultiMediaCard controller firmware and not with a physical OTP cell.2.6.10 Copy BitThe content of an MultiMediaCard can be marked as an original or a copy using the copy bit in the CSD register. Once the Copy bit is set (marked as a copy) it cannot be cleared.The Copy bit of the MultiMediaCard is programmed (during test and formatting on the manufacturing floor) as a copy. The MultiMediaCard can be purchased with the copy bit set (copy) or cleared, indicating the card is a master.The One Time Programmable (OTP) characteristic of the Copy bit is implemented in the MultiMediaCard controller firmware and not with a physical OTP cell.2.6.11 The CSD RegisterAll the configuration information of the MultiMediaCard is stored in the CSD register. The MSB bytes of the register contain manufacturer data and the two least significant bytes contains the host controlled data - the card Copy and write protection and the user ECC register.The host can read the CSD register and alter the host controlled data bytes using the SEND_CSD and PROGRAM_CSD commands.2.7 SPI ModeThe SPI mode is a secondary (optional) communication protocol offered for MultiMediaCard. This mode is a subset of the MultiMediaCard protocol, designed to communicate with an SPI channel, commonly found in Motorola’s (and lately a few other vendors’) microcontrollers.2.7.1 Negotiating Operation ConditionsThe operating condition negotiation function of the MultiMediaCard bus is not supported in SPI mode. The host must work within the valid voltage range (2.7 to 3.6 volts) of the card.2.7.2 Card Acquisition and IdentificationThe card acquisition and identification function of the MultiMediaCard bus is not supported in SPI mode. The host must know the number of cards currently connected on the bus. Specific card selection is done via the CS signal.2.7.3 Card StatusIn SPI mode only 16 bits (containing the errors relevant to SPI mode) can be read out of the MultiMediaCard status register.2.7.4 Memory Array PartitioningMemory partitioning in SPI mode is equivalent to MultiMediaCard mode. All read and write commands are byte addressable.2.7.5 Read and Write OperationsIn SPI mode, only single block read/write mode is supported.2.7.6 Data Transfer RateIn SPI mode only block mode is supported. The typical access time (latency) for each data block, in read operation, is 1.5mS. The write typical access time (latency) for each data block, in read operation, is 1.5mS. The write block operation is done in handshake mode. The card will keep DataOut line low as long as the write operation is in progress and there are no write buffers available.2.7.7 Data Protection in the MultiMediaCardSame as for the MultiMediaCard mode.2.7.8 EraseSame as in MultiMediaCard mode2.7.9 Write ProtectionSame as in MultiMediaCard modeFigure 3-1 Timing Diagram of Data Input and Output3.5 Physical SpecificationsDimensions of Normal MMC(24mm x 32mm x 1.4mm)Dimensions of RS-MMC(24mm x 18mm x 1.4mm)rising and falling edges). If the host does not allow the switchable R OD implementation, a fix R CMD can be used. Consequently the maximum operating implementation, a fix R CMD can be used. Consequently the maximum operating frequency in the open drain mode has to be reduced in this case.4.4 SPI Bus Topology4.4.1 SPI Interface ConceptThe Serial Peripheral Interface (SPI) is a general-purpose synchronous serial interface originally found on certain Motorola micro-controllers. The MultiMediaCard SPI interface is compatible with SPI hosts available on the market. As any other SPI device the MultiMediaCard SPI channel consists of the following 4 signals:- CS : Host to card chip select signal- CLK : Host to card clock signal- DataIn : Host to card data signal- DataOut : Card to host data signalAnother SPI common characteristic, which is implemented in the MultiMediaCard card as well, is byte transfers. All data tokens are multiples of 8 bit bytes and always byte aligned to the CS signal. The SPI standard defines the physical link only and not the complete data transfer protocol. The MultiMediaCard uses a subset of the MultiMediaCard protocol and command set.4.4.2 SPI Bus TopologyThe MultiMediaCard card identification and addressing algorithms are replaced by hardware Chip Select (CS) signal. There are no broadcast commands. A card (slave) is selected, for every command, by asserting (active low) the CS signal (see Figure 4-3). The CS signal bust is continuously active for the duration of the SPI transaction (command, response and data). The only exception is card-programming time. At this time the host can de-assert the CS signal without affecting the programming process. The bi-directional CMD and DAT lines are replaced by unidirectional dataIn and dataOut signals. This eliminates the ability of executing commands while data is being read or written and, therefore, eliminates the sequential and multi block read/write operations. The SPI channel supports only single block read/write.Figure 4-3 SPI Bus SystemReadThe read access time is defined as the sum of the two times given by the CSD parameters TAAC and NSAC (refer to Table “Card Specific Data (CSD)”). These card parameters define the typical delay between the end bit of the read command and the start bit of the data block. This number is card dependent and should be used by the host to calculate throughput and the maximal frequency for stream read.WriteThe R2W_FACTOR field in the CSD is used to calculate the typical block program time obtained by multiplying the read access time by this factor. It applies to all write/erase commands (e.g. SET(CLEAR)_WRITE_PROTECT, PROGRAM_CSD(CID) and the block write commands). It should be used by the host to calculate throughput.EraseThe duration of an erase command will be (order of magnitude) the number of sectors to be erased multiplied by the block write delay.4.8 Card Identification ModeAll the data communication in the card identification mode uses only the command line (CMD). MultiMediaCard State Diagram (Card Identification Mode)Figure 4-2 MultiMediaCard State Diagram (Card Identification Mode)The host starts the card identification process in open drain mode with the identification clock rate f OD(generated by a push pull driver stage). The open drain driver stages on the CMD line allow the parallel card operation during card identification. After the bus is activated the host will request the cards to send their valid operation conditions with the command SEND_OP_COND (CMD1). Since the bus is in open drain mode, as long as there is more than one card with operating conditions restrictions, the host gets in the response to the CMD1 a “wired or” operation condition restrictions of those cards. The host then must pick a common denominator for operation and notify the application that cards with out of range parameters (from the host perspective) are connected to the bus. Incompatible cards go into Inactive State (refer to also Chapter “Operating Voltage Range Validation”). The busy bit in the CMD1 response can be used by a card to tell the host that it is still working on its power-up/reset procedure (e.g. downloading the register information from memory field) and is not ready yet for communication. In this case the host must repeat CMD1 until the busy bit is cleared. After an operating mode is established, the host asks all cards for their unique card identification (CID) number with the broadcast command ALL_SEND_CID (CMD2).All not already identified cards (i.e. those which are in Ready State) simultaneously start sending their CID numbers serially, while bit-wise monitoring their outgoing bitstream. Those cards, whose outgoing CID bits do not match the corresponding bits on the command line in any one of the bit periods, stop sending their CID immediately and must wait for the next identification cycle (cards stay in the Ready State). There should be only one card which successfully sends its full CID-number to the host. This card then goes into the Identification State. The host assigns to this card (using CMD3, SET_RELATIVE_ADDR) a relative card address (RCA, shorter than CID), which will be used to address the card in future communication (faster than with the CID). Once the RCA is received the card transfers to the Standby State and does not react to further identification cycles. The card also switches the output drivers from the open-drain to the push-pull mode in this state. The host repeats the identification process as long as it receives a response (CID) to its identification command (CMD2). When no card responds to this command, all cards have been identified. The time-out condition to recognize this, is waiting for the start bit for more than 5 clock periods after sending CMD24.8.1 Operating Voltage Range ValidationThe MultiMediaCard standards operating range validation is intended to support reduced voltage range MultiMediaCards. The MultiMediaCard supports the range of 2.7 V to 3.6V supply voltage. So the MultiMediaCard sends a R3 response to CMD1 which contains an OCR value of 0x80FF8000 if the busy flag is set to “ready” or 0x00FF8000 if the busy flag is active (refer to Chapter “Responses”). By omitting the voltage range in the command, the host can query the card stack and determine the common voltage range before sending out-of-range cards into the Inactive State. This bus query should be used if the host is able to select a common voltage range or if a notification to the application of non usable cards in the stack is desired. Afterwards, the host must choose a voltage for operation and reissue CMD1 with this condition sending incompatible cards into the Inactive State.4.9 Data Transfer ModeWhen in Standby State, both CMD and DAT lines are in the push-pull mode. As long as the content of all CSD registers is not known, the f PushPull clock rate is equal to the slow f OpenDrain clock rate. SEND_CSD (CMD9) allows the host to get the Card Specific Data (CSD register), e.g. ECC type, block length, card storage capacity, maximum clock rate etc..。
源2电源(Cam-Lok)连接的产品配置说明说明书
Quick connect of temporary generatorProduct configurations• Cam-Lok E E1016 series (male) receptacles allow quick connection of source 2 (emergency) power• Operation modes:• Manual• Non-automatic• Automatic• 30 to 1000 A• Two-, three- and four-pole • Up to 600 Vac, 50/60 Hz• Open transition• Service entrance (100% rated)• Integral molded case circuitbreaker(s) with trip unit • NEMA T 1, 12, 3R enclosure • UL T 1008 Listed, CSA T C22.2 No. 178, Seismic OSHPD/IBC/ CBC/UBC Zone 4• Cam-Lok options: hinged covers; minimum ground ampacity (25%, 50%, 100%)Features and benefits• Source 2 power (Cam-Lok)connections are color codedto industry standards• Quick-connect transformerpanel permits field selectionof system voltage and derivescontrol power from eitherpower source• Isolated Cam-Lokcompartment minimizesexposure to energizedtransfer switch compartment,enhancing worker safety• Lockable doors preventunauthorized access• Removable gland plate(underside) exposes openingsfor ingress of source 1 (utility)and load cables• Door safety interlock(automatic operation models)mitigates risk of unintentionalcable disconnect fromCam-Lok receptacle whensource 2 power is live andconnected to the load• Hinged bottom flap securesin closed position whencables are not present• “Field conversion ready” forconnection of permanentgenerator (future)• Mechanically interlockedto prevent simultaneousconnection of both sourcesFirst transfer switch is equipped with Cam-Lok receptacles for quick connection to a temporary roll-up generator (during maintenance of the permanent generator) and feeds a second transfer switch. First transfer switch provides compliance to NEC T Article 700.3(F) in an emergency system.T ransfer switch equipped with Cam-Lok receptacles for quick connection to a temporary roll-up generator during a utility power outage.1000 A Cam-Lok power panel with25% ground ampacityEaton is a registered trademark.All other trademarks are property of their respective owners.Eaton1000 Eaton Boulevard Cleveland, OH 44122United States © 2021 EatonAll Rights Reserved Printed in USAPublication No. SA140012EN / Z25600October 2021Product selectionCatalog numbering systemAA Dimensions are approximate, applicable for standard product configuration, and subject to change. Please reference product outline drawings for the latest detailed information.Information provided is for open transition, three‐pole, 480 V configuration. For weights—consult with factory.B Suitable for copper conductor termination. Alternate lug terminal sizes are available for some configurations—consult with factory.C Terminal connection size listed is for a product configuration with a solid neutral. For product configurations with a switched neutral (four‐pole), reference the size listed in the loadterminal connection column.D Applies to two‐pole, single‐phase voltage configurations (240/120 V or 208/120 V) with ATC‐300+ controller only.E Normal terminal connections configured for 3/0–350.A Limited to 600 A and below.B 304 or 316 grade stainless steel available.Custom orderingIn many cases, standard products can be custom- order engineered to meet your application needs. For additional information, please contact your local Eaton sales representative.Follow us on social media to get the latest product and support information.。
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MultiMediaCard SpecificationVersion : Ver. 0.9Date 4 – June - 2004Samsung Electronics Co., LTDSemiconductor Flash Memory Product Planning & Applications1 Introduction to the MultiMediaCard ----------------------------------------------------------- 51.1 System Features ----------------------------------------------------------------------------------------- 5-------------------------------------------------------------------------------------- 51.2 ProductModel2 Function Description ------------------------------------------------------------------------------- 72.1 Flash Technology Independence ------------------------------------------------------------------ 72.2 Defect and Error Management --------------------------------------------------------------------- 72.3 Endurance ----------------------------------------------------------------------------------------------- 72.4 Automatic Sleep Mode ------------------------------------------------------------------------------- 72.5 Hot Insertion -------------------------------------------------------------------------------------------- 82.6 MultiMediaCard Mode -------------------------------------------------------------------------------- 82.6.1 MultiMediaCard Standard Compliance ----------------------------------------------------------- 82.6.2 Negotiation Operation Conditions ----------------------------------------------------------------- 82.6.3 Card Acquisition and Identification ---------------------------------------------------------------- 82.6.4 Card Status ---------------------------------------------------------------------------------------------- 82.6.5 Memory Array Partitioning --------------------------------------------------------------------------- 92.6.6 Read and Write Operations ------------------------------------------------------------------------- 92.6.7 Data Transfer Rate ------------------------------------------------------------------------------------102.6.8 Data Protection in the Flash Card -----------------------------------------------------------------10-----------------------------------------------------------------------------------------------------10 2.6.9 Erase2.6.10 Write Protection ----------------------------------------------------------------------------------------102.6.11 Copy Bit ------------------------------------------------------------------------------------------------- 102.6.12 The CSD Register ------------------------------------------------------------------------------------ 112.7 SPI Mode ----------------------------------------------------------------------------------------------- 112.7.1 Negotiating Operation Conditions ---------------------------------------------------------------- 112.7.2 Card Acquisition and Identification --------------------------------------------------------------- 112.7.3 Card Status --------------------------------------------------------------------------------------------- 112.7.4 Memory Array Partitioning -------------------------------------------------------------------------- 112.7.5 Read and Write Operations ------------------------------------------------------------------------- 112.7.6 Data Transfer Rate ------------------------------------------------------------------------------------ 112.7.7 Data Protection in the MultiMediaCard ----------------------------------------------------------- 1212-----------------------------------------------------------------------------------------------------2.7.8 Erase2.7.9 Write Protection ---------------------------------------------------------------------------------------- 123 Product Specifications ----------------------------------------------------------------------------- 133.1 Recommended Operating Conditions ------------------------------------------------------------------------- 133.2 Operating Characteristis ----------------------------------------------------------------- 143.3 System Environmental Specifications ----------------------------------------------------------------- 153.4 System Reliability and Maintenance -------------------------------------------------------------- 153.5 Physical Specifications ------------------------------------------------------------------------------- 164 MultiMediaCard Interface Description --------------------------------------------------------- 174.1 Pin Assignments in MultiMediaCard Mode ------------------------------------------------------- 174.2 Pin Assignments in SPI Mode ---------------------------------------------------------------------- 184.3 MultiMediaCard Bus Topology ---------------------------------------------------------------------- 184.4 SPI Bus Topology -------------------------------------------------------------------------------------------------- 194.4.1 SPI Interface Concept ------------------------------------------------------------------------------------------- 194.4.2 SPI Bus Topology ------------------------------------------------------------------------------------------------ 1920------------------------------------------------------------------------------------------------- 4.5 Registers4.5.1 Operation Condition Register (OCR) ---------------------------------------------------------------------------204.5.2 Card Identification (CID) ------------------------------------------------------------------------------214.5.3 Relative Card Address (RCA) ----------------------------------------------------------------------- 21 4.5.4 Card Specific Data (CSD) ---------------------------------------------------------------------------- 22 4.6 MultiMediaCard Communication -------------------------------------------------------------------- 3030----------------------------------------------------------------------------------------------- 4.6.1 Commands4.7 Read, Write and Erase Time-out Conditions ----------------------------------------------------- 33 4.8 Card Identification Mode ------------------------------------------------------------------------------ 34 4.8.1 Operating Voltage Range Validation --------------------------------------------------------------- 35 4.9 Data Transfer Mode ------------------------------------------------------------------------------------ 35 4.9.1 Block Read ----------------------------------------------------------------------------------------------- 37 4.9.2 Block Write ----------------------------------------------------------------------------------------------- 3738------------------------------------------------------------------------------------------------------ 4.9.3 Erase4.9.4 Write Protect Management -------------------------------------------------------------------------- 38 4.9.5 Card Lock/Unlock Operation ------------------------------------------------------------------------ 38----------------------------------------------------------------------------------------------- 41 4.9.6 Responses4.9.7 Status ------------------------------------------------------------------------------------------------------ 42 4.9.8 Command Response Timing ------------------------------------------------------------------------ 4448 4.9.9 Reset------------------------------------------------------------------------------------------------------ 4.10 SPI Communication ----------------------------------------------------------------------------------- 49 4.10.1 Mode Selection ----------------------------------------------------------------------------------------- 49 4.10.2 Bus Transfer Protection ------------------------------------------------------------------------------ 49 4.10.3 Data Read Overview ---------------------------------------------------------------------------------- 50 4.10.4 Data Write Overview ---------------------------------------------------------------------------------- 51 4.10.5 Erase and Write Protect Management ----------------------------------------------------------- 52 4.10.6 Reading CID/CSD Registers ------------------------------------------------------------------------ 53 4.10.7 Reset Sequence --------------------------------------------------------------------------------------- 53 4.10.8 Error Conditions ---------------------------------------------------------------------------------------- 53 4.10.9 Memory Array Partitioning --------------------------------------------------------------------------- 53 4.10.10 Card Lock/Unlock -------------------------------------------------------------------------------------- 53 4.10.11 Commands ----------------------------------------------------------------------------------------------- 54 4.10.12 Responses ----------------------------------------------------------------------------------------------- 56 4.10.13 Data Tokens --------------------------------------------------------------------------------------------- 58 4.10.14 Data Error Token --------------------------------------------------------------------------------------- 59 4.10.15 Clearing Status Bits ------------------------------------------------------------------------------------ 60 4.11 SPI Bus Timing ----------------------------------------------------------------------------------------- 61 4.12 Error Handling ------------------------------------------------------------------------------------------ 64 4.12.1 Error Correction Code (ECC) ----------------------------------------------------------------------- 64 4.12.2 Cyclic Redundancy Check (CRC) ----------------------------------------------------------------- 642 Function Description2.1 Flash Technology IndependenceThe 512 byte sector size of the MultiMediaCard is the same as that in an IDE magnetic disk drive. To write or read a sector (or multiple sectors), the host computer software simply issues a Read or Write command to the MultiMediaCard. This command contains the address and the number of sectors to write/read. The host software then waits for the command to complete. The host software does not get involved in the details of how the flash memory is erased, programmed or read. This is extremely important as flash devices are expected to get more and more complex in the future. Because the MultiMediaCard uses an intelligent on-board controller, the host system software will not require changing as new flash memory evolves. In other words, systems that support the MultiMediaCard today will be able to access future MultiMediaCards built with new flash technology without having to update or change host software.2.2 Defect and Error ManagementMultiMediaCards contain a sophisticated defect and error management system. This system is analogous to the systems found in magnetic disk drives and in many cases offers enhancements. For instance, disk drives do not typically perform a read after write to confirm the data is written correctly because of the performance penalty that would be incurred. MultiMediaCards do a read after write under margin conditions to verify that the data is written correctly (except in the case of a Write without Erase Command). In the rare case that a bit is found to be defective, MultiMediaCards replace this bad bit with a spare bit within the sector header. If necessary, MultiMediaCards will even replace the entire sector with a spare sector. This is completely transparent to the host and does not consume any user data space.The MultiMediaCards soft error rate specification is much better than the magnetic disk drive specification. In the extremely rare case a read error does occur, MultiMediaCards have innovative algorithms to recover the data. This is similar to using retries on a disk drive but is much more sophisticated. The last line of defense is to employ powerful ECC to correct the data. If ECC is used to recover data, defective bits are replaced with spare bits to ensure they do not cause any future problems.These defect and error management systems coupled with the solid-state construction give MultiMediaCards unparalleled reliability2.3 EnduranceMultiMediaCards have an endurance specification for each sector of 1,000,000 writes (reading a logical sector is unlimited). This is far beyond what is needed in nearly all applications of MultiMediaCards. Even very heavy use of the MultiMediaCard in cellular phones, personal communicators, pagers and voice recorders will use only a fraction of the total endurance over the typical device’s five year lifetime. For instance, it would take over 100 years to wear out an area on the MultiMediaCard on which a files of any size (from 512 bytes to capacity) was rewritten 3 times per hour, 8 hours a day, 365 days per year.With typical applications the endurance limit is not of any practical concern to the vast majority of users.2.4 Automatic Sleep ModeAn important feature of the MultiMediaCard is automatic entrance and exit from sleep mode. Upon completion of an operation, the MultiMediaCard will enter the sleep mode to conserve power if no further commands are received within 5 msec The host does not have to take any action for this to occur. In most systems, the MultiMediaCard is in sleep mode except when the host is accessing it, thus conserving power. When the host is ready to access the MultiMediaCard and it is in sleep mode, any command issued to the MultiMediaCard will cause it to exit sleep and respond. The host does not have to issue a reset first. It may do this if desired, but it is not needed. By not issuing the reset, performance is improved through the reduction of overhead.2.5 Hot InsertionSupport for hot insertion will be required on the host but will be supported through the connector. Connector manufacturers will provide connectors that have power pins long enough to be powered before contact is made with the other pins. Please see connector data sheets for more details. This approach is similar to that used in PCMCIA to allow for hot insertion. This applies to both MultiMediaCard and SPI modes.2.6 MultiMediaCard Mode2.6.1 MultiMediaCard Standard ComplianceThe MultiMediaCard is fully compliant with MultiMediaCard standard specification V3.31.The structure of the Card Specific Data (CSD) register is compliant with CSD structure V1.2.2.6.2 Negotiating Operation ConditionsThe MultiMediaCard supports the operation condition verification sequence defined in the MultiMediaCard standard specifications. The MultiMediaCard host should define an operating voltage range that is not supported by the MultiMediaCard. It will put itself in an inactive state and ignore any bus communication. The only way to get the card out of the inactive state is by powering it down and up again. In addition the host can explicitly send the card to the inactive state by using the GO_INACTIVE_STATE command.2.6.3 Card Acquisition and IdentificationThe MultiMediaCard bus is a single master (MultiMediaCard host) and multi-slaves (cards) bus. The host can query the bus and find out how many cards of which type are currently connected. The MultiMediaCard’s CID register is pre-programmed with a unique card identification number which is used during the acquisition and identification procedureIn addition, the MultiMediaCard host can read the card’s CID register using the READ_CID MultiMediaCard command. The CID register is programmed during the MultiMediaCard testing and formatting procedure, on the manufacturing floor. The MultiMediaCard host can only read this register and not write to it.2.6.4 Card StatusMultiMediaCard status is stored in a 32 bit status register which is sent as the data field in the card respond to host commands. Status register provides information about the card’s current state and completion codes for the last host command. The card status can be explicitly read (polled) with the SEND_STATUS command.2.6.7 Data Protection in the Flash CardEvery sector is protected with an Error Correction Code (ECC). The ECC is generated (in the memory card) when the sectors are written and validated when the data is read. If defects are found, the data is corrected prior to transmission to the host.The MultiMediaCard can be considered error free and no additional data protection is needed. However, if an application uses additional, external, ECC protection, the data organization is defined in the user writeable section of the CSD register2.6.8 EraseThe smallest erasable unit in the MultiMediaCard is a erase group. In order to speed up the erase procedure, multiple erase groups can be erased in the same time. The erase operation is divided into two stages.Tagging - Selecting the Sectors for ErasingTo facilitate selection, a first command with the starting address is followed by a second command with the final address, and all erase groups within this range will be selected for erase.Erasing - Starting the Erase ProcessTagging can address erase groups. An arbitrary selection of erase groups may be erased at one time. Tagging and erasing must follow a strict command sequence (refer to the MultiMediaCard standard specification for details).2.6.9 Write ProtectionThe MultiMediaCard erase groups are grouped into write protection groups. Commands are provided for limiting and enabling write and erase privileges for each group individually. The current write protect map can be read using SEND_WRITE_PROT command.In addition two, permanent and temporary, card levels write protection options are available.Both can be set using the PROGRAM_CSD command (see below). The permanent write protect bit, once set, cannot be cleared.The One Time Programmable (OTP) characteristic of the permanent write protect bit is implemented in the MultiMediaCard controller firmware and not with a physical OTP cell.2.6.10 Copy BitThe content of an MultiMediaCard can be marked as an original or a copy using the copy bit in the CSD register. Once the Copy bit is set (marked as a copy) it cannot be cleared.The Copy bit of the MultiMediaCard is programmed (during test and formatting on the manufacturing floor) as a copy. The MultiMediaCard can be purchased with the copy bit set (copy) or cleared, indicating the card is a master.The One Time Programmable (OTP) characteristic of the Copy bit is implemented in the MultiMediaCard controller firmware and not with a physical OTP cell.2.6.11 The CSD RegisterAll the configuration information of the MultiMediaCard is stored in the CSD register. The MSB bytes of the register contain manufacturer data and the two least significant bytes contains the host controlled data - the card Copy and write protection and the user ECC register.The host can read the CSD register and alter the host controlled data bytes using the SEND_CSD and PROGRAM_CSD commands.2.7 SPI ModeThe SPI mode is a secondary (optional) communication protocol offered for MultiMediaCard. This mode is a subset of the MultiMediaCard protocol, designed to communicate with an SPI channel, commonly found in Motorola’s (and lately a few other vendors’) microcontrollers.2.7.1 Negotiating Operation ConditionsThe operating condition negotiation function of the MultiMediaCard bus is not supported in SPI mode. The host must work within the valid voltage range (2.7 to 3.6 volts) of the card.2.7.2 Card Acquisition and IdentificationThe card acquisition and identification function of the MultiMediaCard bus is not supported in SPI mode. The host must know the number of cards currently connected on the bus. Specific card selection is done via the CS signal.2.7.3 Card StatusIn SPI mode only 16 bits (containing the errors relevant to SPI mode) can be read out of the MultiMediaCard status register.2.7.4 Memory Array PartitioningMemory partitioning in SPI mode is equivalent to MultiMediaCard mode. All read and write commands are byte addressable.2.7.5 Read and Write OperationsIn SPI mode, only single block read/write mode is supported.2.7.6 Data Transfer RateIn SPI mode only block mode is supported. The typical access time (latency) for each data block, in read operation, is 1.5mS. The write typical access time (latency) for each data block, in read operation, is 1.5mS. The write block operation is done in handshake mode. The card will keep DataOut line low as long as the write operation is in progress and there are no write buffers available.2.7.7 Data Protection in the MultiMediaCardSame as for the MultiMediaCard mode.2.7.8 EraseSame as in MultiMediaCard mode2.7.9 Write ProtectionSame as in MultiMediaCard modeFigure 3-1 Timing Diagram of Data Input and Output3.5 Physical SpecificationsDimensions of Normal MMC(24mm x 32mm x 1.4mm)Dimensions of RS-MMC(24mm x 18mm x 1.4mm)rising and falling edges). If the host does not allow the switchable R OD implementation, a fix R CMD can be used. Consequently the maximum operating implementation, a fix R CMD can be used. Consequently the maximum operating frequency in the open drain mode has to be reduced in this case.4.4 SPI Bus Topology4.4.1 SPI Interface ConceptThe Serial Peripheral Interface (SPI) is a general-purpose synchronous serial interface originally found on certain Motorola micro-controllers. The MultiMediaCard SPI interface is compatible with SPI hosts available on the market. As any other SPI device the MultiMediaCard SPI channel consists of the following 4 signals:- CS : Host to card chip select signal- CLK : Host to card clock signal- DataIn : Host to card data signal- DataOut : Card to host data signalAnother SPI common characteristic, which is implemented in the MultiMediaCard card as well, is byte transfers. All data tokens are multiples of 8 bit bytes and always byte aligned to the CS signal. The SPI standard defines the physical link only and not the complete data transfer protocol. The MultiMediaCard uses a subset of the MultiMediaCard protocol and command set.4.4.2 SPI Bus TopologyThe MultiMediaCard card identification and addressing algorithms are replaced by hardware Chip Select (CS) signal. There are no broadcast commands. A card (slave) is selected, for every command, by asserting (active low) the CS signal (see Figure 4-3). The CS signal bust is continuously active for the duration of the SPI transaction (command, response and data). The only exception is card-programming time. At this time the host can de-assert the CS signal without affecting the programming process. The bi-directional CMD and DAT lines are replaced by unidirectional dataIn and dataOut signals. This eliminates the ability of executing commands while data is being read or written and, therefore, eliminates the sequential and multi block read/write operations. The SPI channel supports only single block read/write.Figure 4-3 SPI Bus SystemReadThe read access time is defined as the sum of the two times given by the CSD parameters TAAC and NSAC (refer to Table “Card Specific Data (CSD)”). These card parameters define the typical delay between the end bit of the read command and the start bit of the data block. This number is card dependent and should be used by the host to calculate throughput and the maximal frequency for stream read.WriteThe R2W_FACTOR field in the CSD is used to calculate the typical block program time obtained by multiplying the read access time by this factor. It applies to all write/erase commands (e.g. SET(CLEAR)_WRITE_PROTECT, PROGRAM_CSD(CID) and the block write commands). It should be used by the host to calculate throughput.EraseThe duration of an erase command will be (order of magnitude) the number of sectors to be erased multiplied by the block write delay.4.8 Card Identification ModeAll the data communication in the card identification mode uses only the command line (CMD). MultiMediaCard State Diagram (Card Identification Mode)Figure 4-2 MultiMediaCard State Diagram (Card Identification Mode)The host starts the card identification process in open drain mode with the identification clock rate f OD(generated by a push pull driver stage). The open drain driver stages on the CMD line allow the parallel card operation during card identification. After the bus is activated the host will request the cards to send their valid operation conditions with the command SEND_OP_COND (CMD1). Since the bus is in open drain mode, as long as there is more than one card with operating conditions restrictions, the host gets in the response to the CMD1 a “wired or” operation condition restrictions of those cards. The host then must pick a common denominator for operation and notify the application that cards with out of range parameters (from the host perspective) are connected to the bus. Incompatible cards go into Inactive State (refer to also Chapter “Operating Voltage Range Validation”). The busy bit in the CMD1 response can be used by a card to tell the host that it is still working on its power-up/reset procedure (e.g. downloading the register information from memory field) and is not ready yet for communication. In this case the host must repeat CMD1 until the busy bit is cleared. After an operating mode is established, the host asks all cards for their unique card identification (CID) number with the broadcast command ALL_SEND_CID (CMD2).All not already identified cards (i.e. those which are in Ready State) simultaneously start sending their CID numbers serially, while bit-wise monitoring their outgoing bitstream. Those cards, whose outgoing CID bits do not match the corresponding bits on the command line in any one of the bit periods, stop sending their CID immediately and must wait for the next identification cycle (cards stay in the Ready State). There should be only one card which successfully sends its full CID-number to the host. This card then goes into the Identification State. The host assigns to this card (using CMD3, SET_RELATIVE_ADDR) a relative card address (RCA, shorter than CID), which will be used to address the card in future communication (faster than with the CID). Once the RCA is received the card transfers to the Standby State and does not react to further identification cycles. The card also switches the output drivers from the open-drain to the push-pull mode in this state. The host repeats the identification process as long as it receives a response (CID) to its identification command (CMD2). When no card responds to this command, all cards have been identified. The time-out condition to recognize this, is waiting for the start bit for more than 5 clock periods after sending CMD24.8.1 Operating Voltage Range ValidationThe MultiMediaCard standards operating range validation is intended to support reduced voltage range MultiMediaCards. The MultiMediaCard supports the range of 2.7 V to 3.6V supply voltage. So the MultiMediaCard sends a R3 response to CMD1 which contains an OCR value of 0x80FF8000 if the busy flag is set to “ready” or 0x00FF8000 if the busy flag is active (refer to Chapter “Responses”). By omitting the voltage range in the command, the host can query the card stack and determine the common voltage range before sending out-of-range cards into the Inactive State. This bus query should be used if the host is able to select a common voltage range or if a notification to the application of non usable cards in the stack is desired. Afterwards, the host must choose a voltage for operation and reissue CMD1 with this condition sending incompatible cards into the Inactive State.4.9 Data Transfer ModeWhen in Standby State, both CMD and DAT lines are in the push-pull mode. As long as the content of all CSD registers is not known, the f PushPull clock rate is equal to the slow f OpenDrain clock rate. SEND_CSD (CMD9) allows the host to get the Card Specific Data (CSD register), e.g. ECC type, block length, card storage capacity, maximum clock rate etc..。