What goes in FPGA of USRP1

What goes in FPGA?By Minglong Zhang For USRP1This section gives an analysis for USRP1’s hardware, including RF front end, AD/DA converter and FPGA. Certainly, the most important part is how signals are processed in FPGA.1.The entire hardware structure of the system is shown below:Fig. 1 The entire hardware structure of USRP12.RF front endIn a radio receiver circuit, the RF front end is a generic term for all the circuitry between the antenna and the first intermediate frequency (IF) stage. It consists of all the components in the receiver that processes the signal at the original incoming radio frequency (RF), before it is converted to a lower intermediate frequency. The RF front end usually consists of following components, as shown in Fig. 2:(1) An impedance matching circuit to match the input impedance of the receiver with the antenna, so the maximum power is transferred from the antenna;(2) A band-pass filter (BPF) to reduce input noise and image frequency response;(3) An RF amplifier often called the low-noise amplifier (LNA). Its primary responsibility is to increase the sensitivity of the receiver by amplifying weak signals without contaminating them with noise, so they are above the noise level in succeeding stages. It must have a very low noise figure;(4) The mixer, which mixes the incoming signal with the signal from a local oscillator (LO) to convert the signal to the intermediate frequency.Fig. 2. A general receiver path of the RF front endIn USRP1 system, the RF front end is on daughterboard and has a similar structure as Fig. 2 shown. It consists of several ASICs, including HWS383, IRM046U7 and MAX2829ETN, which act as transmit/receive combination, amplifier and mixer, independently. The whole receiving and transmitting path in our system is shown below (take an example by XCVR2450):Fig.3. The whole receiving and transmitting path in USRP1NOTE: AD9862 is a powerful chip that can complete AD/DA converting and digital up converting 3.DDCThe main responsibility of the FPGA is translating broadband IF signals into baseband signals. It acts as a digital down converter (DDC). Besides, it also completes a part of tasks of a digital up converter (DUC) and the remnant parts of the DUC are implemented by the chip AD9862. Figure 4 depicts all main modules in FPGA. It includes a DDC and an interpolator, which is a part of DUC. More importantly, its structure is configurable for user. It could contain four DDCs and two interpolators at most. All those were described by hardware description language (HDL) Verilog. The code files are approximately 6000 lines. The following section will analyze these modules one by one. In the end, we will provide a synthesis report from which we can evaluate hardware complexity.Fig. 4. Main modules in the FPGALet us make a deep analysis for each module and show not only their inner structures but also principles and algorithms.(1)Adc_interfaceThis module is an interface between the chip AD9862 and DDC. It contains 4 sub-modules: sr_rxmux, rssi_block, rx_dcoffset and sr_dco_en.For the module sr_rxmux, because there are two AD9862 chips on the motherboard and each contains two ADCs, it looks like a switcher that determines which ADC is connected to DDC. Users can control this switcher in their Python programs by using usrp.set_mux(). On the side of hardware, we define many special registers to save these values set by software. The hardware programs could read those registers via memory mapping and generate the corresponding circuits.For module sr_dco_en and rx_dcoffset, the former generates enable signals for the latter which accompanies automatic DC offset correction control loop. The DC offset correction works if the attached daughterboard blocks DC. This includes basic rx, dbs_rx, tv_rx and flex_xxx_rx. So its register needs to be set by software programs. In terms of rssi_block, it is actually an automatic gain controller (AGC). Sometimes sampling data from ADC is too high or too low. We need to adjust them in order to improve processing precision for the subsequent modules.(2)Rx_chainThis is the most important and complicated module in our hardware system. It firstly multiplies the input IF complex signals by a local IF signal generated by a numerically controlled oscillator (NCO). Then it uses a cascaded integrator comb (CIC) decimator and a half band filter (HBF) to complete low-pass filtering and decimating simultaneously. It consists of four sub-modules: phase_acc, cordic, CIC_decimator and halfband filter.Here we utilize module phase_acc and cordic to construct a NCO which could calculate the sine and cosine value of the input phase. In order to avoid using look up tables and multipliers, the NCO adopts a CORDIC algorithm to generate local IF signals. The following is a brief introduction to the CORDIC algorithm:In figure 5, suppose vector BB�⃗can be obtained by rotating vector AA⃗, it can be expressed by equation (1) or (2):�x n=x0 cosz0−y0 sinz0y n=y0 cosz0+x0 sinz0 (1) �x n=cosz0(x0 −y0 tanz0)y n=cosz0(y0 +x0 tanz0) (2) Assume rotating vector AA⃗by n times can reach vector BB�⃗and the i th rotating angle equal to tan-12-i, so we can obtain a rotating equation for the i th rotating:(3) Where d i stands for rotating direction and equals 1 or -1 for anticlockwise or clockwise direction.After iterating this equation by n times, it can be express by (4), where K is a constant while n is large enough.(4)Fig. 5. Rotating vector AA ⃗ to vector BB �⃗ If the initial vector is (x, 0), after iterating, the final result is:�x n =x cosz 0y n =x sinz 0 (5) So if x is the signal that needs to be demodulated, the outputs are two orthotropic signals I and Q. From the equation (3), we know that we can realize this procedure only by adders and shifters. It can save a lot of hardware logic resources.The module phase_acc provides an initial phase to the module cordic at the beginning of each computation and then the module cordic completes the whole iteration shown by equation (3). In this system, it employs a pipeline structure to carry out twelve-stage iterations.CIC_decimator is a high efficiency low-pass filter and able to decimate input data by aconfigurable parameter N. The range of N is [1,255]. In order to understand its feature, the following is a brief introduction to its function and structure.Its impulse response can be expressed as below:h (n) = �1, 0≤n ≤D −10 , other (6) Where D is the decimation parameterTranslating it in the Z domain:H(z) = ∑ ℎ(nn ) zz−nn DD−1nn =0 = 1−zz −DD1−zz = H 1(z) H 2(z) (7) Where H 1(z) = 11−zz and H 2(z) = 1-z -DComputing its frequency response H(e jw ) as below:HH�ee jj jj�=sin⁡(jjDD2)sin⁡(jj2)ee jj jj(1−DD) (8) So its structure can be described by Fig. 6. Using Matlab we can plot its magnitude and phase spectrum curves, as shown in Fig. 7.Fig. 6. CIC filter’s inner structureFig. 7. CIC filter magnitude and phase spectrumObviously, for only one stage CIC filter, the difference between the main lobe and the first side lobe is approximately only 13dB. It is difficult to meet our requirement. However, if we use a Q stage cascaded CICs, the magnitude frequency response is: �HH QQ�ee jj jj��=�sin⁡(jjDD2)sin⁡(jj)�QQ (9) For Q = 5, its spectrum is shown in Fig. 8.Fig. 8. Five cascaded CIC filter magnitude and phase spectrumFrom Fig. 8, we can estimate the difference between the main lobe and the first side lobe is about 65dB. Generally, four or five stages are enough for engineering use, too many stages may lead to attenuation of the passband signals.For a one-stage CIC decimator, its structure and its equivalent one is shown by Fig. 9.Fig. 9. One-stage CIC decimator’s structureSimilarly, Fig. 10 shows the n-stage CIC decimator’s equivalent structure:Fig. 10. n-stage CIC decimatorIn our system, there is a four-stage CIC decimator with a configurable decimation parameter . Module CIC_decimator adopts a similar structure as Fig.10 shows.In fact, our main purpose is to decimate the input data, but why we use a CIC decimator instead of a direct decimator? The reason is that it can avoid aliasing. Suppose x(n) is input samples, after decimating, it forms a new sequence x D (m), where x D (m) = x(mD). Assume x(e jw ) is x(n)’s Fourier transform, soxx DD (ee jj jj )=1DD ∑xx [ee jj (jj −2ππππ)DD ]DD−1ππ=0 (10)From the Fig. 11, we find that decimation may lead to spectrum extension. So there are spectrum aliasing phenomena for x D (e jw ).Fig. 11. spectrum aliasing after decimationIf we carry out low pass filtering before decimating, there is no spectrum aliasing for x D (e jw ). This process is shown by Fig. 12.Fig. 12. Low pass filtering before decimation can avoid spectrum aliasingHalfband filter is the last module in module rxchain. This design implements a 31-tap halfband filter that decimates by 2. Halfband filter is a special FIR filter. Its frequency response H(e jw) can be expressed by equation (11). Its magnitude spectrum is shown in Fig. 13.�jj AA=ππ−jj ccδδss=δδpp=δδ (11) Where w c is pass band width, π- w A is stop band width, δp is pass band ripple and δs is stop band ripple.Fig. 13. Halfband filter magnitude spectrumIn time domain, its impulse response has the following characteristic:h(n) = 0 , where n=±2, ±4, ±6,…,and n≠0. (12) Because the halfband filter is a kind of FIR filter, so we can design it by using the same method as designing a FIR filter. As we known, each output of a FIR filter is determined by the following convolution equation:NN−1mm=0=ℎ(nn)∗xx(nn) (13)yy(nn)=∑ℎ(mm)xx(nn−mm)Where h(m) is the coefficient and N is the filter’s tap number. It can be carried out by the following hardware structure, as shown by Fig. 14:Fig. 14. Structure of a FIR filterIn terms of our system’s halfband filter, it has 31 taps corresponding to 31 coefficients. The coefficients are symmetric, and with the exception of the middle tap, every other coefficient is zero. The taps are scaled relative to 32768, thus the middle tap equals 1.0. Not counting the middle tap, there 8 non-zero taps on each side, and they are symmetric. Because of symmetry, for each two symmetric non-zero taps, we can replace 2 multipliers with one adder and one multiplier. Thus, to compute each output sample, we need to perform 8 multiplications. Since the middle tap’s coefficient is 1, we just add the corresponding delay value.We can save all coefficients in a ROM in advance. In this implementation, there is only one multiplier, so it takes 8 clock cycles to compute a single output. However, since we are decimating by two we can accept a new input sample every 4 cycles. We use two block rams to store the data, one for even samples and one for odd samples. So the ram acts as a delay line. The odd one is written on each odd sequence and read on each clock when we are computing the final output. The even ram works similarly, although because it holds the even samples we must be able to read two samples from different addresses at the same time, while writing the incoming even samples. By using this structure, we can obtain the even output values every 8 cycles with a simple control logic.There are 5 sub-modules contained in the top module halfband filter: coeff_rom, ram16_even, ram16_odd, mult and acc, which are responsible for storing coefficients, even input samples and odd input samples, multiplying and calculating the final sum. (3)RX_bufferThis module is an interface to USB controller Cpress FX2 bus and used to buffer the data from RX_chain. It uses a fifo to store data and the fifo has 4096 lines of 18bits each. Each packet sent to USB is 512 bytes, so the buffer’s capacity is 8192 bytes or 16 packets. When there is more than one receive channel, the buffer adopt a round-robin strategy and service each channel for 2 bytes. In the end, it output stored data in an interlaced pattern, such as, I0, Q0, I1, Q1, I2, Q2...(4)TX_chainIt works like the module RX_chain, but in an inverse way. It buffers data from USB controller and then uses a CIC interpolator to improve resolution. There are two sub-modules in the TX_chain: TX_buffer and CIC interpolator.TX_bufferThis module connects the USB controller and a CIC interpolator . It saves data from USB into a fifo. The fifo has the same capacity of the RX_buffer . It can accept two pair of signals at most. So it has four output data ports, and the sending sequence is tx_i_0, tx_q_0, tx_i_1, tx_q_1…CIC interpolatorInterpolation is an inverse process to decimation. As we known, the latter may lead to spectrum extension, so the former may cause spectrum compression. However , there is no aliasing in this process. Assume the initial sample sequence is x(n), so afterinterpolating, the sequence x I (m) can be expressed by:X(m/I), m = 0, ±I,±2I…x I (m) = (14) 0, otherIf x(e jw ) is the discrete Fourier transform of x(n), so we can obtain x I (e jw ) = x(e jwI ). Fig. 15 shows their spectrum. Fig. 15(a) is the original spectrum before interpolation. Fig. 15(b) shows that the spectrum has been compressed by I times after interpolation. Although there is no aliasing, it brings high frequency harmonic to the original spectrum. Fig. 15(c) shows that by using low pass filter , we can get baseband components.Fig. 15. Spectrum compression after interpolationFor a CIC interpolator , since it works inversely comparing with a CIC decimator , so we can educe its structure easily, as below.Fig.16. structure of CIC interpolatorIn this design, we implement a 4 stage CIC interpolator as shown in Fig. 16. The output data is directly sent to AD9862, which contains low pass filters and modulators. In the end, orthotropic data is sent to DACs.(5)Serial_io and master controlAll modules described above are only responsible for signal processing. They can accompany all that we need. However, the whole system still lacks a control module to make them work in order. The module master control mainly outputs control signals for different modules. Those signals include decimation and interpolation rate, reseting, enable, sample strobe, decimation strobe and so on. Serial_io is an interface between USB controller and FPGA. Its function is just to read and write special registers from/to SPI bus. Those registers are configuration registers and used to provided control signals, such as which ADC or DAC has been selected, user’s setup, feedback for AGC and some debug tri-state ports for debug purpose.4.Hardware complexityIn order to understand DDC’s hardware complexity, we download all Verilog code files from website of USRP and carry out synthesis. Because there is no Quartus II, we use ISE 10.1 instead. Please note that it will not affect us to evaluate the complexity. .The FPGA’s type is ALTERA Cyclone EP1C12Q240C8N. Table 1 is the logic resource utilization summary for USRP1.From the table, we find that, for hardware logic, USRP1 is not very complicated. This is because some functions have been transferred to software or ASICs outside. However, for a high-performance DDC, it is still need to be improved. For example, we can insert a 128-tap low-pass FIR filter and an all-pass compensation filter between RX_chain and RX_buffer. By this, it can filter out more high-frequency harmonics without reducing baseband signals.For USRP2For hardware complexity in FPGA, USRP2 is more complicated than USRP1. This conclusion can be intuitively demonstrated by synthesis report. We use the same FPGA and development tool ISE10.1 to make a comparison. Note that here the FPGA’s type is XILINX Spartan-3 XC3S2000-5fg456 which is used in USRP2. Fig. 17(a) and (b) show USRP1 logic resource utilization summary and timing summary, independently. Fig. 18(a) and (b) show USRP2 logic resource utilization summary and timing summary, independently.Fig.17(a). USRP1 synthesis report for resource utilization summaryFig.17(b). USRP1 synthesis report for timing summaryFig.18(a). USRP2 synthesis report for resource utilization summaryModules analysis for USRP2 will come soon ...1)The report focuses on the signal processing part, such as down-conversion from IF to BB. Isuppose this is the main function of FPGA. If we need to change the down-conversion process in the future, we may need to understand this part thoroughly. Currently, I do not see any reason to do so, unless we feel that the down-conversion by the FPGA is not good enough for what we aim to achieve. Lu Lu, is this assessment correct?Firstly, compared to other DDC systems based upon FPGA, this design lacksa FIR filter. We can insert a 128-tap low-pass FIR filter and an all-passcompensation filter between RX_chain and RX_buffer. By this, it can filter out more high-frequency harmonics without reducing baseband signals.Secondly, USRP1’s hardware logic has included a whole DUC. However, it is disabled currently. It only uses a CIC interpolator and other functions are carried out in AD9862.2)More important, I think, is the control part. How different modules are fit together? Can weinsert MAC functionality, such as carrier sensing into FPGA? Is the hardware powerful enough for this to be achieved? I read somewhere that WARP is more powerful in that regard.●For the control section in FPGA, several points need to be added here:○1FPGA is controlled by FX2 via special registers. All communications between FPGA and FX2 rely on SPI bus. The FX2 receive control signals from PC and then set corresponding registers on SPI. FPGA can read those registers through SPI bus and then generates control signals. For the user, we can obtain some information by read the FX2. However, the FPGA registers are write-only. When reading, instead of the register contents, you get 'readback' register contents which are actually a number of useful signals inside the FPGA, mostly for reading I/O pins and RSSI levels.○2Module master control has 4 sub-modules: setting_reg, strobe_gen, clk_divider and atr_delay.⏹setting_reg is used to write control registers and then generatescontrol signals according to these registers. These control signalsinclude receive/transmit enable and reset, decimation/interpolationrate, reference clocks’frequency for daughterboard, FPGA debugenable and automatic transmit/receive switching control.⏹strobe_gen can generate strobe signals for the modules CIC decimatorand CIC interpolator according to decimation/interpolation rate setby users in software programs.⏹Clk_divider is used to generate a reference clock for daughterboardaccording to the frequency set by users.⏹Atr_delay set a delay time to transmit data to daughterboard. Thisallows someone (from Python) to manually adjust the timing offset ofthe auto-transmit/receive switching to better align with the transmitted data when using an external transmit/receive switch.For inserting a MAC layer in the existing FPGA, I think we should consider this problem from following aspects:○1Hardware logic resources limitation. From Table 1 and Fig. 18, we can learn about how many logic cells are left to us. Generally, if resource utilization ratio exceeded 85%, it would be difficult to map and translate our design into FPGA or meet our timing constraint. For USRP2, only 10% is left to us.○2The complexity of the MAC functionality. On the one hand, a full-function MAC in 802.11 may be a very complicated system and it may take a long time to develop it. On the other hand, we can simplify it. We should seriously discuss how to simplify it and write a technical document before developing it. However, compared with other MAC layer in 802.11, if there is no new function in our inserted MAC, we can realize it quickly by using an IP core based on FPGA. There are various such IP cores provided by XILINX and other similar corporations. Of course, it should not exceed the FPGA’s resource limitation after inserting it.3)Why are there four ADCs in USRP1? Which one is used by default usually?There are two AD9862 on our motherboard of USRP1. Each AD9862 contains two 12-bit ADCs. In the FPGA, Four input ports are corresponding to them. A configurable switch controls which ADC connect with an input port.4)To Lu Lu/ Taotao: Did we play with the AGC in the ADC_Interface mentioned in this report?According to some documents of USRP1, there are two kinds of AGCs: Analog AGC and digital AGC. In my report, it only involves the digital one. Its signals are limited in FPGA and it is not disabled currently. However, the analog AGC is disabled in our system.。