MCZ33993EWR2中文资料

MULTIPLE SWITCH DETECTION INTERFACE
The 33993 device has two modes of operation, Sleep and Normal. The Sleep mode provides low quiescent current and enables the wake-up features of the device. Normal mode allows programming of the device and supplies switch contacts with pull-up or pull-down current as it monitors switch change of state.
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 2. Maximum Ratings
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device.
Switch-to-ground input pins.
Battery supply input pin. Pin requires external reverse battery protection.
Wake-Up
Open drain wake-up output. Designed to control a power supply enable pin.
VPWR VDD GND
VPWR VPWR
16.0
2.0
mA
mA
SP7
16.0 mA
2.0 mA
4.0 V Ref
+ –
To SPI
Comparator
VPWR VPWR
16.0
2.0
mA
mA
SG0
5.0 V VPWR
4.0 V Ref
+ –
To SPI
Comparator
VPWR VPWR
16.0
• Pb-Free Packaging Designated by Suffix Code EW
VBAT VBAT
VBAT
33993
SP0 SP1
VPWR
SP7
SG0 SG1
VDD
WAKE SI
SCLK CS SO INT
AMUX
VDD
Power Supply LVI
Enable
Watchdog
VDD
© Freescale Semiconductor, Inc., 2003-2007. All rights reserved.
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INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
SP0 SP1 SP2 SP3 SP4 SP5 SP6 SP7
Protocol • Selectable Wake-Up on Change of State
Device
MC33993DWB/R2 MCZ33993EW/R2
Temperature Range (TA)
-40°C to 125°C
Package 32 SOICW
• Selectable Wetting Current (16 mA or 2.0 mA)
Features
DW SUFFIX EK SUFFIX (PB-FREE)
98ARH99137A 32-PIN SOICW
ORDERING INFORMATION
• Designed to Operate 5.5 V ≤ VPWR ≤ 26 V • Switch Input Voltage Range -14 V to VPWR, 40 V Max • Interfaces Directly to Microprocessor Using 3.3 V/5.0 V SPI
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Freescale Semiconductor Advance Information
Multiple Switch Detection Interface
Document Number: MC33993 Rev. 4.0, 6/2007
33993
The 33993 Multiple Switch Detection Interface is designed to detect the closing and opening of up to 22 switch contacts. The switch status, either open or closed, is transferred to the microprocessor unit (MCU) through a serial peripheral interface (SPI). The device also features a 22-to-1 analog multiplexer for reading inputs as analog. The analog input signal is buffered and provided on the AMUX output pin for the MCU to read.
VDD SO
Ground SPI Slave In Serial Clock Chip Select
Programmable Switches 0–7
Switch-to-Ground Inputs 0 – 13
Battery Input
Ground for logic, analog, and switch to battery inputs. SPI control data input pin from MCU to the 33993. SPI control clock input pin. SPI control chip select input pin from MCU to the 33993. Logic 0 allows data to be transferred in. Programmable switch-to-battery or switch-to-ground input pins.
Pin Number Pin Name
Formal Name
Definition
1 2 3 4
5–8 25 – 28 9 – 15, 18 – 24
16 17 29 30 31 32
GND SI
SCLK CS
SP0 – 3 SP4 – 7 SG0 – 6, SG13 – 7 VPWR WAKE
INT AMUX
SG0 SG1 SG2 SG3 SG4 SG5 SG6 SG7 SG8 SG9 SG10 SG11 SG12 SG13
VPWR VPWR
16.0
2.0
mA
mA
SP0
5.0 V VPWR
16.0 mA
2.0 mA
4.0 V Ref
+ –
To SPI
Comparator
VPWR, VDD, 5.0 V
POR Bandgap Sleep PWR
Interrupt
Open-drain output to the MCU. Used to indicate an input switch change of state.
Analog Multiplex Output Analog multiplex output. Voltage Drain Supply 3.3/5.0 V supply. Sets SPI communication level for the SO driver.
VDD 125 kΩ
INT Control MUX Interface
VDD
VDD 40 µA
VDD
+ –
Analog Mux Output
WAKE
INT
CS SCLK SI SO
AMUX
Figure 2. 33993 Simplified Internal Block Diagram
33993
2
Analog Integrated Circuit Device Data Freescale Semiconductor
26
SP5
25
SP4
24
SG7
23
SG822Fra bibliotekSG9
21
SG10
20
SG11
19
SG12
18
SG13
17
WAKE
Figure 3. 33993 Pin Connections
Table 1. 33993 Pin Definitions A functional description of each pin can be found in the Functional Pin Description section beginning on page 9.
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PIN CONNECTIONS
PIN CONNECTIONS
GND
1
SI
2
SCLK
3
CS
4
SP0
5
SP1
6
SP2
7
SP3
8
SG0
9
SG1
10
SG2
11
SG3
12
SG4