A 40-Gbps integrated clock and data recovery circuit in a 50-GHz FT silicon bipolar technology

A 40-Gb/s Integrated Clock and Data RecoveryCircuit in a50-GHzSilicon Bipolar Technology Martin Wurzer,Josef B¨o ck,Herbert Knapp,Wolfgang Zirwas,Fritz Schumann,and Alfred FelderAbstract—Clock and data recovery (CDR)circuits are key elec-tronic components in future optical broadband communicationsystems.In this paper,we present a 40-Gb/s integrated CDR circuit applying a phase-locked loop technique.The IC has been fabricated in a 50-GHz f T self-aligned double-polysilicon bipolar technology using only production-like process steps.The achieved data rate is a record value for silicon and comparable with the best results for this type of circuit realized in SiGe and III–V technologies.Index Terms—Bipolar digital integrated circuits,clocks,data communication,high-speed integrated circuits,phase-locked loops,synchronization.I.I NTRODUCTIONTHE demands for new services and increased flexibility have accelerated the development of telecommunication transport networks,which has resulted in the synchronous op-tical networks (SONET)/synchronous digital hierarchy (SDH)standards.Key elements of such high-capacity networks are fiber-optic communication links.Time-division multiplexing (TDM)systems operating at 10Gb/s are now under devel-opment using advanced silicon bipolar production technolo-gies to fabricate all high-speed IC’s.Next generations with SONET/SDH are expected to operate at data rates of 40Gb/s [1].To enable such large-capacity optical transmission systems to be put into practical use,very high-speed monolithic IC’s are required as key components.It has been shown that basic digital functions like MUX and DMUX for 40-Gb/s optical-fiber TDM systems can be realized in silicon bipolar technology [2].But clock and data recovery circuits in a silicon technology have so far only been demonstrated for 20Gb/s [3].With more sophisticated SiGe or III–V technologies,40-Gb/s operation has been achieved [4]–[7].Some of these solutions are hybrid.All these realizations are based on either high-Q filters or phase-locked loops (PLL’s).The advantage of the first concept is the easy implementation.The disadvantages are that temperature and frequency variation of filter group delay makes sampling time difficult to control,the high-Q filter isManuscript received January 11,1999;revised March 23,1999.M.Wurzer is with Corporate Technology,Microelectronics,Siemens AG,Munich 81730Germany and the Institut f¨u r Nachrichtentechnik und Hochfrequenztechnik,Technische Universit¨a t Wien,Austria (e-mail:Martin.Wurzer@mchp.siemens.de).J.B¨o ck,H.Knapp, F.Schumann,and A.Felder are with Corporate Technology,Microelectronics,Siemens AG,Munich 81730GermanyW.Zirwas is with Information and Communication Networks,Siemens AG,Munich 81379Germany.Publisher Item Identifier S0018-9200(99)06493-8.Fig.1.Block diagram of the fiber-optic link.difficult to integrate,and narrow pulses require ahigh(a)(b)Fig.2.CDR circuit:(a)block diagram and (b)timingdiagram.Fig.3.Circuit diagram of the master–slave D-flip-flop.with DFF2and the XOR gate.All these functions are integrated in a single chip.The fixed 90delayed clock signal.This results in the sampling of the input in the vicinity of midbit and each following potential transition.If a transition is present,the phase relationship of the data and the clock can be deduced to be early or late.If the midbit clock CLK is too early,DFF3samples the same bit;if it is too late,DFF3samples the following bit.Under locked conditions,DFF3samples at the edge of the data eye.The XOR compares the output samples of DFF2and DFF3.The result is fed to the loop filter.The output signal of the loop filter serves as the control signal of the VCO.The advantages of this concept are that all components operate at half the data rate and that the input is demultiplexed at the same time.The disadvantage is that the input signal has to drive three DFF’s in parallel.IV.C IRCUITANDD ESIGN P RINCIPLESThe circuit is designed for the single supply voltage ofCL (emitter–emittercoupled logic)is used with emitter followers at the inputs and current switches at the outputs.The series gating between clock and data signals enables differential operation with lowvoltage swings(mV )resulting in an increase in speed and a reduction of power consumption.Furthermore,differential operation reduces time jitter and crosstalk and offers good common-mode suppression compared to single-mode operation [10].Cascaded emitter followers are used for level shifting and impedance transformation between the various current switches.Multiple emitter followers improve the decoupling capability and increase the collector-base volt-age of the current-switch transistors allowing for smaller transistors,resulting in lower collector-base capacitances [10].On-chip matching resistors(50Fig.4.Chip micrograph(chip size:0.920.9mm2).Meeting the required speed rather than low power con-sumption was the main aim of this design.All transistor sizes are individually optimized with respect to the function of the transistor in the circuit.Extra attention was given to the on-chip wiring.The lines on the chips were classified as “critical”or“uncritical.”For example,the lines driven by emitter followers are critical because they support ringing, while the lines driven by current switches are uncritical[10]. The critical lines are then shortened at the cost of the uncritical ones.The longer signal lines are realized as microstrip lines (with the lowest metallization layer as a ground plane),mainly to improve simulation accuracy.This leads to the layout shown in Fig.4.V.C HIP T ECHNOLOGYThe circuit has been fabricated in a self-aligned double-polysilicon bipolar technology[12].The fabrication starts with buried layer formation.A1-.The isolation consistsof a channel stopper implantation combined with LOCOSfield oxide.The active base is formed by5-keV BFmm design rules.A three-level metallization completes the process.Fig.5shows a schematic cross section of a transistor. Except for epitaxy,only process steps of a0.5-Vand.Table I summarizes typical parametersfor transistors with effective emitter size of-Fig.7.Photograph of the package (package size:70270mm 2).Fig.8.Eye diagram of the 40-Gb/s input data signal D in .respectively,have to be the same.To achieve a compact layout of these lines,coupled microstrip lines are used.At theinput70mm5V and consumes 1.6W.It should be mentionedthat no additional cooling was applied.Fig.8shows the 40-Gb/s input signal to the CDR circuit.To demonstrate the input sensitivity of the circuit,the eye opening is artificially reduced.In Fig.9,an eye diagram of the well regenerated and demultiplexed data signal is shown.Fig.10shows in (a)the 20-GHz transmitter clock and in (b)the recovered clock.The jitter histogram of the extracted clock in the time domain is displayed in Fig.11.The measured rms time jitter as observed on the sampling oscilloscope is about 0.8ps.The measured signal spectra of the VCO are plotted in Fig.12.The dashed line represents the free-running VCO and the solid line the VCO phase-locked to the 40-Gb/s data signal shown in Fig.8.The peak is about 35dB above the floor caused by the statistics of thedata.Fig.9.Eye diagram of the 20-Gb/s data signal at the output D 2of the 1:2demultiplexer.(a)(b)Fig.10.(a)Transmitter clock and (b)recoveredclock.Fig.11.Jitter histogram of the recoveredclock.Fig.12.VCO spectra.VIII.C ONCLUSIONAn integrated clock and data recovery circuit operating up to 40Gb/s has been realized in a0.5-digital functions necessary for a 40-Gb/s transmission system are feasible with silicon bipolar production technologies.R EFERENCES[1]K.Hagimoto,Y.Miyamoto,T.Kataoka,H.Ichino,and O.Nakajima,“Twenty-Gbit/s signal transmission using simple high-sensitivity optical receiver,”in OFC’92Tech.Dig.,Feb.1992,p.48.[2] A.Felder,M.M¨o ller,J.Popp,J.B¨o ck,and H.-M.Rein,“46Gb/sDEMUX,50Gb/s MUX,and 30GHz static frequency divider in silicon bipolar technology,”IEEE J.Solid-State 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Circuits,vol.25,pp.763–766,June 1990.[12]J.B¨o ck,A.Felder,T.F.Meister,M.Franosch,K.Aufinger,M.Wurzer,R.Schreiter,S.Boguth,and L.Treitinger “A 50GHz implanted base silicon bipolar technology with 35GHz static frequency divider,”in Symp.VLSI Technology Tech.Dig.,June 1996,pp.108–109.[13]J.B¨o ck,M.Franosch,H.Sch¨a fer,H.v.Philipsborn,and J.Popp,“In-situ doped emitter-polysilicon for 0.5 m silicon bipolar technology,”inProc.ESSDERC’95,The Hague,the Netherlands,Sept.1995,pp.421–424.[14]M.M¨o ller,H.-M.Rein,A.Felder,and T.F.Meister,“60Gbit/s time-division multiplexer in SiGe-bipolar technology with special regard tomounting and measuring technique,”Electron.Lett.,vol.33,no.8,pp.679–680,Apr.1997.Martin Wurzer was born in Innsbruck,Austria,in 1966.He received the Diplomingenieur degree in electrical engineering from the Technical University Vienna,Austria,in 1994,where he is currently pursuing the Ph.D.degree.He joined Corporate Research and Development,Siemens AG,Munich,Germany,in 1994,where he has been engaged in the development of digital high-speed silicon bipolar IC’s for future optical communication systems in the gigabit-per-secondrange.Josef B¨o ck was born in Straubing,Germany,in 1968.He received the diploma degree in physics and the Ph.D.degree from University of Regensburg,Germany,in 1994and 1997,respectively.He joined Corporate Research and Development,Siemens AG,Munich,Germany,in 1993,where he first investigated narrow emitter effects in deep submicrometer silicon bipolar devices.His work on technology development and process integration for high-speed silicon bipolar transistors resulted in the SIEGET 45microwave-transistor family.Currently,he is working on process development for Si and SiGe bipolartechnologies.Herbert Knapp was born in Salzburg,Austria,in 1964.He received the Diplomingenieur degree in electrical engineering from Technical University Vienna,Austria,in 1997.He joined Corporate Research and Development,Siemens AG,Munich,Germany,in 1993,where he has been involved in the design of integrated circuits for wireless communications.His current research interests include the design of high-speed and low-power microwavecircuits.Wolfgang Zirwas received the Diplomingenieur degree in electrical engineering from Technical Uni-versity Munich,Germany.He joined Siemens AG,Munich,in 1987.First,he worked in the field of high-bit-rate fiber-optic communication ter,he focused his work on broad-band access technologies (xDSL,HFC)for both residential and business users.He is now working in the field of broad-band wirelesssystems.Fritz Schumann received the Diplomingenieur de-gree in electrical engineering from Technical Uni-versity Berlin,Germany,in 1981.Subsequently,he worked in the field of RF and microwave hybrid circuit and system design for telecommunication and radar applications.In 1992,he joined the silicon bipolar IC design group,Cor-porate Research and Development,Siemens AG,Munich,Germany.Since then,he has realized IC’s for wireless and fiber-optic communication systems up to 60Gb/s.Alfred Felder was born in Bruneck,South Tyrol,Italy,in 1963.He received the Diplomingenieur and Ph.D.degrees in electrical engineering from the Technical University Vienna,Austria,in 1989and 1993,respectively.He joined Corporate Research and Development,Siemens AG,Munich,Germany,in 1989,where he has been engaged in the development of analog and digital high-speed silicon bipolar IC’s for future optical communication systems in the gigabit-per-second range.From 1996to 1998,he was Manager of the Technology Department of Siemens K.K.The department is the liaison office of the Corporate Technology of Siemens AG in Japan,responsible for the cooperation with Japanese companies in research.Since 1998,he has been heading the business operation Signal Processing &Control within the Siemens Semiconductor Group in Japan and has been responsible for marketing of microcontrollers and digital signal processors.。