FPGA可编程逻辑器件芯片EP2AGX65DF25C5N中文规格书

U NIVERSAL S ERIAL B US (USB)
USB O PERATING M ODES
3.At the end of the attempt to send the data, the USB controller generates an Endpoint 0 interrupt (for
example by setting the USB_INTRTX.EP0 bit). The processor core should then read the USB_EP0_CSRn_
H to establish whether the USB_EP0_CSRn_H.RXSTALL bit, the USB_EP0_CSRn_H.TOERR bit, or the USB_
EP0_CSRn_H.NAKTO bit is set.
If USB_EP0_CSRn_H.RXSTALL=1, the target has issued a stall response.
If USB_EP0_CSRn_H.TOERR=1 the USB controller has tried to send the OUT token and the following
data packet three times without getting a response.
If USB_EP0_CSRn_H.NAKTO=1, the USB controller has received a NAK response to each attempt to send
the OUT token, for longer than the time set in the USB_EP0_NAKLIMITn register. The USB controller
can then be directed either to continue trying this transaction (until it times out again) by clearing the
USB_EP0_CSRn_H.NAKTO bit; or to abort the transaction by flushing the FIFO before clearing the USB_ EP0_CSRn_H.NAKTO bit.
If none of the USB_EP0_CSRn_H.RXSTALL, USB_EP0_CSRn_H.TOERR, or USB_EP0_CSRn_H.NAKTO bits
are set, the OUT data is correctly acknowledged.
4.If further data needs to be sent, the processor core should repeat the previous steps.
When all the data is successfully sent, the processor core should proceed to the IN status phase of the
control transaction.
IN Status Phase as a Host (Following SETUP Phase or OUT Data Phase) The processor core driving the host device performs the following actions for the IN status phase of a control transaction.
1.Set the USB_EP0_CSRn_H.STATUSPKT and USB_EP0_CSRn_H.REQPKT bits. These bits must be set
together.
2.Wait while the USB controller both sends an IN token and receives a response from the USB peripheral.
3.When the USB controller generates the Endpoint 0 interrupt (for example, sets the USB_INTRTX.EP0
bit), read the USB_EP0_CSRn_H register to establish whether the USB_EP0_CSRn_H.RXSTALL, USB_EP0_ CSRn_H.TOERR, USB_EP0_CSRn_H.NAKTO, or the USB_EP0_CSRn_H.RXPKTRDY bits are set.
If USB_EP0_CSRn_H.RXSTALL=1 the target could not complete the command and so has issued a stall
response.
If USB_EP0_CSRn_H.TOERR=1the USB controller has tried to send the required IN token three times
without getting a response.
If USB_EP0_CSRn_H.NAKTO=1 the USB controller has received a NAK response to each attempt to send
the IN token, for longer than the time set in the USB_EP0_NAKLIMITn register. The USB controller can
then be directed either to continue trying this transaction (until it times out again) by clearing the USB_ EP0_CSRn_H.NAKTO bit or to abort the transaction by clearing USB_EP0_CSRn_H.REQPKT and USB_
EP0_CSRn_H.STATUSPKT before clearing the USB_EP0_CSRn_H.NAKTO bit.
ADSP-BF60X B LACKFIN P ROCESSOR H ARDWARE R EFERENCE
U NIVERSAL S ERIAL B US (USB)
USB O PERATING M ODES
Peripheral Mode, ISO IN, Large MaxPktSize
P REREQUISITE:
For this process, the maximum individual packet size (MaxPktSize) in bytes is greater than 128 bytes and is an even number of bytes. Double buffering is assumed to be enabled, and the auto set feature unused (because packets are often less than MaxPktSize).
1.Load MaxPktSize into USB_TXMAXPn.
2.Set ISO_T = 1 in USB_TXCSR.
3.Set ISO_UPDATE = 1 in USB_POWER to prevent initial packet loaded into the FIFO from being trans-
mitted on USB until the next 1ms frame.
4.Load the total number of bytes for the first two packets into USB_DMA_CNTn.
5.Configure the DMA controller to pre-load the two packets into the corresponding TX FIFO address.
Set TXPKTRDY.
6.Set up an ISR, sensitive to the SOF_B interrupt, which writes a new packet into the TX FIFO by config-
uring the DMA controller to load the packet.
7.Set SOF_B = 1 in USB_INTRUSBE to generate an interrupt on each start-of-frame.
8.Step 7 is repeated for each ISO packet.
Peripheral Mode, Bulk OUT, Transfer Size Known
P REREQUISITE:
For this process, the maximum individual packet size (MaxPktSize) in bytes and the complete transfer size (TxferSize) in bytes must be known.
1.Load MaxPktSize into USB_RXMAXPn.
2.Set DMA_ENA = 1, AUTOCLEAR_R = 1, ISO_R = 0, FRCDATATOG = 0, DMAREQMODE_R = 0 in USB_RXCSR.
3.Configure the DMA controller to read the full TxferSize/2 half words from the corresponding RX FIFO
address.
4.On each USB_DMAxINT transition, the DMA controller reads another packet from the FIFO. RXPKTRDY
is automatically cleared by the USB controller when each new packet is read.
5.Step 5 is repeated for each full packet of the transfer.
6.If TxferSize is not an exact multiple of MaxPktSize, the final USB_DMAxINT transition causes the DMA
controller to read out only the short packet that remains.
ADSP-BF60X B LACKFIN P ROCESSOR H ARDWARE R EFERENCE
U NIVERSAL S ERIAL B US (USB)
USB O PERATING M ODES
ADSP-BF60X B LACKFIN P ROCESSOR H ARDWARE R EFERENCE the USB_EP0_CSRn_P.SSETUPEND bit, and return to the IDLE state. If the USB_EP0_CSRn_P.RXPKTRDY bit is set, this indicates that the host has sent another SETUP packet and the software should then process this command.
If the software wants to abort the current transfer, because it cannot process the command or has some other internal error, then it should set the USB_EP0_CSRn_P.SENTSTALL bit. The USB controller then sends a stall packet to the host, set the USB_EP0_CSRn_P.SENTSTALL bit and generate an Endpoint 0 inter-rupt.
Stalls Issued to Control Transfers
In peripheral mode, the USB controller automatically issues a stall handshake to a control transfer under the following conditions:
1.The host sends more data during an OUT data phase of a control transfer than was specified in the
device request during the SETUP phase. This condition is detected by the USB controller when the host sends an OUT token (instead of an IN token) after the processor core has unloaded the last OUT packet and set the USB_EP0_CSRn_P.DATAEND bit.
2.The host requests more data during an IN data phase of a control transfer than was specified in the
device request during the SETUP phase. This condition is detected by the USB controller when the host sends an IN token (instead of an OUT token) after the processor core has cleared USB_EPn_TXCSR_P.TXPKTRDY and set USB_EP0_CSRn_P.DATAEND in response to the ACK issued by the host to what should have been the last packet.
3.The host sends more than MaxPktSize data with an OUT data token.
4.The host sends the wrong PID (packet identifier) for the OUT status phase of a control transfer.
5.The host sends more than a zero length data packet for the OUT status phase.
Zero Length OUT Data Packets in Control Transfers
A zero-length OUT data packet is used to indicate the end of a control transfer. In normal operation, such packets should only be received after the entire length of the device request is transferred (for example, after the processor core has set the USB_EP0_CSRn_P.DATAEND bit). If the host sends a zero-length OUT data packet before the entire length of device request is transferred, this packet signals the premature end of the transfer. In this case, the US
B controller automatically flushes any IN token loaded by processor core ready for the data phase from the FIFO and sets the USB_EP0_CSRn_P.SETUPEND bit.
Host Mode
USB OTG interface operations in host mode differ from peripheral mode in a number of ways. The following sections describe host mode operations.。