MEMORY存储芯片MT29F256G08CMAAAC5中文规格书

be applied with power-down exit latency, t XP , after CKE goes HIGH. Power-down exit la-
tency is defined in the AC Specifications table.
Figure 94: Active Power-Down Entry and Exit
CK_t CK_c
Command
Address CKE
power-down
mode power-down mode
T0
T1T2Ta0Ta1Tb0Tb1Tc0
Don’t Care
Time Break Notes: 1.Valid commands at T0 are ACT, DES, or PRE with one bank remaining open after comple-
tion of the PRECHARGE command.
2.ODT pin driven to a valid state; MR5[5] = 0 (normal setting).
3.ODT pin drive/float timing requirements for the ODT input buffer disable option (for ad-
ditional power savings during active power-down) is described in the section for ODT In-
put Buffer Disable Mode for Power-Down (page 169); MR5[5] = 1.
8Gb: x4, x8, x16 DDR4 SDRAM Power-Down Mode
Figure 246: Measurement Setup and Test Load for I DDx , I PPx , and I DDQx
Figure 247: Correlation: Simulated Channel I/O Power to Actual Channel I/O Power
Application-specific
memory channel
environment I DD Q test load
C hanne l I /O
power n
umber
Note: 1.Supported by I DDQ measurement.
I DD Definitions
Table 137: Basic I DD , I PP , and I DDQ Measurement Conditions
8Gb: x4, x8, x16 DDR4 SDRAM Current Specifications – Measurement Conditions
When T C > 85°C: I DD0, I DD1, I DD2N , I DD2NT , I DD2Q , I DD3N , I DD3P , I DD4R , I DD4W , and I DD5R must be derated by 3%; I DD2P must be derated by 40%. These values are verified by design and characterization, and may not be subject to production test.
25.I PP6x is applicable to I DD6N , I DD6E , I DD6R and I DD6A conditions.
Table 149: I DD , I PP , and I DDQ Current Limits; Die Rev. B (0° ื T C ื 85°C)
8Gb: x4, x8, x16 DDR4 SDRAM Current Specifications – Limits。