56617_THS3091+

FEATURES DESCRIPTIONAPPLICATIONSTOTAL HARMONIC DISTORTIONvsTYPICAL ARBITARY WAVEFORMGENERATOR OUTPUT DRIVE CIRCUITf − Frequency − HzTotalHarmonicDistortion−dBcTHS3091THS3095SLOS423B–SEPTEMBER2003–REVISED FEBRUARY2004 HIGH-VOLTAGE,LOW-DISTORTION,CURRENT-FEEDBACKOPERATIONAL AMPLIFIERS•Low Distortion The THS3091and THS3095are high-voltage,low-distortion,high speed,current-feedback –77dBc HD2at10MHz,R L=1kΩamplifiers designed to operate over a wide supply –69dBc HD3at10MHz,R L=1kΩrange of±5V to±15V for applications requiring •Low Noise large,linear output signals such as Pin,Power FET,–14pA/√Hz Noninverting Current Noise and VDSL line drivers.–17pA/√Hz Inverting Current Noise The THS3095features a power-down pin(PD)thatputs the amplifier in low power standby mode,and –2nV/√Hz Voltage Noiselowers the quiescent current from9.5mA to500µA.•High Slew Rate:7300V/µs(G=5,V O=20V PP)The wide supply range combined with total harmonic •Wide Bandwidth:210MHz(G=2,R L=100Ω)distortion as low as-69dBc at10MHz,in addition,to •High Output Current Drive:±250mAthe high slew rate of7300V/µs makes the THS3091/5•Wide Supply Range:±5V to±15V ideally suited for high-voltage arbitrary waveformdriver applications.Moreover,having the ability to •Power-Down Feature:(THS3095Only)handle large voltage swings driving intohigh-resistance and high-capacitance loads whilemaintaining good settling time performance makes •High-Voltage Arbitrary Waveformthe devices ideal for Pin driver and PowerFET driver •Power FET Driver applications.•Pin DriverThe THS3091and THS3095are offered in an8-pin •VDSL Line Driver SOIC(D),and the8-pin SOIC(DDA)packages withPowerPAD™.Please be aware that an important notice concerning availability,standard warranty,and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.PowerPAD is a trademark of Texas Instruments.Note A: The devices with the power down option defaults to the ON state if no signal is applied to the PD pin. Additionallly, the REF pin functional range is from V S− to (V S+ − 4 V).DISSIPATION RATING TABLETHS3091THS3095SLOS423B–SEPTEMBER2003–REVISED FEBRUARY2004These devices have limited built-in ESD protection.The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damageto the MOS gates.ODERING INFORMATION(1)The PowerPAD is electrically isolated from all other pins.(1)This data was taken using the JEDEC standard High-K test PCB.(2)Power rating is determined with a junction temperature of125°C.This is the point where distortion starts to substantially increase.Thermal management of the final PCB should strive to keep the junction temperature at or below125°C for best performance and long term reliability.(3)The THS3091and THS3095may incorporate a PowerPAD™on the underside of the chip.This acts as a heatsink and must beconnected to a thermally dissipating plane for proper power dissipation.Failure to do so may result in exceeding the maximum junction temperature which could permanently damage the device.See TI Technical Brief SLMA002for more information about utilizing the PowerPAD™thermally enhanced package.RECOMMENDED OPERATING CONDITIONS ABSOLUTE MAXIMUM RATINGSTHS3091THS3095 SLOS423B–SEPTEMBER2003–REVISED FEBRUARY2004over operating free-air temperature(unless otherwise noted)(1)(1)The absolute maximum ratings under any condition is limited by the constraints of the silicon process.Stresses above these ratings maycause permanent damage.Exposure to absolute maximum conditions for extended periods may degrade device reliability.These are stress ratings only,and functional operation of the device at these or any other conditions beyond those specified is not implied.(2)The maximum junction temperature for continuous operation is limited by package constraints.Operation above this temperature mayresult in reduced reliability and/or lifetime of the device.ELECTRICAL CHARACTERISTICSTHS3091THS3095SLOS423B–SEPTEMBER 2003–REVISED FEBRUARY 2004V S =±15V,R F =1.21k Ω,R L =100Ω,and G =2(unless otherwise noted)ELECTRICAL CHARACTERISTICS(CONTINUED)THS3091THS3095 SLOS423B–SEPTEMBER2003–REVISED FEBRUARY2004V S=±15V,R F=1.21kΩ,R L=100Ω,and G=2(unless otherwise noted)ELECTRICAL CHARACTERISTICSTHS3091THS3095SLOS423B–SEPTEMBER 2003–REVISED FEBRUARY 2004V S =±5V,R F =1.15k Ω,R L =100Ω,and G =2(unless otherwise noted)ELECTRICAL CHARACTERISTICS(CONTINUED)THS3091THS3095 SLOS423B–SEPTEMBER2003–REVISED FEBRUARY2004V S=±5V,R F=1.15kΩ,R L=100Ω,and G=2(unless otherwise noted)TYPICAL CHARACTERISTICSTABLE OF GRAPHSTHS3091THS3095SLOS423B–SEPTEMBER 2003–REVISED FEBRUARY 2004TABLE OF GRAPHSTHS3091THS3095 SLOS423B–SEPTEMBER2003–REVISED FEBRUARY2004TYPICAL CHARACTERISTICS(continued)TYPICAL CHARACTERISTICS (±15V)1 M10 M100 M1 Gf - Frequency - Hz N o n i n v e r t i ng G a i n - d B1 M10 M100 M1 Gf − Frequency − Hz N o n i n v e r t i ng G a i n − d B1 M10 M100 M1 Gf − Frequency − HzI n v e r t i n g G a i n − d Bf − Frequency − HzI n v e r t i n g G a i n − dB246810121416 f − Frequency − HzN o n i n v e r t i n g G a i n − d B5.75.85.966.16.26.3f - Frequency - HzN o n i n v e r t i n g G a i n - d B−2246810121416S i g n a l G a i n − d Bf − Frequency − HzC L − Capacitive Load − pFR e c o m m e n d e d RI S OΩ− f − Frequency − Hz2n d H a r m o n i c D i s t o r t i o n − d B cTHS3091THS3095SLOS423B–SEPTEMBER 2003–REVISED FEBRUARY 2004NONINVERTING SMALL SIGNALNONINVERTING SMALL SIGNALINVERTING SMALL SIGNAL FREQUENCY RESPONSEFREQUENCY RESPONSEFREQUENCY RESPONSEFigure 1.Figure 2.Figure 3.0.1dB GAIN FLATNESS NONINVERTING LARGE SIGNALINVERTING LARGE SIGNAL FREQUENCY RESPONSEFREQUENCY RESPONSEFREQUENCY RESPONSEFigure 4.Figure 5.Figure 6.RECOMMENDED R ISO2ND HARMONIC DISTORTIONCAPACITIVE LOAD vsvsFREQUENCY RESPONSECAPTIVATE LOADFREQUENCYFigure 7.Figure 8.Figure 9.f − Frequency − Hz 2n d H a r m o n i c D i s t o r t i o n − d B c−90−80−70−60−50−40f − Frequency − Hz3r d H a r m o n i c D i s t o r t i o n − d B c−55−85−75−65−45-90-80-70-60-50-401 M10 M100 Mf - Frequency - Hz100 k3r d H a r m o n i c D i s t o r t i o n - d Bcf − Frequency − Hz2n d H a r m o n i c D i s t o r t i o n − d B cf − Frequency − Hz3r d H a r m o n i c D i s t o r t i o n − d B c-100-95-90-85-80-70-60024681012H a r m o n i c D i s t o r t i o n - d B cV O - Output Voltage Swing - V PP-75-65141618200.51 1.52 2.53 3.54 4.55V O − Output Voltage − V PPS R − S l e w R a t e − sµV /-100-90-80-70-60-40024681012H a r m o n i c D i s t o r t i o n - d B cV O - Output Voltage Swing - V PP-5014161820100020003000400050006000V O - Output Voltage - V PPS R - S l e w R a t e - sµV /TYPICAL CHARACTERISTICS (±15V)(continued)3RD HARMONIC DISTORTION2ND HARMONIC DISTORTION3RD HARMONIC DISTORTIONvsvsvsFREQUENCYFREQUENCYFREQUENCYFigure 10.Figure 11.Figure 12.2ND HARMONIC DISTORTION3RD HARMONIC DISTORTIONHARMONIC DISTORTIONvsvsvsFREQUENCYFREQUENCYOUTPUT VOLTAGE SWINGFigure 13.Figure 14.Figure 15.HARMONIC DISTORTIONSLEW RATESLEW RATEvsvsvsOUTPUT VOLTAGE SWINGOUTPUT VOLTAGE STEPOUTPUT VOLTAGE STEPFigure 16.Figure 17.Figure 18.110100100010100 1 k 10 k 100 kf − Frequency − Hz− C u r r e n t N o i s e −V n I n − V o l t a g e N o i s e − p A /H zn V /H z-1.25-1-0.75-0.5-0.2500.250.50.7511.25012345678910t - Time - ns- O u t p u t V o l t a g e - VV O010002000300040005000600070008000V O - Output Voltage - V PPS R - S l e w R a t e - sµV /-4.5-4-3.5-3-2.5-2-1.5-1-0.500.511.522.533.544.5t - Time - ns- O u t p u t V o l t a g e - VV O− Q u i e s c e n t C u r r e n t − m AI Q V S − Supply Voltage − ±V1 M10 M − Q u i e s c e n t C u r r e n t − m AI Q f − Frequency − Hz-16-12-8-40481216R L - Load Resistance - Ω- O u t p u t V o l t a g e -VV O 00.511.522.53T C - Case Temperature - °C- I n p u t O f f s e t V o l t a g e - m VV O S0.511.522.533.544.555.566.57T C - Case Temperature - °C- I n p u t B i a s C u r r e n t s -I I B I O S - I n p u t O f f s e t C u r r e n t s -A µAµSLOS423B–SEPTEMBER 2003–REVISED FEBRUARY 2004TYPICAL CHARACTERISTICS (±15V)(continued)SLEW RATENOISE vsvsOUTPUT VOLTAGE STEPFREQUENCYSETTLING TIMEFigure 19.Figure 20.Figure 21.QUIESCENT CURRENTQUIESCENT CURRENTvsvsSETTLING TIMESUPPLY VOLTAGEFREQUENCYFigure 22.Figure 23.Figure 24.INPUT BIAS AND OUTPUT VOLTAGEOFFSET CURRENTINPUT OFFSET VOLTAGEvsvsvsLOAD RESISTANCECASE TEMPERATURECASE TEMPERATUREFigure 25.Figure 26.Figure 27.-0.3-0.25-0.2-0.15-0.1-0.05010203040506070t - Time - n s- O u t p u t V o l t a g e - VV O 010203040506070R e j e c t i o n R a t i o − d Bf − Frequency − Hz100 k1 M10 M100 M1 Gf − Frequency − HzT r a n s i m p e d a n c e G a i n − d B O h m s00.10.20.30.40.50.60.70.80.91t − Time − µs− O u t p u t V o l t a g e − V− I n p u t V o l t a g e − VV I V O-12-10-8-6-4-2t - Time - n s- O u t p u t V o l t a g e- VV O t − Time − n s− O u t p u t V o l t a g e − VV O00.010.020.030.040.050.060.070.080.090.10012345678Number of Loads - 150 ΩD i f f e r e n t i a l G a i n - %0.010.020.030.040.05Number of Loads − 150 ΩD i f f e r e n t i a l P h a s e −°1 M10 M100 M1 Gf − Frequency − HzC l o s e d -L o o p O u t p u t I m p e d a n c e −ΩTYPICAL CHARACTERISTICS (±15V)(continued)TRANSIMPEDANCEREJECTION RATIOvsvsNONINVERTING SMALL SIGNALFREQUENCYFREQUENCYTRANSIENT RESPONSEFigure 28.Figure 29.Figure 30.INVERTING LARGE SIGNAL INVERTING LARGE SIGNAL TRANSIENT RESPONSETRANSIENT RESPONSEOVERDRIVE RECOVERY TIMEFigure 31.Figure 32.Figure 33.CLOSED-LOOP OUTPUTDIFFERENTIAL GAINDIFFERENTIAL PHASEIMPEDANCEvsvsvsNUMBER OF LOADSNUMBER OF LOADSFREQUENCYFigure 34.Figure 35.Figure 36.−0.100.10.20.3t − Time − ms− O u t p u t V o l t a g e L e v e l − VV O P o w e r D o w n P u l s e − VV S - Supply Voltage - ±VP o w e r d o w n Q u i e s c e n t C u r r e n t -AµSLOS423B–SEPTEMBER 2003–REVISED FEBRUARY 2004TYPICAL CHARACTERISTICS (±15V)(continued)POWER-DOWN QUIESCENTCURRENTvsTURNON AND TURNOFFSUPPLY VOLTAGETIME DELAYFigure 37.Figure 38.TYPICAL CHARACTERISTICS (±5V)1 M10 M 100 M 1 Gf − Frequency − HzI n v e r t i n g G a i n − dB-4-2024681012141618202224 1 M10 M100 M1 Gf - Frequency - HzN o n i n v e r t i n g G a i n - d B5.75.85.966.16.26.31 M10 M100 Mf - Frequency - HzN o n i n v e r t i n g G a i n - dB-1.25-1-0.75-0.5-0.2500.250.50.7511.25012345678910t - Time - ns- O u t p u t V o l t a g e - VV O02468101214161 M10 M100 M1 Gf − Frequency − Hz N o n i n v e r t i ng G a i n − d B−4−202468101214161 M10 M 100 M 1 Gf − Frequency − HzI n v e r t i n g G a i n − dBf − Frequency − Hz 2n d H a r m o n i c D i s t o r t i o n − d B c-90-80-70-60-50-40f - Frequency - Hz 3r d H a r m o n i c D i s t o r t i o n - d B cf − Frequency − Hz2n d H a r m o n i c D i s t o r t i o n − d B cNONINVERTING SMALL SIGNALINVERTING SMALL SIGNAL 0.1dB GAIN FLATNESS FREQUENCY RESPONSEFREQUENCY RESPONSEFREQUENCY RESPONSEFigure 39.Figure 40.Figure 41.NONINVERTING LARGE SIGNALINVERTING LARGE SIGNAL FREQUENCY RESPONSEFREQUENCY RESPONSESETTLING TIMEFigure 42.Figure 43.Figure 44.2ND HARMONIC DISTORTION3RD HARMONIC DISTORTION2ND HARMONIC DISTORTIONvsvsvsFREQUENCYFREQUENCYFREQUENCYFigure 45.Figure 46.Figure 47.f − Frequency − Hz3r d H a r m o n i c D i s t o r t i o n − d B c123456H a r m o n i c D i s t o r t i o n - d BcV O - Output Voltage Swing - V PP123456H a r m o n i c D i s t o r t i o n − d B cV O − Output Voltage Swing − V PP12345S R − S l e w R a t e − V /V O − Output Voltage −V PPsµ02004006008001000120014001600S R − S l e w R a t e − V /V O − Output Voltage −V PPsµ020040060080010001200140016001800200000.51 1.52 2.53 3.54 4.55S R - S l e w R a t e - V /V O - Output Voltage -V PPsµ-40-30-20-100102030405060708090- I n p u t B i a s C u r r e n t -T C - Case Temperature - °C- I n p u t O f f s e t C u r r e n t -I I B AµI O S Aµ246810121416182022− Q u i e s c e n t C u r r e n t − m AI Q f − Frequency − Hz-3.5-3-2.5-2-1.5-1-0.500.511.522.533.5101001000R L - Load Resistance - Ω- O u t p u t V o l t a g e - VV O SLOS423B–SEPTEMBER 2003–REVISED FEBRUARY 2004TYPICAL CHARACTERISTICS (±5V)(continued)3RD HARMONIC DISTORTIONHARMONIC DISTORTIONHARMONIC DISTORTIONvsvsvsFREQUENCYOUTPUT VOLTAGE SWINGOUTPUT VOLTAGE SWINGFigure 48.Figure 49.Figure 50.SLEW RATESLEW RATESLEW RATEvsvsvsOUTPUT VOLTAGE STEPOUTPUT VOLTAGE STEPOUTPUT VOLTAGE STEPFigure 51.Figure 52.Figure 53.INPUT BIAS AND QUIESCENT CURRENTOUTPUT VOLTAGEOFFSET CURRENTvsvsvsFREQUENCYLOAD RESISTANCECASE TEMPERATUREFigure 54.Figure 55.Figure 56.-5-4-3-2-1012345t - Time - µs- I n p u t V o l t a g e - VV I - O u t p u t V o l t a g e - AV O 010203040506070100 k1 M 10 M 100 MR e j e c t i o n R a t i o - d Bf - Frequency - HzTYPICAL CHARACTERISTICS (±5V)(continued)REJECTION RATIOOVERDRIVE RECOVERYvsTIMEFREQUENCYFigure 57.Figure 58.APPLICATION INFORMATIONWIDEBAND,NONINVERTING OPERATION−15 VV ISLOS423B–SEPTEMBER 2003–REVISED FEBRUARY 2004Current-feedback amplifiers are highly dependent on the feedback resistor R F for maximum performance The THS3091/5are unity gain stable 235-MHz and stability.Table 1shows the optimal gain setting current-feedback operational amplifiers,designed to resistors R F and R G at different gains to give operate from a ±5-V to ±15-V power supply.maximum bandwidth with minimal peaking in theFigure 59shows the THS3091in a noninverting gain frequency response.Higher bandwidths can be of 2-V/V configuration typically used to generate the achieved,at the expense of added peaking in the performance curves.Most of the curves were frequency response,by using even lower values for characterized using signal sources with 50-Ωsource R F .Conversely,increasing R F decreases the impedance,and with measurement equipment bandwidth,but stability is improved.presenting a 50-Ωload impedance.Table 1.Recommended Resistor Values forOptimum Frequency ResponseFigure 59.Wideband,Noninverting GainConfigurationWIDEBAND,INVERTING OPERATIONS 2Video DistributionSINGLE SUPPLY OPERATIONFigure 60shows the THS3091in a typical inverting gain configuration where the input and output impedances and signal gain from Figure 59are retained in an inverting circuit configuration.Figure 61.DC-Coupled,Single-Supply Operation Figure 60.Wideband,Inverting GainConfigurationThe wide bandwidth,high slew rate,and high output drive current of the THS3091/5matches the demands The THS3091/5have the capability to operate from a for video distribution for delivering video signals down single supply voltage ranging from multiple cables.To ensure high signal quality with 10V to 30V.When operating from a single power minimal degradation of performance,a 0.1-dB gain supply,biasing the input and output at mid-supply flatness should be at least 7x the passband allows for the maximum output voltage swing.The frequency to minimize group delay variations from the circuits shown in Figure 61shows inverting and amplifier.A high slew rate minimizes distortion of the noninverting amplifiers configured for single supply video signal,and supports component video and operations.RGB video signals that require fast transition times and fast settling times for high signal quality.Figure 62.Video Distribution AmplifierApplicationDriving Capacitive LoadsC L − Capacitive Load − pFR e c o m m e n d e d RI S OΩ−SLOS423B–SEPTEMBER 2003–REVISED FEBRUARY 2004Placing a small series resistor,R ISO ,between the amplifier’s output and the capacitive load,as shown Applications such as FET line drivers can be highly in Figure 64,is an easy way of isolating the load capacitive and cause stability problems for capacitance.high-speed amplifiers.Using a ferrite chip in place of R ISO ,as shown in Figure 63through Figure 68show recommended Figure 65,is another approach of isolating the output methods for driving capacitive loads.The basic idea of the amplifier.The ferrite's impedance characteristic is to use a resistor or ferrite chip to isolate the phase versus frequency is useful to maintain the low shift at high frequency caused by the capacitive load frequency load independence of the amplifier while from the amplifier’s feedback path.See Figure 63for isolating the phase shift caused by the capacitance at recommended resistor values versus capacitive load.high e a ferrite with similar impedance to R ISO ,20Ω-50Ω,at 100MHz and low impedance at dc.Figure 66shows another method used to maintain the low frequency load independence of the amplifier while isolating the phase shift caused by the capaci-tance at high frequency.At low frequency,feedback is mainly from the load side of R ISO .At high fre-quency,the feedback is mainly via the 27-pF capacitor.The resistor R IN in series with the negative input is used to stabilize the amplifier and should be equal to the recommended value of R F at unity gain.Replacing R IN with a ferrite of similar impedance at about 100MHz as shown in Figure 67gives similar results with reduced dc offset and low frequency Figure 63.Recommended R ISO vs Capacitive Loadnoise.(See the ADDITIONAL REFERENCE MA-TERIAL section for Expanding the usability of cur-rent-feedback amplifiers.)Figure 64.Figure 66.Figure 65.V S S V SAVING POWER WITH POWER-DOWNV S−V S THS3091THS3095SLOS423B–SEPTEMBER 2003–REVISED FEBRUARY 2004Figure 67.Figure 68is shown using two amplifiers in parallel toFigure 69.PowerFET Drive Circuit double the output drive current to larger capacitiveloads.This technique is used when more outputcurrent is needed to charge and discharge the loadfaster like when driving large FET transistors.FUNCTIONALITY AND SETTING THRESHOLD LEVELS WITH THE REFERENCE PIN The THS3095features a power-down pin (PD)which lowers the quiescent current from 9.5mA down to 500µA,ideal for reducing system power.The power-down pin of the amplifier defaults to the negative supply voltage in the absence of an applied voltage,putting the amplifier in the power-on mode of operation.To turn off the amplifier in an effort to conserve power,the power-down pin can be driven towards the positive rail.The threshold voltages for power-on and power-down are relative to the supply rails and are given in the specification tables.Belowthe Enable Threshold Voltage ,the device is on.Figure 68.Above the Disable Threshold Voltage ,the device isoff.Behavior in between these threshold voltages isFigure 69shows a push-pull FET driver circuit typical not specified.of ultrasound applications with isolation resistors to Note that this power-down functionality is just that;isolate the gate capacitance from the amplifier.the amplifier consumes less power in power-downmode.The power-down mode is not intended toprovide a high-impedance output.In other words,thepower-down functionality is not intended to allow useas a 3-state bus driver.When in power-down mode,the impedance looking back into the output of theamplifier is dominated by the feedback and gainsetting resistors,but the output impedance of thedevice itself varies depending on the voltage appliedto the outputs.Figure 70shows the total system output impedancewhich includes the amplifier output impedance inparallel with the feedback plus gain resistors,whichcumulate to 2380Ω.Figure 59shows this circuitconfiguration for reference. PRINTED-CIRCUIT BOARD LAYOUTf − Frequency − Hz− P o w e r d o w n O u t p u t I m p e d a n c e − Z O P D ΩPOWER-DOWN REFERENCE PIN THS3091THS3095SLOS423B–SEPTEMBER 2003–REVISED FEBRUARY 2004TECHNIQUES FOR OPTIMAL PERFORMANCE Achieving optimum performance with high frequency amplifier,like the THS3091/5,requires careful attention to board layout parasitic and external component types.Recommendations that optimize performance include:•Minimize parasitic capacitance to any ac ground for all of the signal I/O pins.Parasitic capacitance on the output and input pins can cause instability.To reduce unwanted capacitance,a window around the signal I/O pins should be opened in all of the ground and power planes around those Figure 70.Power-down Output Impedance vs pins.Otherwise,ground and power planes should Frequencybe unbroken elsewhere on the board.•Minimize the distance (<0.25”)from the power As with most current feedback amplifiers,the internalsupply pins to high frequency 0.1-µF and 100-pF architecture places some limitations on the systemdecoupling capacitors.At the device pins,the when in power-down mode.Most notably is the factground and power plane layout should not be in that the amplifier actually turns ON if there is a ±0.7Vclose proximity to the signal I/O pins.Avoid or greater difference between the two input nodesnarrow power and ground traces to minimize (V+and V-)of the amplifier.If this difference exceedsinductance between the pins and the decoupling ±0.7V,the output of the amplifier creates an output capacitors.The power supply connections should voltage equal to approximatelyalways be decoupled with these capacitors.[(V+-V-)-0.7V]×Gain.This also implies that if aLarger (6.8µF or more)tantalum decoupling voltage is applied to the output while in power-downcapacitors,effective at lower frequency,should mode,the V-node voltage is equal toalso be used on the main supply pins.These may V O(applied)×R G /(R F +R G ).For low gain configurationsbe placed somewhat farther from the device and and a large applied voltage at the output,themay be shared among several devices in the amplifier may actually turn ON due to thesame area of the PC board.aforementioned behavior.•Careful selection and placement of external The time delays associated with turning the device oncomponents preserve the high frequency and off are specified as the time it takes for theperformance of the THS3091/5.Resistors should amplifier to reach either 10%or 90%of the finalbe a very low reactance type.Surface-mount output voltage.The time delays are in the order ofresistors work best and allow a tighter overall microseconds because the amplifier moves in and outlayout.Again,keep their leads and PC board of the linear mode of operation in these transitions.trace length as short as possible.Never use wirebound type resistors in a high frequency application.Since the output pin and inverting OPERATIONinput pins are the most sensitive to parasitic capacitance,always position the feedback and In addition to the power-down pin,the THS3095series output resistors,if any,as close as poss-features a reference pin (REF)which allows the userible to the inverting input pins and output pins.to control the enable or disable power-down voltageOther network components,such as input termin-levels applied to the PD pin.In most split-supplyation resistors,should be placed close to the applications,the reference pin is connected togain-setting resistors.Even with a low parasitic ground.In either case,the user needs to be aware ofcapacitance shunting the external resistors,voltage-level thresholds that apply to the power-downexcessively high resistor values can create sig-pin.The usable range at the REF pin is from V S-tonificant time constants that can degrade perform-(V S+-4V).ance.Good axial metal-film or surface-mountresistors have approximately 0.2pF in shunt withthe resistor.For resistor values > 2.0k Ω,thisparasitic capacitance can add a pole and/or azero that can effect circuit operation.Keep re-sistor values as low as possible,consistent withload driving considerations.Side View (a)End View (b)Bottom View (c)PowerPAD™DESIGN CONSIDERATIONSTop ViewAll Units in InchesTHS3091THS3095 SLOS423B–SEPTEMBER2003–REVISED FEBRUARY2004•Connections to other wideband devices on the leadframe upon which the die is mounted[see board may be made with short direct traces or Figure71(a)and Figure71(b)].This arrangement through onboard transmission lines.For short results in the lead frame being exposed as a thermal connections,consider the trace and the input to pad on the underside of the package[see the next device as a lumped capacitive load.Figure71(c)].Because this thermal pad has direct Relatively wide traces(50mils to100mils)thermal contact with the die,excellent thermal per-should be used,preferably with ground and formance can be achieved by providing a good power planes opened up around them.Estimate thermal path away from the thermal pad.Note that the total capacitive load and determine if isolation devices such as the THS3091/5have no electrical resistors on the outputs are necessary.Low connection between the PowerPAD and the die.parasitic capacitive loads(<4pF)may not needThe PowerPAD package allows for both assembly an R S since the THS3091/5are nominally com-and thermal management in one manufacturing oper-pensated to operate with a2-pF parasitic load.ation.During the surface-mount solder operation Higher parasitic capacitive loads without an RS(when the leads are being soldered),the thermal pad are allowed as the signal gain increasescan also be soldered to a copper area underneath the (increasing the unloaded phase margin).If a longpackage.Through the use of thermal paths within this trace is required,and the6-dB signal loss intrin-copper area,heat can be conducted away from the sic to a doubly-terminated transmission line ispackage into either a ground plane or other heat acceptable,implement a matched impedancedissipating device.transmission line using microstrip or striplinetechniques(consult an ECL design handbook for The PowerPAD package represents a breakthrough microstrip and stripline layout techniques).A in combining the small area and ease of assembly of 50-Ωenvironment is not necessary onboard,and surface mount with the,heretofore,awkward in fact,a higher impedance environment mechanical methods of heatsinking.improves distortion as shown in the distortionversus load plots.With a characteristic boardtrace impedance based on board material andtrace dimensions,a matching series resistor intothe trace from the output of the THS3091/5isused as well as a terminating shunt resistor at theinput of the destination device.Remember alsothat the terminating impedance is the parallelcombination of the shunt resistor and the input Figure71.Views of Thermal Enhanced Package impedance of the destination device:this totaleffective impedance should be set to match theAlthough there are many ways to properly heatsink trace impedance.If the6-dB attenuation of athe PowerPAD package,the following steps illustrate doubly terminated transmission line is unaccept-the recommended approach.able,a long trace can be series-terminated at thesource end only.Treat the trace as a capacitiveload in this case.This does not preserve signalintegrity as well as a doubly-terminated line.If theinput impedance of the destination device is low,there is some signal attenuation due to thevoltage divider formed by the series output intothe terminating impedance.•Socketing a high speed part like the THS3091/5are not recommended.The additional lead lengthand pin-to-pin capacitance introduced by thesocket can create an extremely troublesomeparasitic network which can make it almost im-possible to achieve a smooth,stable frequencyresponse.Best results are obtained by solderingthe THS3091/5parts directly onto the board.The THS3091/5are available in aFigure72.DDA PowerPAD PCB Etch and Via thermally-enhanced PowerPAD family of packages.PatternThese packages are constructed using a downset。