SM20MT24C中文资料

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SM20中文资料

Rack and Panel ConnectorsSubminiature Rectangular For technical questions, contact: connectors@Document Number: 36010SM20Vishay DaleFEATURES•Lightweight.•Polarized by guides or screwlocks.•Screwlocks lock connectors together to withstand vibration and accidental disconnect.•Overall height kept to a minimum.•Floating contacts aid in alignment and in withstanding vibration.•Contacts, precision machined and individually gauged,provide high reliability.•Insertion and withdrawal forces kept low without increasing contact resistance.•Contact plating provides protection against corrosion,assures low contact resistance and ease of soldering.SMP20SMS20ELECTRICAL SPECIFICATIONSCurrent Rating: 7.5 amps.Breakdown Voltage:At sea level: 2000 V RMS.At 70,000 feet [21,336 meters]: 500 V RMS.PHYSICAL SPECIFICATIONSNumber of Contacts: 5, 7, 11, 14, 20, 26, 34, 42, 50, 75.Contact Spacing: .120" [3.05mm].Contact Gauge: #20 AWG.Minimum Creepage Path Between Contacts:.080" [2.03mm].Minimum Air Space Between Contacts: .050" [1.27mm].APPLICATIONSFor use wherever space is at a premium and a high quality connector is required in avionics, automation,communications, controls, instrumentation, missiles,computers and guidance systems.MATERIAL SPECIFICATIONSContact Pin: Brass, gold plated.Contact Socket: Phosphor bronze, gold plated.(Beryllium copper available on request.)Guides: Stainless steel, passivated.Screwlocks: Stainless steel, passivated.Standard Body: Glass-filled diallyl phthalate per MIL-M-14,Model GDI-30F, green.SM20Vishay DaleDocument Number: 36010For technical questions, contact: connectors@ For technical questions, contact: connectors@Document Number: 36010SM20Vishay DaleVishay DaleDocument Number: 36010For technical questions, contact: connectors@ Disclaimer Legal Disclaimer NoticeVishayAll product specifications and data are subject to change without notice.Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained herein or in any other disclosure relating to any product.Vishay disclaims any and all liability arising out of the use or application of any product described herein or of any information provided herein to the maximum extent permitted by law. The product specifications do not expand or otherwise modify Vishay’s terms and conditions of purchase, including but not limited to the warranty expressed therein, which apply to these products.No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of Vishay.The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications unless otherwise expressly indicated. Customers using or selling Vishay products not expressly indicated for use in such applications do so entirely at their own risk and agree to fully indemnify Vishay for any damages arising or resulting from such use or sale. Please contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications.Product names and markings noted herein may be trademarks of their respective owners.元器件交易网。

M24C32,M24C64--存储芯片手册免费下载

M24C64 M24C32
64Kbit and 32Kbit Serial I²C Bus EEPROM
FEATURES SUMMARY
■ Two-Wire I2C Serial Interface Supports 400kHz Protocol
■ Single Supply Voltage: – 4.5 to 5.5V for M24Cxx – 2.5 to 5.5V for M24Cxx-W – 1.8 to 5.5V for M24Cxx-R
Table 1. Product List
Reference
Part Number
M24C64
M24C64
M24C64-W
M24C64-R
M24C32
M24C32
M24C32-W
M24C32-R
Figure 1. Packages
8 1
PDIP8 (BN)
8 1
SO8 (MN) 150 mil width
MEMORY ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 6. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
TSSOP8 (DW) 169 mil width
UFDFPN8 (MB) 2x3mm² (MLP)

24c02中文资料

24c02中文资料1. 简介24c02是Microchip公司推出的一种串行电子可擦写可编程读写存储器，属于EEPROM（Electrically Erasable Programmable Read-Only Memory）系列。

它采用2-wire串行总线（I2C）接口，具有体积小、功耗低、可靠性高等特点。

本文档将详细介绍24c02的硬件特性、接口规范、存储容量和使用方法。

2. 硬件特性24c02的主要硬件特性如下：•存储容量：24c02有256个字节，每个字节有8位，总计拥有2Kb的存储空间。

•工作电源：24c02需要使用3.3V到5V的供电电压，支持广泛的电源电压范围。

•通信接口：24c02使用I2C串行总线进行通信，具有两根信号线：串行数据线（SDA）和串行时钟线（SCL）。

•封装类型：24c02有多种封装类型可供选择，如DIP（双列直插式封装）、SOP（小型轻负载封装）等。

3. 接口规范24c02采用I2C串行总线接口，其接口规范如下：•数据传输方式：24c02支持字节读写操作和页写操作。

字节读写操作是指每次读写一个字节的数据；页写操作是指每次可以写入8个连续字节的数据。

•起始信号和停止信号：在I2C总线上进行通信时，需要发送起始信号（Start）和停止信号（Stop）以标识数据传输的开始和结束。

•从器件地址：24c02有多个从器件地址可供选择，通过设置硬件地址引脚，可以实现多个24c02器件的级联。

4. 存储容量24c02的存储容量为2Kb，相当于256个字节。

每个字节有8位，可存储0x00到0xFF的数据。

这些存储空间可以被分为多个页，每页包含8个字节。

5. 使用方法以下是24c02的基本使用方法，供参考：•初始化：将24c02与主控芯片（如单片机）连接，并提供正常的供电电源。

同时，设置24c02的硬件地址引脚，确保能正确寻址。

•写入数据：选择要写入数据的存储地址，发送起始信号和器件地址，然后发送数据字节。

24c02中文官方资料手册pdf

当使用 24WC01 或 24WC02 时最大可级联 8 个器件如果只有一个 24WC02 被总线寻址这三个地
ｗ址输入脚 A0 A1 A2 可悬空或连接到 Vss 如果只有一个 24WC01 被总线寻址这三个地址输入
脚 A0 A1 A2 必须连接到 Vss
当使用 24WC04 时最多可连接 4 个器件该器件仅使用 A1 A2 地址管脚 A0 管脚未用可以连
符号
参数
最小
典型
最大单位
测试条件
ICC 电源电流
3
mA
FSCL=100KHz
ISB ILI ILO VIL VIH VOL1 VOL2
备用电流(Vcc=5.0V) 输入漏电流输出漏电流输入低电压输入高电压输出低电压输出低电压
1 Vcc 0.7
0
A
10
A
10
A
Vcc 0.3 V
Vcc+0.5 V
s
tHD: DAT
数据输入保持时间
0
0
ns
tSUl: DAT
数据输入建立时间
50
50
ns
tR
SDA 及 SCL 上升时间
1
0.3
s
tF
SDA 及 SCL 下降时间
300
300
ns
tSU: STO
停止信号建立时间
4
0.6
s
tDH
数据输出保持时间
100
100
ns4Biblioteka 海纳电子资讯网：ｗｗｗ．ｆｐｇａ－ａｒｍ．ｃｏｍ
上电时序
符号
参数
最大
单位
tPUR
上电到读操作
1

SM24A 调节器说明书

SM24ADamper actuator for adjusting dampers intechnical building installations• Air damper size up to approx. 4 m²• Torque motor 20 Nm• Nominal voltage AC/DC 24 V• Control Open/close, 3-pointTechnical dataElectrical data Nominal voltage AC/DC 24 VNominal voltage frequency50/60 HzNominal voltage range AC 19.2...28.8 V / DC 19.2...28.8 VPower consumption in operation 2 WPower consumption in rest position0.2 WPower consumption for wire sizing 4 VAConnection supply / control Cable 1 m, 3x 0.75 mm²Parallel operation Yes (note the performance data)Functional data Torque motor20 NmDirection of motion motor selectable with switch 0 (ccw rotation) / 1 (cwrotation)Manual override with push-button, can be lockedAngle of rotation Max. 95°Angle of rotation note can be limited on both sides with adjustablemechanical end stopsRunning time motor150 s / 90°Sound power level, motor45 dB(A)Mechanical interface Universal shaft clamp reversible 10...20 mmPosition indication Mechanical, pluggableSafety data Protection class IEC/EN III, Safety Extra-Low Voltage (SELV)Power source UL Class 2 SupplyDegree of protection IEC/EN IP54Degree of protection NEMA/UL NEMA 2Enclosure UL Enclosure Type 2EMC CE according to 2014/30/EUCertification IEC/EN IEC/EN 60730-1 and IEC/EN 60730-2-14UL Approval cULus according to UL60730-1A, UL60730-2-14and CAN/CSA E60730-1The UL marking on the actuator depends onthe production site, the device is UL-compliantin any caseHygiene test According to VDI 6022 Part 1 / SWKI VA104-01, cleanable and disinfectable, lowemissionType of action Type 1Rated impulse voltage supply / control0.8 kVPollution degree3Safety dataAmbient humidity Max. 95% RH, non-condensing Ambient temperature -30...50°C [-22...122°F]Storage temperature -40...80°C [-40...176°F]Servicingmaintenance-free WeightWeight 0.94 kg•••••••Safety notesThis device has been designed for use in stationary heating, ventilation and air-conditioning systems and must not be used outside the specified field of application, especially in aircraft or in any other airborne means of transport.Outdoor application: only possible in case that no (sea) water, snow, ice, insolation or aggressive gases interfere directly with the device and that it is ensured that the ambient conditions remain within the thresholds according to the data sheet at any time.Only authorised specialists may carry out installation. All applicable legal or institutional installation regulations must be complied with during installation.The device may only be opened at the manufacturer's site. It does not contain any parts that can be replaced or repaired by the user.Cables must not be removed from the device.To calculate the torque required, the specifications supplied by the damper manufacturers concerning the cross-section and the design, as well as the installation situation and the ventilation conditions must be observed.The device contains electrical and electronic components and must not be disposed of as household refuse. All locally valid regulations and requirements must be observed.Product featuresSimple direct mountingSimple direct mounting on the damper shaft with a universal shaft clamp, supplied with an anti-rotation device to prevent the actuator from rotating.Manual overrideManual override with push-button possible (the gear train is disengaged for as long as the button is pressed or remains locked).Adjustable angle of rotation Adjustable angle of rotation with mechanical end stops.High functional reliabilityThe actuator is overload protected, requires no limit switches and automatically stops when the end stop is reached.AccessoriesElectrical accessoriesDescriptionType Auxiliary switch 1x SPDT add-on S1A Auxiliary switch 2x SPDT add-onS2A Feedback potentiometer 140 Ω add-on P140A Feedback potentiometer 1 kΩ add-on P1000A Feedback potentiometer 10 kΩ add-onP10000A Mechanical accessoriesDescriptionType Actuator arm for standard shaft clamp (reversible)AH-20Shaft extension 240 mm ø20 mm for damper shaft ø12...21 mm CrNi AV12-25-I Shaft extension 240 mm ø20 mm for damper shaft ø8...22.7 mm AV8-25Ball joint suitable for damper crank arm KH8KG8Ball joint suitable for damper crank arm KH8 / KH10KG10A Damper crank arm Slot width 8.2 mm, clamping range ø10...18 mm KH8Shaft clamp one-sided, clamping range ø8...26 mm, Multipack 20 pcs.K-ENSA Shaft clamp one-sided, clamping range ø12...26 mm, for CrNi shaft (INOX), Multipack 20 pcs.K-ENSA-IDescription Type Shaft clamp reversible, clamping range ø10...20 mm K-SAAnti-rotation mechanism 180 mm, Multipack 20 pcs.Z-ARS180Anti-rotation mechanism 230 mm, Multipack 20 pcs.Z-ARS230 Form fit insert 10x10 mm, Multipack 20 pcs.ZF10-NSAForm fit insert 12x12 mm, Multipack 20 pcs.ZF12-NSAForm fit insert 15x15 mm, Multipack 20 pcs.ZF15-NSA Form fit insert 16x16 mm, Multipack 20 pcs.ZF16-NSA Mounting kit for linkage operation for flat installation ZG-SMA Position indicator, Multipack 20 pcs.Z-PI Baseplate extension for SM..A to SM../AM../SMD24R Z-SMAWire colours:1 = black2 = red3 = whiteElectrical installationSupply from isolating transformer.Parallel connection of other actuators possible. Observe the performance data.Wiring diagramsAC/DC 24 V, open/closeAC/DC 24 V, 3-point DimensionsSpindle lengthMin. 48Min. 20Clamping rangeWhen using a round shaft made of CrNi(INOX): ø12...20 mm。

SM20MT24C-LF-T13中文资料

SM20MT05CthruSM20MT24CST ANDARD CAP ACIT ANCE TVS ARRA YOnly One Name Means ProTek’Tion™APPLICA TIONS✔ Parallel Port✔ RS-232, RS-422 & RS-423 Data Lines ✔ Industrial & Instrumentation Equipment ✔ Board Level Interface Protection ✔ I/O Port ProtectionIEC COMPA TIBILITY (EN61000-4)✔ 61000-4-2 (ESD): Air - 15kV, Contact - 8kV ✔ 61000-4-4 (EFT): 40A - 5/50ns✔ 61000-4-5 (Surge): 24A, 8/20µs - Level 2(Line-Gnd) & Level 3(Line-Line)FEA TURES✔ 1500 Watts Peak Pulse Power per Line (tp=8/20µs)✔ ESD Protection > 40 kilovolts✔ Protection for 8 or 9 Bidirectional Data Lines ✔ Externally Low Clamping Voltage✔ Available in 4 Voltage Types Ranging From 5V to 24V ✔ Bidirectional Configuration ✔ Monolithic Design✔ RoHS Compliant in Lead-Free VersionsMECHANICAL CHARACTERISTICS✔ Molded JEDEC SO-20WB (Wide Body) Package ✔ Weight 0.5 grams (Approximate)✔ Available in Tin-Lead or Lead-Free Pure-Tin Plating(Annealed)✔ Solder Reflow Temperature:Tin-Lead - Sn/Pb, 85/15: 240-245°C Pure-Tin - Sn, 100: 260-270°C✔ Flammability rating UL 94V-0✔ 24mm Tape and Reel Per EIA Standard 481✔ Marking: Logo, Part Number, Date Code & Pin One Defined By Dot on Top of PackageSO-20WB(Wide Body)05079PIN CONFIGURA TIONSIN 1IN 2IN 3IN 4IN 5GND IN 6IN 7IN 8I N 9OUT 1OUT 2OUT 3OUT 4OUT5GND OUT 6OUT 7OUT 8OUT 9GND IN 1IN 2IN 3IN 4IN 5IN 6IN 7IN 8GND GND OUT 1OUT 2OUT 3OUT4OUT 5OUT 6OUT 7OUT 8GNDEQUAL T O 8 BIDIRECTIONAL T VS DEVICESEQUAL T O 9 BIDIRECTIONAL T VS DEVICESSM20MT05CthruSM20MT24CDEVICE CHARACTERISTICSMAXIMUM RATINGS @ 25°C Unless Otherwise SpecifiedOperating T emperature SYMBOL VALUE -55°C to 150°C°C°C -55°C to 150°C UNITS T J T STGPARAMETERStorage T emperaturePeak Pulse Power (t p = 8/20µs) - See Figure 1P PP 1500Watts ELECTRICAL CHARACTERISTICS PER LINE @ 25°C Unless Otherwise SpecifiedPART NUMBER (See Note 1)RATED ST AND-OFF VOLTAGEV WM VOLTSMINIMUM BREAKDOWN VOLTAGE@ 1mA V (BR)VOLTS MAXIMUM CLAMPING VOLTAGE (See Fig. 2)@ I PP = 10AV C VOLTSSM20MT05C SM20MT08C SM20MT15C SM20MT24C 5.08.015.024.0 6.510.018.025.09.513.023.031.011.017.026.036.0MAXIMUM LEAKAGE CURRENT@V WMI D µA MAXIMUM CAPACITANCE@V WM , 1 MHzC pF501044700360250140Note 1: These devices are bidirectional only. Electrical characteristics apply in both directions. The monolithic TVS array is based on 10 unidirec-tional P/N junctions with a common cathode and can be configured to offer 8 to 9 bidirectional lines of protection. The inputs are symmetrical and can be reversed for specific application layout requirements.MAXIMUM CLAMPING VOLTAGE (See Fig. 2)@ I PP = 25AV C VOLTSSM20MT05CthruSM20MT24CGRAPHST L - Lead Temperature - °C20406080100% O f R a t e d P o w e rFIGURE 3POWER DERATING CURVE0 5 10 15 20 25 30t - Time - µs20406080100120I P P - P e a k P u l s e C u r r e n t - %o f I P PFIGURE 20.1 1 10 100 1,000 10,000t d - Pulse Duration - µs1001,00010,000100,000P P P - P e a k P u l s e P o w e r - W a t t sFIGURE 1PEAK PULSE POWER VS PULSE TIMESM20MT05CthruSM20MT24CCOPYRIGHT © ProTek Devices 2005SPECIFICATIONS: ProTek reserves the right to change the electrical and or mechanical characteristics described herein without notice (except JEDEC).DESIGN CHANGES: ProTek reserves the right to discontinue product lines without notice, and that the final judgement concerning selection and specifications is the buyer’s and that in furnishing engineering and technical assistance, ProTek assumes no responsibility with respect to the selection or specifications of such products.P ACKAGE OUTLINE & DIMENSIONSProTek Devices2929 South Fair Lane, Tempe, AZ 85282Tel: 602-431-8101 Fax: 602-431-2288E-Mail: sales@ Web Site: 。

AT24C1024介绍

AT24C1024介绍AT24C10242 线串⾏EEPROM特性低电压操作：2.7（Vcc=2.7V to 5.5V）内部组织：131,072*8 位=1M2 线串⾏接⼝施密特触发器，噪声抑制滤波输⼊双向数据传输协议时钟速率：400kHz(2.7V)和1MHz(5V) 硬件写保护引脚和软件数据保护256 字节页写模式(允许部分页⾯写⼊)随机和顺序读写模式⾃定义写周期(5ms)⾼可靠性：耐久⼒：写周期/页100,000 次数据保留：40 年8 引脚PDIP，8 引脚有铅SOIC 封装，8 引脚⽆铅阵列和8 引脚球状dBGA 封装描述AT24C1024 提供1,048,567 位的串⾏可电擦除和可编程只读存储器（EEPROM），它的每8 位组成⼀个字节，共131,072 个字节。

该设备的级联功能允许多达2 个设备共亨同⼀条2- 线总线。

该设备适合⽤于许多⼯业和商业，应⽤必要的低功耗和低电压的操作。

该器件可提供节省空间的8 引脚PDIP，8 引脚有铅SOIC 封装，8 引脚⽆铅阵列和8 引脚球状dBGA 封装。

另外，这⼀系列产品允许在2.7V（2.7V~5.5V）下⼯作。

绝对最⼤额定值：⼯作温度：-55~+125存储温度：-65~+150任何引脚的对地电压：-1.0V~+7.0V最⼤⼯作电压：6.25V 直流输出电流：5.0mA注意：强制⾼出“绝对最⼤额定值”可能导致设备的永久损坏。

设备的压⼒等级和功能操作只有在这些或超出本规范所标明的其他任何条件下是不允许的。

长时间⼯作在绝对最⼤额定值的条件下可能影响设备的可靠性。

引脚描述：串⾏时钟（SCL）：SCL 的输⼊是在时钟的上升沿数据进⼊每个EEPROM 设备和下降沿数据输出每个设备。

串⾏数据（SDA）：SDA 引脚是双向串⾏数据传输的。

这个引脚是漏极输出的，可以与其它的漏极开路或集电极开路的设备线或。

器件/ 页地址（A1 ）：A1 引脚是设备的输⼊地址，它能够通过导线与不兼容的设备AT24C128/256/512 连接。

24C02B中文资料

FEATURES•Single supply with 5.0V operation •Low power CMOS technology - 1 mA active current typical-10 µ A standby current typical at 5.0V - 5 µ A standby current typical at 5.0V•Organized as a single block of 128 bytes (128 x 8) or 256 bytes (256 x 8)•2-wire serial interface bus, I 2 C compatible •100 kHz compatibility•Self-timed write cycle (including auto-erase)•Page-write buffer for up to 8 bytes• 2 ms typical write cycle time for page-write •Hardware write protect for entire memory •Can be operated as a serial ROM •ESD protection > 3,000V•1,000,000 ERASE/WRITE cycles guaranteed Data retention > 200 years •8 pin DIP or SOIC package•Available for extended temperature ranges DESCRIPTIONThe Microchip T echnology Inc. 24C01B and 24C02B are 1K bit and 2K bit Electrically Erasable PROMs. The devices are organized as a single block of 128 x 8 bit or 256 x 8 bit memory with a 2-wire serial interface. The 24C01B and 24C02B also have page-write capability for up to 8 bytes of data. The 24C01B and 24C02B are available in the standard 8-pin DIP and an 8-pin surface mount SOIC package.These devices are for extended temperature applications only. It is recommended that all other applications use Microchip’s 24LC01B/02B.-Automotive (E):-40˚C to +125˚C2元器件交易网24C01B/02B1.0ELECTRICAL CHARACTERISTICS1.1Maximum Ratings*V CC ...................................................................................7.0V All inputs and outputs w.r.t. V SS ................-0.6V to V CC +1.0V Storage temperature.....................................-65˚C to +150˚C Ambient temp. with power applied.................-65˚C to +125˚C Soldering temperature of leads (10 seconds).............+300˚C ESD protection on all pins............................................. ≥ 4 kV*Notice: Stresses above those listed under “Maximum ratings”may cause permanent damage to the device. This is a stress rat-ing only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this speciﬁcation is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.TABLE 1-1:PIN FUNCTION TABLEName FunctionV SS SDA SCL WP V CC NCGroundSerial Address/Data I/O Serial ClockWrite Protect Input +5.0V Power Supply No Internal ConnectionTABLE 1-1:DC CHARACTERISTICSAll parameters apply across the speci-ﬁed operating ranges unless otherwise noted.VCC = +4.5V to 5.5VAutomotive (E):Tamb = -40 ° C to 125 ° C ParameterSymbol Min.Max.Units ConditionsWP , SCL and SDA pins:High level input voltageV IH .7 V CCV Low level input voltageV IL .3 V CC V Hysteresis of Schmidt trigger inputs V HYS .05 V CC —V (Note)Low level output voltage V OL .40V I OL = 3.0 mA, V CC = 2.5V Input leakage current ILI -1010 µ A V IN = .1V to 5.5V Output leakage currentILO -1010 µ mA V OUT = .1V to 5.5VPin capacitance (all inputs/outputs)C IN , C OUT —10pF V CC = 5.0V (Note 1)Tamb = 25˚C, F CLK = 1 MHz Operating current I CC Write —3mA V CC = 5.5V , SCL = 100 kHzI CC Read —1mA Standby current ICCS—30 µ A V CC = 3.0V , SDA = SCL = VCC 100 µ AV CC = 5.5V , SDA = SCL = VCC Note:This parameter is periodically sampled and not 100% tested.元器件交易网24C01B/02BTABLE 1-2:AC CHARACTERISTICSAll Parameters apply across thespeciﬁed operating ranges unless otherwise notedVcc = 4.5V to 5.5V Automotive (E):Tamb = -40˚C to +125˚C,ParameterSymbol Min.Max.Units RemarksClock frequency F CLK —100kHz Clock high time T HIGH 4000—ns Clock low time T LOW 4700—ns SDA and SCL rise time T R —1000ns (Note 1)SDA and SCL fall time T F —300ns (Note 1)ST ART condition hold time T HD : STA 4000—ns After this period the ﬁrst clock pulse is generatedST ART condition setup time T SU : STA 4700—ns Only relevant for repeated ST ART condition Data input hold time T HD : DAT 0—ns (Note 2)Data input setup time T SU : DAT 250—ns STOP condition setup time T SU : STO 4000—ns Output valid from clock T AA —3500ns (Note 2)Bus free timeT BUF 4700—ns Time the bus must be free before a new transmission can start Output fall time from V IH minimum to V IL maximum T OF —250ns (Note 1), CB ≤ 100 pF Input ﬁlter spike suppression (SDA and SCL pins)T SP —50ns (Note 3)Write cycle time T WR —10ms Byte or Page modeEndurance—1M—cycles25 ° C, Vcc = 5.0V , Block Mode (Note 4)Note 1:Not 100% tested. CB = total capacitance of one bus line in pF .2:As a transmitter, the device must provide an internal minimum delay time to bridge the undeﬁned region(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.3:The combined T SP and VHYSspeciﬁcations are due to Schmitt trigger inputs which provide improved noisespike suppression. This eliminates the need for a TI speciﬁcation for standard operation.4:This parameter is not tested but guaranteed by characterization. For endurance estimates in a speciﬁcapplication, please consult the T otal Endurance Model which can be obtained on our BBS or website.元器件交易网24C01B/02B2.0FUNCTIONAL DESCRIPTION The 24C01B/02B supports a bi-directional two wire bus and data transmission protocol. A device that sends data onto the bus is deﬁned as transmitter, and a device receiving data as receiver. The bus has to be controlled by a master device which generates the serial clock (SCL), controls the bus access, and gener-ates the ST ART and STOP conditions, while the 24C01B/02B works as slave. Both master and slave can operate as transmitter or receiver but the master device determines which mode is activated.3.0BUS CHARACTERISTICSThe following bus protocol has been deﬁned:•Data transfer may be initiated only when the busis not busy.•During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is HIGH will be interpreted as a ST ART or STOP condition. Accordingly, the following bus conditions have been deﬁned (Figure 3-1).3.1Bus Not Busy (A)Both data and clock lines remain HIGH.3.2Start Data Transfer (B)A HIGH to LOW transition of the SDA line while the clock (SCL) is HIGH determines a ST ART condition. All commands must be preceded by a ST ART condi-tion.3.3Stop Data Transfer (C)A LOW to HIGH transition of the SDA line while the clock (SCL) is HIGH determines a STOP condition. All operations must be ended with a STOP condition.3.4Data Valid (D)The state of the data line represents valid data when, after a ST ART condition, the data line is stable for the duration of the HIGH period of the clock signal.The data on the line must be changed during the LOW period of the clock signal. There is one clock pulse per bit of data.Each data transfer is initiated with a ST ART condition and terminated with a STOP condition. The number of the data bytes transferred between the ST ART and STOP conditions is determined by the master device and is theoretically unlimited, although only the last six-teen will be stored when doing a write operation. When an overwrite does occur it will replace data in a ﬁrst in ﬁrst out fashion.3.5AcknowledgeEach receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse which is associated with this acknowledge bit. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. A master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line HIGH to enable the master to generate the STOP condition.元器件交易网24C01B/02B3.6Device AddressAfter generating a ST ART condition, the bus master transmits the slave address consisting of a 4-bit device code (1010) for the 24C01B/02B, followed by three don't care bits.The eighth bit of slave address determines if the master device wants to read or write to the 24C01B/02B (Figure 3-2).The 24C01B/02B monitors the bus for its correspond-ing slave address all the time. It generates an acknowl-edge bit if the slave address was true and it is not in a programming mode.4.0WRITE OPERATION4.1Byte WriteFollowing the start signal from the master, the device code (4 bits), the don't care bits (3 bits), and the R/W bit which is a logic low is placed onto the bus by the master transmitter. This indicates to the addressed slave receiver that a byte with a word address will follow after it has generated an acknowledge bit during the ninth clock cycle. Therefore the next byte transmitted by the master is the word address and will be written into the address pointer of the 24C01B/02B. After receiving another acknowledge signal from the 24C01B/02B the master device will transmit the data word to be written into the addressed memory location.The 24C01B/02B acknowledges again and the master generates a stop condition. This initiates the internal write cycle, and during this time the 24C01B/02B will not generate acknowledge signals (Figure 4-1).4.2Page WriteThe write control byte, word address and the ﬁrst data byte are transmitted to the 24C01B/02B in the same way as in a byte write. But instead of generating a stop condition the master transmits up to eight data bytes to the 24C01B/02B which are temporarily stored in the on-chip page buffer and will be written into the memoryafter the master has transmitted a stop condition. After the receipt of each word, the three lower order address pointer bits are internally incremented by one. The higher order ﬁve bits of the word address remains con-stant. If the master should transmit more than eight words prior to generating the stop condition, the address counter will roll over and the previously received data will be overwritten. As with the byte write operation, once the stop condition is received an inter-nal write cycle will begin (Figure 4-2).元器件交易网24C01B/02B5.0ACKNOWLEDGE POLLINGSince the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). Once the stop condition for a write com-mand has been issued from the master, the device ini-tiates the internally timed write cycle. ACK polling can be initiated immediately. This involves the master send-ing a start condition followed by the control byte for a write command (R/W = 0). If the device is still busy with the write cycle, then no ACK will be returned. If the cycle is complete, then the device will return the ACK and the master can then proceed with the next read or write command. See Figure 5-1 for ﬂow diagram. FIGURE 5-1:ACKNOWLEDGE POLLING6.0WRITE PROTECTIONThe 24C01B/02B can be used as a serial ROM when the WP pin is connected to V CC. Programming will be inhibited and the entire memory will be write-protected.7.0READ OPERATIONRead operations are initiated in the same way as write operations with the exception that the R/W bit of the slave address is set to one. There are three basic types of read operations: current address read, random read, and sequential read.7.1Current Address ReadThe 24C01B/02B contains an address counter that maintains the address of the last word accessed, inter-nally incremented by one. Therefore, if the previous access (either a read or write operation) was to address n, the next current address read operation would access data from address n + 1. Upon receipt of the slave address with R/W bit set to one, the 24C01B/ 02B issues an acknowledge and transmits the eight bit data word. The master will not acknowledge the trans-fer but does generate a stop condition and the 24C01B/ 02B discontinues transmission (Figure 7-1).7.2Random ReadRandom read operations allow the master to access any memory location in a random manner. T o perform this type of read operation, ﬁrst the word address must be set. This is done by sending the word address to the 24C01B/02B as part of a write operation. After the word address is sent, the master generates a start condition following the acknowledge. This terminates the write operation, but not before the internal address pointer is set. Then the master issues the control byte again but with the R/W bit set to a one. The 24C01B/02B will then issue an acknowledge and transmits the eight bit data word. The master will not acknowledge the transfer but does generate a stop condition and the 24C01B/02B discontinues transmission (Figure 7-2).7.3Sequential ReadSequential reads are initiated in the same way as a ran-dom read except that after the 24C01B/02B transmits the ﬁrst data byte, the master issues an acknowledge as opposed to a stop condition in a random read. This directs the 24C01B/02B to transmit the next sequen-tially addressed 8-bit word (Figure 7-3).To provide sequential reads the 24C01B/02B contains an internal address pointer which is incremented by one at the completion of each operation. This address pointer allows the entire memory contents to be serially read during one operation.7.4Noise ProtectionThe 24C01B/02B employs a V CC threshold detector cir-cuit which disables the internal erase/write logic if the V CC is below 1.5 volts at nominal conditions.The SCL and SDA inputs have Schmitt trigger and ﬁlter circuits which suppress noise spikes to assure proper device operation even on a noisy bus.元器件交易网24C01B/02B8.0PIN DESCRIPTIONS8.1Serial DataThis is a bi-directional pin used to transfer addresses and data into and data out of the device. It is an open drain terminal, therefore the SDA bus requires a pull-up resistor to V CC (typically 10 KΩ for 100 kHz).For normal data transfer SDA is allowed to change only during SCL low. Changes during SCL high are reserved for indicating the ST ART and STOP condi-tions.8.2SCL Serial ClockThis input is used to synchronize the data transfer from and to the device.8.3WPThis pin must be connected to either V SS or V CC.If tied to V SS, normal memory operation is enabled (read/write the entire memory).If tied to V CC, WRITE operations are inhibited. The entire memory will be write-protected. Read operations are not affected.This feature allows the user to use the 24C01B/02B as a serial ROM when WP is enabled (tied to V CC).元器件交易网元器件交易网24C01B/02B Array NOTES:元器件交易网24C01B/02B Array NOTES:元器件交易网24C01B/02B Array NOTES:24C01B/02BT o order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales ofﬁce.Data SheetsProducts supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom-mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:1.Y our local Microchip sales ofﬁce.2.The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277.3.The Microchip’s Bulletin Board, via your local CompuServe number (CompuServe membership NOT required).Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.元器件交易网元器件交易网MAll rights reserved. © 1997, Microchip T echnology Incorporated, USA. 12/97 Printed on recycled paper.。

英特吉小系统(SM20)简介

英特吉配置编辑器英特吉配置编辑器通常安装在笔记本电脑中，并且由施威
（ICE)
特克的工程师在安装和维护时使用。笔记本电脑可通过
SM20 前面板后的 RS232 口与 IMPS 进行连接。
管理模块 (SM20)
管理模块 SM20 监视着 IMPS 的各种功能，并且控制整流器和 LVD 的操作。所有独立模块都受监视，即任一影响系统参数的模块故障，SM20 都会产生告警。SM20 可接收来自电流、电压、温度等传感器输出的模拟信号。SM20 有 8 个继电器输出触点，也用于外部告警电路。
低压脱离 (LVD)
低压脱离保护是为了防止交流停电时间过长时导致电池过放电而影响电池寿命。用一组电子开关来控制电池的通和断，当电池电压低于预先设定的电压时，电子开关断开；当电压上升到预先设定的电压时，电子开关重新闭合。在操作过程中 LVD 接收来自监控器 SM20 的控制信号。
整流器
整流器的功能是将交流输入电压转化直流输出电压，然后给电池和负载供电。整流器的交流输入来自用户的交流输出，MS500 就是从 ACD 上接入的。每个整流器的直流输出均连接到直配模块上。SM20 通过多芯控制线控制每个整流器。整流器告警及其状态通过前面板的发光二极管显示。
负载
DCD
负A只C适D用和于
MOVs MS500）
交流输出
路
MOV 告警
背
板
进线故障告警
电池温度房间温度 7 路数字输入
键盘和显示
RS 232
8 路外部告警（数字量输出）
输入输入输入
接口延时
SM20
告警告警告警告警告警
LV电D池控电制流负载电流

AT24C1024B 1024K EEPROM 产品说明书

Features•Low-voltage Operation–1.8V(V CC=1.8V to3.6V)–2.5V(V CC=2.5V to5.5V)•Internally Organized131,072x8•Two-wire Serial Interface•Schmitt Triggers,Filtered Inputs for Noise Suppression•Bidirectional Data Transfer Protocol•400kHz(1.8V)and1MHz(5V,2.5V)Clock Rate•Write Protect Pin for Hardware and Software Data Protection•256-byte Page Write Mode(Partial Page Writes Allowed)•Random and Sequential Read Modes•Self-timed Write Cycle(5ms Typical)•High Reliability–Endurance:1,000,000Write Cycles/Page–Data Retention:40Years•8-lead PDIP,8-lead JEDEC SOIC,8-lead EIAJ SOIC,8-lead TSSOP,8-lead Ultra Thin Small Array(SAP),and8-ball dBGA2Packages•Die Sales:Wafer Form,Tape and Reel and Bumped DieDescriptionThe AT24C1024B provides1,048,576bits of serial electrically erasable and program-mable read only memory(EEPROM)organized as131,072words of8bits each.The device’s cascadable feature allows up to four devices to share a common two-wire bus.The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential.The devices are available in space-saving8-lead PDIP,8-lead JEDEC SOIC,8-lead EIAJ SOIC,8-lead TSSOP, 8-ball dBGA2and8-lead Ultra Thin SAP packages.In addition,the entire family is available in1.8V(1.8V to3.6V)and2.5V(2.5V to5.5V)versions.8-lead PDIP12348765NCA1A2GNDVCCWPSCLSDA8-lead TSSOP12348765VCCWPSCLSDANCA1A2GND8-lead SOIC12348765NCA1A2GNDVCCWPSCLSDA8-lead Ultra-Thin SAPBottom ViewVCCWPSCLSDANCA1A2GND123487658-lead dBGA2Bottom ViewVCCWPSCLSDANCA1A2GND1234876525194F–SEEPR–1/08AT24C1024B1.Absolute Maximum Ratings**NOTICE:Stresses beyond those listed under “Absolute Maximum Ratings”may cause permanent dam-age to the device.This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied.Exposure to absolute maximum rating conditions for extended periods may affect device reliability.35194F–SEEPR–1/08AT24C1024BFigure 1-1.Block Diagram2.Pin DescriptionSERIAL CLOCK (SCL):The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each device.SERIAL DATA (SDA):The SDA pin is bi-directional for serial data transfer.This pin is open-drain driven and may be wire-ORed with any number of other open-drain or open-collector devices.DEVICE/ADDRESSES (A1/A2):The A1,A2pin is a device address input that can be hardwired or left not connected for hardware compatibility with other AT24Cxx devices.When the A1,A2pins are hardwired,as many as four 1024K devices may be addressed on a single bus system (device addressing is discussed in detail under the Device Addressing section).If the A1/A2pins are left floating,the A1/A2pin will be internally pulled down to GND if the capacitive coupling to the circuit board V CC plane is <3pF.If coupling is >3pF,Atmel recommends connecting the A1/A2pin to GND.WRITE PROTECT (WP):The write protect input,when connected to GND,allows normal write operations.When WP is connected high to V CC ,all write operations to the memory are inhibited.If the pin is left floating,the WP pin will be internally pulled down to GND if the capacitive cou-pling to the circuit board V CC plane is <3pF.If coupling is >3pF,Atmel recommends connecting the pin to GND.Switching WP to V CC prior to a write operation creates a software write-protectfunction.VCC GND WP SCL SDAA 2A 1A 045194F–SEEPR–1/08AT24C1024B3.Memory OrganizationAT24C1024B,1024K SERIAL EEPROM:The 1024K is internally organized as 512pages of 256bytes each.Random word addressing requires a 17-bit data word address.IL IH Table 3-1.Pin Capacitance (1)Table 3-2.DC CharacteristicsTable 3-3.AC Characteristics (Industrial Temperature)Applicable over recommended operating range from T AI =-40︒C to +85︒C,V CC =+1.8V to +3.6V,CL =100pF (unless oth-55194F–SEEPR–1/08AT24C1024B2.AC measurement conditions:R L (connects to V CC ):1.3k Ω(2.5V,5V),10k Ω(1.8V)Input pulse voltages:0.3V CC to 0.7V CC Input rise and fall times:≤50nsInput and output timing reference voltages:0.5V CC4.Device OperationCLOCK and DATA TRANSITIONS:The SDA pin is normally pulled high with an external device.Data on the SDA pin may change only during SCL low time periods (see Figure 4-4on page 7).Data changes during SCL high periods will indicate a start or stop condition as defined below.START CONDITION:A high-to-low transition of SDA with SCL high is a start condition which must precede any other command (see Figure 4-5on page 8).Table 3-3.AC Characteristics (Industrial Temperature)Applicable over recommended operating range from T AI =-40︒C to +85︒C,V CC =+1.8V to +3.6V,CL =100pF (unless oth-65194F–SEEPR–1/08AT24C1024BSTOP CONDITION:A low-to-high transition of SDA with SCL high is a stop condition.After a read sequence,the Stop command will place the EEPROM in a standby power mode (see Fig-ure 4-5on page 8).ACKNOWLEDGE:All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words.The EEPROM sends a zero during the ninth clock cycle to acknowl-edge that it has received each word.STANDBY MODE:The AT24C1024B features a low-power standby mode which is enabled:a)upon power-up and b)after the receipt of the stop bit and the completion of any internal operations.SOFTWARE RESET:After an interruption in protocol,power loss or system reset,any 2-wire part can be protocol reset by following these steps:(a)Create a start bit condition,(b)clock 9cycles,(c)create another start bit followed by stop bit condition as shown below.The device is ready for next communication after above steps have been completed.Figure 4-1.Software ResetFigure 4-2.Bus Timing (SCL:Serial Clock,SDA:Serial Data I/O ®)SCLSDASCLSDA INSDA OUT75194F–SEEPR–1/08AT24C1024BFigure 4-3.Write Cycle Timing (SCL:Serial Clock,SDA:Serial Data I/O)Note:1.The write cycle time t WR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.Figure 4-4.DataValiditySTOP CONDITIONSTART CONDITIONSCLSDASDASCLDAT A STABLEDAT A STABLEDAT A CHANGE85194F–SEEPR–1/08AT24C1024BFigure 4-5.Start and Stop DefinitionFigure 4-6.Output Acknowledge5.Device AddressingThe 1024K EEPROM requires an 8-bit device address word following a start condition to enable the chip for a read or write operation (see Figure 7-1on page 11).The device address word con-sists of a mandatory one,zero sequence for the first four most significant bits as shown.This is common to all two-wire EEPROM devices.The 1024K uses the two device address bit,A1,A2,to allow up to four devices on the same bus.These A1,A2bits must compare to the corresponding hardwired input pins.The A1,A2pin uses an internal proprietary circuit that biases it to a logic low condition if the pin is allowed to float.The seventh bit (P 0)of the device address is a memory page address bit.This memory page address bit is the most significant bit of the data word address that follows.The eighth bit of the device address is the read/write operation select bit.A read operation is initiated if this bit is high and a write operation is initiated if this bit is low.Upon a compare of the device address,the EEPROM will output a zero.If a compare is not made,the device will return to astandby state.SDASCLSTART STOPSCLDAT A INDAT A OUTSTART ACKNOWLEDGE98195194F–SEEPR–1/08AT24C1024BDATA SECURITY:The AT24C1024B has a hardware data protection scheme that allows the user to write-protect the entire memory when the WP pin is at V CC .6.Write OperationsBYTE WRITE:To select a data word in the 1024K memory requires a 17-bit word address.The word address field consists of the P 0bit of the device address,then the most significant word address followed by the least significant word address (see Figure 7-2on page 11)A write operation requires the P 0bit and two 8-bit data word addresses following the device address word and acknowledgment.Upon receipt of this address,the EEPROM will again respond with a zero and then clock in the first 8-bit data word.Following receipt of the 8-bit data word,the EEPROM will output a zero.The addressing device,such as a microcontroller,then must terminate the write sequence with a stop condition.At this time the EEPROM enters an internally timed write cycle,T WR ,to the nonvolatile memory.All inputs are disabled during this write cycle and the EEPROM will not respond until the write is complete (see Figure 7-2on page 11).PAGE WRITE:The 1024K EEPROM is capable of 256-byte page writes.A page write is initiated the same way as a byte write,but the microcontroller does not send a stop condition after the first data word is clocked in.Instead,after the EEPROM acknowledges receipt of the first data word,the microcontroller can transmit up to 255more data words.The EEPROM will respond with a zero after each data word received.The microcontroller must ter-minate the page write sequence with a stop condition (see Figure 7-3on page 11).The data word address lower 8bits are internally incremented following the receipt of each data word.The higher data word address bits are not incremented,retaining the memory page row location.When the word address,internally generated,reaches the page boundary,the follow-ing byte is placed at the beginning of the same page.If more than 256data words are transmitted to the EEPROM,the data word address will “roll over”and previous data will be overwritten.The address “rollover”during write is from the last byte of the current page to the first byte of the same page.ACKNOWLEDGE POLLING:Once the internally timed write cycle has started and the EEPROM inputs are disabled,acknowledge polling can be initiated.This involves sending a start condition followed by the device address word.The read/write bit is representative of the operation desired.Only if the internal write cycle has completed will the EEPROM respond with a zero,allowing the read or write sequence to continue.7.Read OperationsRead operations are initiated the same way as write operations with the exception that the read/write select bit in the device address word is set to one.There are three read operations:current address read,random address read and sequential read.CURRENT ADDRESS READ:The internal data word address counter maintains the last address accessed during the last read or write operation,incremented by one.This address stays valid between operations as long as the chip power is maintained.The address “rollover”during read is from the last byte of the last memory page,to the first byte of the first page.105194F–SEEPR–1/08AT24C1024BOnce the device address with the read/write select bit set to one is clocked in and acknowledged by the EEPROM,the current address data word is serially clocked out.The microcontroller does not respond with an input zero but does generate a following stop condition (see Figure 7-4on page 11).RANDOM READ:A random read requires a “dummy”byte write sequence to load in the data word address.Once the device address word and data word address are clocked in and acknowledged by the EEPROM,the microcontroller must generate another start condition.The microcontroller now initiates a current address read by sending a device address with the read/write select bit high.The EEPROM acknowledges the device address and serially clocks out the data word.The microcontroller does not respond with a zero but does generate a follow-ing stop condition (see Figure 7-5on page 12).SEQUENTIAL READ:Sequential reads are initiated by either a current address read or a ran-dom address read.After the microcontroller receives a data word,it responds with an acknowledge.As long as the EEPROM receives an acknowledge,it will continue to increment the data word address and serially clock out sequential data words.When the memory address limit is reached,the data word address will “roll over”and the sequential read will continue.The sequential read operation is terminated when the microcontroller does not respond with a zero,but does generate a following stop condition (see Figure 7-6on page 12).115194F–SEEPR–1/08AT24C1024BFigure 7-1.Device AddressFigure 7-2.Byte WriteFigure 7-3.Page WriteFigure 7-4.Current AddressReadSIGNIFICANTMOSTSIGNIFICANTLEAST125194F–SEEPR–1/08AT24C1024BFigure 7-5.Random ReadFigure 7-6.Sequential Read135194F–SEEPR–1/08AT24C1024BNotes: 1.“-B”denotes bulk2.“-T”denotes tape and reel.SOIC =4K per reel.TSSOP and dBGA2=5K per reel.SAP =3K per reel.EIAJ =2K per reel.3.Available in tape and reel and wafer form;order as SL788for inkless wafer form.Bumped die available upon request.Pleasecontact Serial Interface Marketing.Ordering Information145194F–SEEPR–1/08AT24C1024B8.Part marking scheme8.18-SOIC(1.8V)8.28-SOIC(2.5V)TOP MARKSeal YearY = SEAL YEARWW = SEAL WEEK | Seal Week6: 2006 0: 2010 02 = Week 2 | | |7: 2007 1: 2011 04 = Week 4 |---|---|---|---|---|---|---|---| 8: 2008 2: 2012 :: : :::: : A T M L H Y W W 9: 2009 3: 2013:: : :::: :: |---|---|---|---|---|---|---|---| 50 = Week 50 2 G B 152 = Week 52|---|---|---|---|---|---|---|---| * Lot NumberLot Number to Use ALL Characters in Marking |---|---|---|---|---|---|---|---| |BOTTOM MARKPin 1 Indicator (Dot)No Bottom MarkTOP MARKSeal YearY = SEAL YEARWW = SEAL WEEK | Seal Week6: 2006 0: 2010 02 = Week 2 | | |7: 2007 1: 2011 04 = Week 4 |---|---|---|---|---|---|---|---| 8: 2008 2: 2012 :: : :::: : A T M L H Y W W 9: 2009 3: 2013:: : :::: :: |---|---|---|---|---|---|---|---| 50 = Week 50 2 G B 252 = Week 52|---|---|---|---|---|---|---|---| * Lot NumberLot Number to Use ALL Characters in Marking |---|---|---|---|---|---|---|---| |BOTTOM MARKPin 1 Indicator (Dot)No Bottom Mark155194F–SEEPR–1/08AT24C1024B8.38-TSSOP(1.8V)8.48-TSSOP(2.5V)TOP MARKPin 1 Indicator (Dot)Y = SEAL YEAR WW = SEAL WEEK |6: 2006 0: 2010 02 = Week 2 |---|---|---|---| 7: 2007 1: 2011 04 = Week 4 * H Y W W 8: 2008 2: 2012 :: : :::: : |---|---|---|---|---| 9: 2009 3: 2013:: : :::: :: 2 G B 1 50 = Week 50 |---|---|---|---|---| 52 = Week 52BOTTOM MARK|---|---|---|---|---|---|---| P H|---|---|---|---|---|---|---| A A A A A A A |---|---|---|---|---|---|---| <- Pin 1 IndicatorTOP MARKPin 1 Indicator (Dot)Y = SEAL YEAR WW = SEAL WEEK |6: 2006 0: 2010 02 = Week 2 |---|---|---|---| 7: 2007 1: 2011 04 = Week 4 * H Y W W 8: 2008 2: 2012 :: : :::: : |---|---|---|---|---| 9: 2009 3: 2013:: : :::: :: 2 G B 2 50 = Week 50 |---|---|---|---|---| 52 = Week 52BOTTOM MARK|---|---|---|---|---|---|---| P H|---|---|---|---|---|---|---| A A A A A A A |---|---|---|---|---|---|---| <- Pin 1 Indicator165194F–SEEPR–1/08AT24C1024B8.58-PDIP(1.8V)8.68-PDIP(2.5V)8.78-Ultra Thin SAP (1.8V)TOP MARKSeal YearY = SEAL YEARWW = SEAL WEEK | Seal Week6: 2006 0: 2010 02 = Week 2 | | |7: 2007 1: 2011 04 = Week 4 |---|---|---|---|---|---|---|---| 8: 2008 2: 2012 :: : :::: : A T M L U Y W W 9: 2009 3: 2013:: : :::: :: |---|---|---|---|---|---|---|---| 50 = Week 50 2 G B 152 = Week 52|---|---|---|---|---|---|---|---| * Lot NumberLot Number to Use ALL Characters in Marking |---|---|---|---|---|---|---|---| |BOTTOM MARKPin 1 Indicator (Dot)No Bottom MarkTOP MARKSeal YearY = SEAL YEARWW = SEAL WEEK | Seal Week6: 2006 0: 2010 02 = Week 2 | | |7: 2007 1: 2011 04 = Week 4 |---|---|---|---|---|---|---|---| 8: 2008 2: 2012 :: : :::: : A T M L U Y W W 9: 2009 3: 2013:: : :::: :: |---|---|---|---|---|---|---|---| 50 = Week 50 2 G B 252 = Week 52|---|---|---|---|---|---|---|---| * Lot NumberLot Number to Use ALL Characters in Marking |---|---|---|---|---|---|---|---| |BOTTOM MARKPin 1 Indicator (Dot)No Bottom MarkTOP MARKSeal Year| Seal Week Y = SEAL YEARWW = SEAL WEEK | | |6: 2006 0: 2010 02 = Week 2 |---|---|---|---|---|---|---|---| 7: 2007 1: 2011 04 = Week 4 A T M L H Y W W 8: 2008 2: 2012 :: : :::: : |---|---|---|---|---|---|---|---| 9: 2009 3: 2013:: : :::: :: 2 G B 150 = Week 50 |---|---|---|---|---|---|---|---| 52 = Week 52Lot Number|---|---|---|---|---|---|---|---| * |Pin 1 Indicator (Dot)175194F–SEEPR–1/08AT24C1024B8.88-Ultra Thin SAP (2.5V)8.9dBGA2TOP MARKSeal Year| Seal Week Y = SEAL YEARWW = SEAL WEEK | | |6: 2006 0: 2010 02 = Week 2 |---|---|---|---|---|---|---|---| 7: 2007 1: 2011 04 = Week 4 A T M L H Y W W 8: 2008 2: 2012 :: : :::: : |---|---|---|---|---|---|---|---| 9: 2009 3: 2013:: : :::: :: 2 G B 250 = Week 50 |---|---|---|---|---|---|---|---| 52 = Week 52Lot Number|---|---|---|---|---|---|---|---| * |Pin 1 Indicator (Dot)TOP MARKLINE 1-------> 2GBU LINE 2-------> PYMTC|<-- Pin 1 This CornerP = COUNTRY OF ORIGINY = ONE DIGIT YEAR CODE 4: 2004 7: 20075: 2005 8: 20086: 2006 9: 2009M = SEAL MONTH (USE ALPHA DESIGNATOR A-L) A = JANUARY B = FEBRUARY " " """"""" J = OCTOBER K = NOVEMBER L = DECEMBERTC = TRACE CODE (ATMEL LOT NUMBERS TO CORRESPONDWITH ATK TRACE CODE LOG BOOK)185194F–SEEPR–1/08AT24C1024B9.Packaging Information 8P3–PDIP195194F–SEEPR–1/08AT24C1024B8S1-JEDEC SOIC205194F–SEEPR–1/08AT24C1024B8S2–EIAJ SOICAT24C1024B 8A2-TSSOP2122AT24C1024B8U4-1-dBGA2AT24C1024B 8Y7–SAP2324AT24C1024B10.Revision HistoryHeadquarters InternationalAtmel Corporation 2325Orchard Parkway San Jose,CA95131 USATel:1(408)441-0311 Fax:1(408)487-2600Atmel AsiaRoom1219Chinachem Golden Plaza77Mody Road TsimshatsuiEast KowloonHong KongTel:(852)2721-9778Fax:(852)2722-1369Atmel EuropeLe Krebs8,Rue Jean-Pierre TimbaudBP30978054Saint-Quentin-en-Yvelines CedexFranceTel:(33)1-30-60-70-00Fax:(33)1-30-60-71-11Atmel Japan9F,Tonetsu Shinkawa Bldg.1-24-8ShinkawaChuo-ku,Tokyo104-0033JapanTel:(81)3-3523-3551Fax:(81)3-3523-7581Product ContactWeb SiteTechnical Support******************Sales Contact/contactsLiterature Requests/literatureDisclaimer:The information in this document is provided in connection with Atmel products.No license,express or implied,by estoppel or otherwise,to any intellectual property right is granted by this document or in connection with the sale of Atmel products.EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI-TIONS OF SALE LOCATED ON ATMEL’S WEB SITE,ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS,IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING,BUT NOT LIMITED TO,THE IMPLIED WARRANTY OF MERCHANTABILITY,FITNESS FOR A PARTICULAR PURPOSE,OR NON-INFRINGEMENT.IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,INDIRECT,CONSEQUENTIAL,PUNITIVE,SPECIAL OR INCIDEN-TAL DAMAGES(INCLUDING,WITHOUT LIMITATION,DAMAGES FOR LOSS OF PROFITS,BUSINESS INTERRUPTION,OR LOSS OF INFORMATION)ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT,EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice.Atmel does not make any commitment to update the information contained herein.Unless specifically provided otherwise,Atmel products are not suitable for,and shall not be used in,automotive applications.Atmel’s products are not intended,authorized,or warranted for use as components in applications intended to support or sustain life.©2008Atmel Corporation.All rights reserved.Atmel®,logo and combinations thereof,are registered trademarks or trademarks of Atmel Cor-poration or its subsidiaries.Other terms and product names may be trademarks of others.。

24C64中文资料_数据手册_参数

2.6.1 Operating supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.6.2 Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.3 Read Identification Page (M24C64-D only) . . . . . . . . . . . . . . . . . . . . . . . 21 5.4 Read the lock status (M24C64-D only) . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.1.2 Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.1.3 Write Identification Page (M24C64-D only) . . . . . . . . . . . . . . . . . . . . . . 18
5.1 Write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.1.1 Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

24c02中文资料

24C02中文资料1. 介绍24C02是一种串行电子可擦除可编程只读存储器（EEPROM），由美国Microchip Technology公司生产。

它具有2K位存储容量，可用于存储数据。

24C02具有低功耗、高可靠性和可编程性等特点，因此在许多电子设备中得到广泛应用。

2. 24C02的功能特点•存储容量：24C02具有2K位的存储容量，相当于256个字节，每个字节包含8位二进制数据。

•串行接口：24C02采用串行接口进行数据的读写操作，使得它能够与各种微处理器和其他外围设备进行通信。

•可擦除、可编程：24C02采用电子擦除可编程技术，可以对存储的数据进行擦除和编程的操作。

•低功耗：24C02在工作状态下的功耗非常低，使得它适合应用于移动设备和电池供电的设备。

•高可靠性：24C02采用了自动页写技术，具有高可靠性和稳定性，适用于各种工业和消费类电子产品。

3. 24C02的引脚图和功能说明24C02具有8个引脚，每个引脚的功能如下：•VCC：供电引脚，将其连接到供电电源即可。

•GND：地引脚，连接到系统的地线。

•SDA：串行数据输入/输出引脚，与微处理器或其他设备进行数据传输。

•SCL：串行时钟引脚，用于同步传输数据。

•WC：写控制引脚，用于控制写入和擦除操作。

•A0、A1、A2：地址选择引脚，用于选择设备的地址，使得多个设备可以同时使用。

4. 24C02的工作原理24C02采用了I2C总线协议进行数据通信，它的工作原理如下：•开始信号：主设备发出一个开始信号，通知24C02开始进行工作。

•地址传输：主设备发送一个设备地址和操作位（读或写）到24C02。

•对应设备响应：24C02将自己的设备地址进行识别，并发出一个应答信号。

•数据传输：主设备发送要读取或写入的数据到24C02。

•应答信号：24C02接收到数据后，会发出应答信号。

•停止信号：传输完成后，主设备发送一个停止信号，通知24C02本次操作结束。

SMDJ24中文资料

MDE Semiconductor, Inc.78-150 Calle Tampico, Unit 210, La Quinta, CA. U.S.A. 92253 Tel: 760-564-8656 • Fax: 760-564-2414SMDJ SERIESSURFACE MOUNT TRANSIENT VOLTAGE SUPPRESSORVOLTAGE-5.0 TO 170 Volts3000 Watt Peak Pulse PowerFEATURES• For surface mounted applications in order to optimize board space • Low profile package • Built-in strain relief• Glass passivated junction • Low inductance• Excellent clamping capability• Repetition rate (duty cycle):0.01%• Fast response time: typically less than1.0 ps from 0 volts to BV for unidirectional types • Typical IR less than 1µA above 10V • High temperature soldering: 250°C/10 seconds at terminals• Plastic package has Underwriters Laboratory Flammability Classification 94 V-OMECHANICAL DATACase: JEDEC DO214AB. Molded plastic over glass passivated junctionTerminals: Solder plated, solderable per MIL-STD-750, Method 2026Polarity: Color band denoted positive end (cathode)except BidirectionalStandard Packaging: 12mm tape (EIA STD RS-481)Weight: 0.007 ounces, 0.021 grams)DEVICES FOR BIPOLAR APPLICATIONSFor Bidirectional use C or CA Suffix for types SMDJ5.0 thru types SMDJ170 (e.g. SMDJ5.0C, SMDJ170CA)Electrical characteristics apply in both directions.MAXIMUM RATINGS AND CHARACTERISTICSRatings at 25°C ambient temperature unless otherwise specified.RATING SYMBOL VALUEUNITSPeak Pulse Power Dissipation on 10/1000 µswaveform (NOTE 1, 2, Fig.1)Ippm SEE TABLE 1Amps Superimposed on Rated Load, (JEDEC Method)(Note2, 3)Operatings and Storage Temperature Range Tj, Tstg -55 +150°C NOTES:1. Non-repetitive current pulse, per Fig.3 and derated above Ta=25 °C per Fig.2.2. Mounted on Copper Pad area of 0.8x0.8" (20x20mm) per Fig.5.3. 8.3ms single half sine-wave, or equivalent square wave, Duty cycle=4 pulses per minutes maximum.P ppmMinimum 3000Watts Peak Pulse Current of on 10/1000 µs waveform (Note 1,Fig 3)I FSM100Amps Peak Forward Surge Current, 8.3ms Single Half Sine-waveMDE Semiconductor, Inc.MDE Semiconductor, Inc.78-150 Calle Tampico, Unit 210, La Quinta, CA., USA 92253 Tel: 760-564-8656 • Fax: 760-564-2414 3000 Watt Surface Mount TVSUNI- DIRECTIONALPARTNUMBERDEVICEMARKINGCODEUNI-POLARDEVICEMARKINGCODE BI-POLARREVERSESTANDOFFVOLTAGEVRWM (V)BREAKDOWNVOLTAGEVBR (V)MIN. @ ITBREAKDOWNVOLTAGEVBR (V)MAX. @ ITTESTCURRENT(It)mAMAXIMUMCLAMPINGVOLTAGE@Ipp Vc (V)PEAKPULSECURRENTIpp (A)REVERSELEAKAGE@ VRWMIR (µA)SMDJ5.0RDD DDD 5.00 6.407.30109.6312.5800 SMDJ5.0A RDE DDE 5.00 6.407.00109.2326.1800 SMDJ6.0RDF DDF 6.00 6.678.151011.4263.2800 SMDJ6.0A RDG DDG 6.00 6.677.371010.3291.3800 SMDJ6.5RDH DDH 6.507.228.821012.3243.9500 SMDJ6.5A RDK DDK 6.507.227.981011.2267.9500 SMDJ7.0PDL DDL7.007.789.511013.3225.6200 SMDJ7.0A PDM DDM7.007.788.601012.0250.0200 SMDJ7.5PDN DDN7.508.3310.20114.3209.8100 SMDJ7.5A PDP DDP7.508.339.21112.9232.6100 SMDJ8.0PDQ DDQ8.008.8910.90115.0200.050 SMDJ8.0A PDR DDR8.008.899.83113.6220.650 SMDJ8.5PDS DDS8.509.4411.50115.9188.720 SMDJ8.5A PDT DDT8.509.4410.40114.4208.320 SMDJ9.0PDU DDU9.0010.0012.20116.9177.510 SMDJ9.0A PDV DDV9.0010.0011.10115.4194.810 SMDJ10PDW DDW10.0011.1013.60118.8159.65 SMDJ10A PDX DDX10.0011.1012.30117.0176.55 SMDJ11PDY DDY11.0012.2014.90120.1149.35 SMDJ11A PDZ DDZ11.0012.2013.50118.2164.85 SMDJ12PED DED12.0013.3016.30122.0136.45 SMDJ12A PEE DEE12.0013.3014.70119.9150.85 SMDJ13PEF DEF13.0014.4017.60123.8126.15 SMDJ13A PEG DEG13.0014.4015.90121.5139.55 SMDJ14PEH DEH14.0015.6019.10125.8116.35 SMDJ14A PEK DEK14.0015.6017.20123.2129.35 SMDJ15PEL DEL15.0016.7020.40126.9111.55 SMDJ15A PEM DEM15.0016.7018.50124.4123.05 SMDJ16PEN DEN16.0017.8021.80128.8104.25 SMDJ16A PEP DEP16.0017.8019.70126.0115.45 SMDJ17PEQ DEQ17.0018.9023.10130.598.45 SMDJ17A PER DER17.0018.9020.90127.6108.75 SMDJ18PES DES18.0020.0024.40132.293.25 SMDJ18A PET DET18.0020.0022.10129.2102.75 SMDJ20PEU DEU20.0022.2027.10135.883.85 SMDJ20A PEV DEV20.0022.2024.50132.492.65 SMDJ22PEW DEW22.0024.4029.80139.476.15 SMDJ22A PEX DEX22.0024.4026.90135.584.55 SMDJ24PEY DEY24.0026.7032.60143.069.85 SMDJ24A PEZ DEZ24.0026.7029.50138.977.15 SMDJ26PFD DFD26.0028.9035.30146.664.45 SMDJ26A PFE DFE26.0028.9031.90142.171.35 SMDJ28PFF DFF28.0031.1038.00150.159.55 SMDJ28A PFG DFG28.0031.1034.40145.466.15 SMDJ30PFH DFH30.0033.3040.70153.556.15 SMDJ30A PFK DFK30.0033.3036.80148.462.05 SMDJ33PFL DFL33.0036.7044.90159.050.85 SMDJ33A PFM DFM33.0036.7040.60153.356.35MDE Semiconductor, Inc.78-150 Calle Tampico, Unit 210, La Quinta, CA., USA 92253 Tel: 760-564-8656 • Fax: 760-564-2414 3000 Watt Surface Mount TVSUNI- DIRECTIONALPARTNUMBERDEVICEMARKINGCODEUNI-POLARDEVICEMARKINGCODE BI-POLARREVERSESTANDOFFVOLTAGEVRWM (V)BREAKDOWNVOLTAGEVBR (V)MIN. @ ITBREAKDOWNVOLTAGEVBR (V)MAX. @ ITTESTCURRENT(It)mAMAXIMUMCLAMPINGVOLTAGE@Ipp Vc (V)PEAKPULSECURRENTIpp (A)REVERSELEAKAGE@ VRWMIR (µA)SMDJ36PFN DFN36.0040.0048.90164.346.75 SMDJ36A PFP DFP36.0040.0044.20158.151.65 SMDJ40PFQ DFQ40.0044.4054.30171.442.05 SMDJ40A PFR DFR40.0044.4049.10164.546.55 SMDJ43PFS DFR43.0047.8058.40176.739.15 SMDJ43A PFT DFT43.0047.8052.80169.443.25 SMDJ45PFU DFU45.0050.0061.10180.337.45 SMDJ45A PFV DFV45.0050.0055.30172.741.35 SMDJ48PFW DFW48.0053.3065.20185.535.15 SMDJ48A PFX DFX48.0053.3058.90177.438.85 SMDJ51PFY DFY51.0056.7069.30191.132.95 SMDJ51A PFZ DFZ51.0056.7062.70182.436.45 SMDJ54A PGD DGD54.0060.0073.30196.331.25 SMDJ54A PGE DGE54.0060.0066.30187.134.45 SMDJ58PGF DGF58.0064.4078.701103.029.15 SMDJ58A PGG DGG58.0064.4071.20193.632.15 SMDJ60PGH DGH60.0066.7081.501107.028.05 SMDJ60A PGK DGK60.0066.7073.70196.831.05 SMDJ64PGL DGL64.0071.1086.901114.026.35 SMDJ64A PGM DGM64.0071.1078.601103.029.15 SMDJ70PGN DGN70.0077.8095.101125.024.05 SMDJ70A PGP DGP70.0077.8086.001113.026.55 SMDJ75PGQ DGQ75.0083.30102.001134.022.45 SMDJ75A PGR DGR75.0083.3092.101121.024.85 SMDJ78PGS DGS78.0086.70106.001139.021.65 SMDJ78A PGT DGT78.0086.7095.801126.023.85 SMDJ85PGU DGU85.0094.40115.001151.019.95 SMDJ85A PGV DGV85.0094.40104.001137.021.95 SMDJ90PGW DGW90.00100.00122.001160.018.85 SMDJ90A PGX DGX90.00100.00111.001146.020.55 SMDJ100PGY DGY100.00111.00136.001179.016.85 SMDJ100A PGZ DGZ100.00111.00123.001162.018.55 SMDJ110PHD DHD110.00122.00149.001196.015.35 SMDJ110A PHE DHE110.00122.00135.001177.016.95 SMDJ120PHF DHF120.00133.00163.001214.014.05 SMDJ120A PHG DHG120.00133.00147.001193.015.55 SMDJ130PHH DHH130.00144.00176.001230.013.05 SMDJ130A PHK DHK130.00144.00159.001209.014.45 SMDJ150PHL DHL150.00167.00204.001268.011.25 SMDJ150A PHM DHM150.00167.00185.001243.012.35 SMDJ160PHN DHN160.00178.00218.001287.010.55 SMDJ160A PHP DHP160.00178.00197.001259.011.65 SMDJ170PHQ DHQ170.00189.00231.001304.09.95 SMDJ170A PHR DHR170.00189.00209.001275.010.95 For Bidirectional type having Vrwm of 10volts and less, the IR limit is double.。

24c02中文资料 (2)

24C02中文资料1. 简介24C02是一种常用的串行EEPROM（Electrically Erasable Programmable Read-Only Memory）存储器芯片。

它采用I2C 接口进行数据交互，能够以字节为单位读写数据。

24C02广泛应用于各种电子设备中，如计算机、家电、汽车电子设备等。

2. 功能特性•容量：24C02的容量为2Kbit，即256字节。

•输入电压：2.5V至5.5V的工作电压范围。

•I2C接口：24C02采用2线制的I2C接口，支持单主机和多主机模式。

•存储器布局：24C02以字节为单位进行数据存储，每个字节有8位。

•数据保持：24C02具有数据保持能力，即在断电或上电时可以保持数据的完整性。

•写保护功能：24C02提供可编程的写保护功能，可以通过设置相应的寄存器位来保护存储器中的数据免受非授权操作。

3. 存储器结构24C02的存储器由256个字节组成，每个字节有8位数据。

存储器分为多个页面，每个页面包含16个字节。

可以通过I2C接口访问这些页面和字节，实现数据的读写操作。

4. 数据读写4.1 读操作要读取24C02中的数据，首先需发送起始条件，并将器件地址（通常为0xA0）和读命令发送到器件。

然后，按照字节的顺序读取数据。

读取操作的流程如下：1.发送起始条件。

2.发送器件地址和读命令。

3.等待器件确认。

4.读取数据。

5.发送停止条件。

4.2 写操作要向24C02写入数据，也需要发送起始条件，并将器件地址和写命令发送到器件。

然后，写入要存储的数据，并发送停止条件。

写入操作的流程如下：1.发送起始条件。

2.发送器件地址和写命令。

3.等待器件确认。

4.写入数据。

5.发送停止条件。

5. 写保护功能24C02提供了可编程的写保护功能，以保护存储器中的数据免受非授权操作。

通过设置存储器的相应寄存器位，可以开启或关闭写保护功能。

具体的设置方法可以参考24C02的数据手册。

M24C04-W1BN6T中文资料

1/25October 2005M24C16, M24C08M24C04, M24C02, M24C0116Kbit, 8Kbit, 4Kbit, 2Kbit and 1Kbit Serial I²C Bus EEPROMFEATURES SUMMARY■Two-Wire I²C Serial Interface Supports 400kHz Protocol ■Single Supply Voltage:– 2.5 to 5.5V for M24Cxx-W – 1.8 to 5.5V for M24Cxx-R ■Write Control Input■BYTE and PAGE WRITE (up to 16 Bytes)■RANDOM and SEQUENTIAL READ Modes ■Self-Timed Programming Cycle ■Automatic Address Incrementing ■Enhanced ESD/Latch-Up Protection ■More than 1 Million Erase/Write Cycles ■More than 40-Year Data Retention ■Packages–ECOPACK® (RoHS compliant)Table 1. Product ListReference Part NumberM24C16M24C16-W M24C16-R M24C08M24C08-W M24C08-R M24C04M24C04-W M24C04-R M24C02M24C02-W M24C02-R M24C01M24C01-W M24C01-RM24C16, M24C08, M24C04, M24C02, M24C01TABLE OF CONTENTSFEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Device internal reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3SIGNAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Serial Clock (SCL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Serial Data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Chip Enable (E0, E1, E2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Write Control (WC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4DEVICE OPERATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6Start Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Stop Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Acknowledge Bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Data Input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Memory Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Write Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Byte Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Minimizing System Delays by Polling On ACK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Random Address Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Current Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Sequential Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Acknowledge in Read Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11INITIAL DELIVERY STATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .242/253/25M24C16, M24C08, M24C04, M24C02, M24C01SUMMARY DESCRIPTIONThese I²C-compatible electrically erasable pro-grammable memory (EEPROM) devices are orga-nized as 2048/1024/512/256/128x 8 (M24C16,M24C08, M24C04, M24C02 and M24C01).In order to meet environmental requirements, ST offers these devices in ECOPACK® packages.ECOPACK® packages are Lead-free and RoHS compliant.ECOPACK is an ST trademark. ECOPACK speci-fications are available at: .I²C uses a two-wire serial interface, comprising a bi-directional data line and a clock line. The devic-es carry a built-in 4-bit Device Type Identifier code (1010) in accordance with the I²C bus definition.The device behaves as a slave in the I²C protocol,with all memory operations synchronized by the serial clock. Read and Write operations are initiat-ed by a Start condition, generated by the bus mas-ter. The Start condition is followed by a Device scribed in Table 3.), terminated by an acknowl-edge bit.When writing data to the memory, the device in-serts an acknowledge bit during the 9th bit time,following the bus master’s 8-bit transmission.When data is read by the bus master, the bus master acknowledges the receipt of the data byte in the same way. Data transfers are terminated by a Stop condition after an Ack for Write, and after a NoAck for Read.Table 2. Signal NamesDevice internal resetIn order to prevent inadvertent Write operations during Power-up, a Power On Reset (POR) circuit is included. At Power-up (continuous rise of V CC ),the device will not respond to any instructions until the V CC has reached the Power On Reset threshold voltage (this threshold is lower than the V CC min. operating voltage defined in DC and AC PARAMETERS ). When V CC has passed over the POR threshold, the device is reset and is in Standby Power mode. At Power-down (continuous decay of V CC ), as soon as V CC drops from the normal operating voltage to below the Power On Reset threshold voltage, the device stops responding to any instruction sent to it.Prior to selecting and issuing instructions to the memory, a valid and stable V CC voltage must be applied. This voltage must remain stable and valid until the end of the transmission of the instruction and, for a Write instruction, until the completion of the internal write cycle (t W ).Note: 1.NC = Not Connected2.See PACKAGE MECHANICAL section for package dimensions, and how to identify pin-1.E0, E1, E2Chip Enable SDA Serial Data SCL Serial Clock WCWrite Control V CC Supply Voltage V SSGroundM24C16, M24C08, M24C04, M24C02, M24C014/25SIGNAL DESCRIPTIONSerial Clock (SCL).This input signal is used to strobe all data in and out of the device. In applica-tions where this signal is used by slave devices to synchronize the bus to a slower clock, the bus master must have an open drain output, and a pull-up resistor can be connected from Serial Clock (SCL) to V CC . (Figure 5. indicates how the value of the pull-up resistor can be calculated). In most applications, though, this method of synchro-nization is not employed, and so the pull-up resis-tor is not necessary, provided that the bus master has a push-pull (rather than open drain) output.Serial Data (SDA).This bi-directional signal is used to transfer data in or out of the device. It is an open drain output that may be wire-OR’ed with other open drain or open collector signals on the bus. A pull up resistor must be connected from Se-rial Data (SDA) to V CC . (Figure 5. indicates how the value of the pull-up resistor can be calculated).Chip Enable (E0, E1, E2).These input signals are used to set the value that is to be looked for on the three least significant bits (b3, b2, b1) of the 7-bit Device Select Code. These inputs must be tied to V CC or V SS , to establish the Device Select Code as shown in Figure 4.for protecting the entire contents of the memory from inadvertent write operations. Write opera-tions are disabled to the entire memory array when nected, the signal is internally read as V IL , and Write operations are allowed.Select and Address bytes are acknowledged,Data bytes are not acknowledged.M24C16, M24C08, M24C04, M24C02, M24C01Table 3. Device Select CodeDevice Type Identifier1Chip Enable2,3RWb7b6b5b4b3b2b1b0M24C01 Select Code1010E2E1E0RWM24C02 Select Code1010E2E1E0RWM24C04 Select Code1010E2E1A8RWM24C08 Select Code1010E2A9A8RWM24C16 Select Code1010A10A9A8RW Note: 1.The most significant bit, b7, is sent first.2.E0, E1 and E2 are compared against the respective external pins on the memory device.3.A10, A9 and A8 represent most significant bits of the address.5/25M24C16, M24C08, M24C04, M24C02, M24C016/25DEVICE OPERATIONThe device supports the I²C protocol. This is sum-marized in Figure 6.. Any device that sends data on to the bus is defined to be a transmitter, and any device that reads the data to be a receiver.The device that controls the data transfer is known as the bus master, and the other as the slave de-vice. A data transfer can only be initiated by the bus master, which will also provide the serial clock for synchronization. The M24Cxx device is always a slave in all communication.Start ConditionStart is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in the High state. A Start condition must precede any data transfer command. The device continuously monitors (except during a Write cycle) Serial Data (SDA) and Serial Clock (SCL) for a Start condition,and will not respond unless one is given.Stop ConditionStop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable and driv-en High. A Stop condition terminates communica-tion between the device and the bus master. A Read command that is followed by NoAck can be followed by a Stop condition to force the device into the Stand-by mode. A Stop condition at the end of a Write command triggers the internal Write cycle.Acknowledge Bit (ACK)The acknowledge bit is used to indicate a success-ful byte transfer. The bus transmitter, whether it be bus master or slave device, releases Serial Data (SDA) after sending eight bits of data. During the 9th clock pulse period, the receiver pulls Serial Data (SDA) Low to acknowledge the receipt of the eight data bits.Data InputDuring data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock (SCL).For correct device operation, Serial Data (SDA)must be stable during the rising edge of Serial Clock (SCL), and the Serial Data (SDA) signal must change only when Serial Clock (SCL) is driv-en Low.Memory AddressingTo start communication between the bus master and the slave device, the bus master must initiate a Start condition. Following this, the bus master sends the Device Select Code, shown in Table 3.(on Serial Data (SDA), most significant bit first).The Device Select Code consists of a 4-bit Device Type Identifier, and a 3-bit Chip Enable “Address”(E2, E1, E0). To address the memory array, the 4-bit Device Type Identifier is 1010b.Each device is given a unique 3-bit code on the Chip Enable (E0, E1, E2) inputs. When the Device Select Code is received, the device only responds if the Chip Enable Address is the same as the val-ue on the Chip Enable (E0, E1, E2) inputs. How-ever, those devices with larger memory capacities (the M24C16, M24C08 and M24C04) need more address bits. E0 is not available for use on devices that need to use address line A8; E1 is not avail-able for devices that need to use address line A9,and E2 is not available for devices that need to use address line A10 (see Figure 3. and Table 3. for details). Using the E0, E1 and E2 inputs, up to eight M24C02 (or M24C01), four M24C04, two M24C08 or one M24C16 devices can be connect-ed to one I²C bus. In each case, and in the hybrid cases, this gives a total memory capacity of 16Kbits, 2KBytes (except where M24C01 devic-es are used).The 8th set to 1 for Read and 0 for Write operations.If a match occurs on the Device Select code, the corresponding device gives an acknowledgment on Serial Data (SDA) during the 9th bit time. If the device does not match the Device Select code, it deselects itself from the bus, and goes into Stand-by mode.Table 4. Operating ModesNote: 1.X = V IH or V IL .ModeRW bit WC 1Bytes Initial SequenceCurrent Address Read 1X 1START , Device Select, RW = 1Random Address Read 0X 1START , Device Select, RW = 0, Address 1X reST ART, Device Select, RW = 1Sequential Read 1X ≥ 1Similar to Current or Random Address Read Byte Write 0V IL 1START , Device Select, RW = 0Page WriteV IL≤ 16START , Device Select, RW = 0M24C16, M24C08, M24C04, M24C02, M24C01Figure 7. Write Mode Sequences with WC=1 (data write inhibited)Following a Start condition the bus master sends a Device Select Code with the Read/Write bit (RW) reset to 0. The device acknowledges this, as shown in Figure 8., and waits for an address byte. The device responds to the address byte with an acknowledge bit, and then waits for the data byte. When the bus master generates a Stop condition immediately after the Ack bit (in the “10th bit” time slot), either at the end of a Byte Write or a Page Write, the internal Write cycle is triggered. A Stop condition at any other time slot does not trigger the internal Write cycle.During the internal Write cycle, Serial Data (SDA) and Serial Clock (SCL) are ignored, and the de-vice does not respond to any requests.Byte WriteAfter the Device Select code and the address byte, the bus master sends one data byte. If the ad-dressed location is Write-protected, by Write Con-trol (WC) being driven High (during the period from byte), the device replies to the data byte with NoAck, as shown in Figure 7., and the location is not modified. If, instead, the addressed location is not Write-protected, the device replies with Ack. The bus master terminates the transfer by gener-ating a Stop condition, as shown in Figure 8.. Page WriteThe Page Write mode allows up to 16 bytes to be written in a single Write cycle, provided that they are all located in the same page in the memory: that is, the most significant memory address bits are the same. If more bytes are sent than will fit up to the end of the page, a condition known as ‘roll-over’ occurs. This should be avoided, as data starts to become overwritten in an implementation dependent way.The bus master sends from 1 to 16 bytes of data, each of which is acknowledged by the device if Write Control (WC) is Low. If the addressed loca-ing driven High (during the period from the Start7/25M24C16, M24C08, M24C04, M24C02, M24C018/25condition until the end of the address byte), the de-vice replies to the data bytes with NoAck, as shown in Figure 7., and the locations are not mod-ified. After each byte is transferred, the internalbyte address counter (the 4 least significant ad-dress bits only) is incremented. The transfer is ter-minated by the bus master generating a Stop condition.M24C16, M24C08, M24C04, M24C02, M24C01During the internal Write cycle, the device discon-nects itself from the bus, and writes a copy of the data from its internal latches to the memory cells. The maximum Write time (t w) is shown in Table 13. and Table 14., but the typical time is shorter. To make use of this, a polling sequence can be used by the bus master.The sequence, as shown in Figure 9., is:–Step 1: the bus master issues a Start condition followed by a Device Select Code (the firstbyte of the new instruction).–Step 2: if the device is busy with the internal Write cycle, no Ack will be returned and thebus master goes back to Step 1. If the device has terminated the internal Write cycle, itresponds with an Ack, indicating that thedevice is ready to receive the second part of the instruction (the first byte of this instruction having been sent during Step 1).9/25M24C16, M24C08, M24C04, M24C02, M24C0110/25Read OperationsRead operations are performed independently of The device has an internal address counter which is incremented each time a byte is read.Random Address ReadA dummy Write is first performed to load the ad-dress into this address counter (as shown in Fig-ure 10.) but without sending a Stop condition.Then, the bus master sends another Start condi-tion, and repeats the Device Select Code, with the Read/Write bit (RW) set to 1. The device acknowl-edges this, and outputs the contents of the ad-dressed byte. The bus master must not acknowledge the byte, and terminates the transfer with a Stop condition.Current Address ReadFor the Current Address Read operation, following a Start condition, the bus master only sends a De-to 1. The device acknowledges this, and outputs the byte addressed by the internal address counter. The counter is then incremented. The bus master terminates the transfer with a Stop condi-tion, as shown in Figure 10., without acknowledg-ing the byte.Sequential ReadThis operation can be used after a Current Ad-dress Read or a Random Address Read. The bus master does acknowledge the data byte output, and sends additional clock pulses so that the de-vice continues to output the next byte in sequence. To terminate the stream of bytes, the bus master must not acknowledge the last byte, and must generate a Stop condition, as shown in Figure 10.. The output data comes from consecutive address-es, with the internal address counter automatically incremented after each byte output. After the last memory address, the address counter ‘rolls-over’, and the device continues to output data from memory address 00h.Acknowledge in Read ModeFor all Read commands, the device waits, aftereach byte read, for an acknowledgment during the 9th bit time. If the bus master does not drive Serial Data (SDA) Low during this time, the device termi-nates the data transfer and switches to its Stand-by mode.INITIAL DELIVERY STATEThe device is delivered with all bits in the memory array set to 1 (each byte contains FFh).11/2512/25MAXIMUM RATINGStressing the device outside the ratings listed in Table 5. may cause permanent damage to the de-vice. These are stress ratings only, and operation of the device at these, or any other conditions out-side those indicated in the Operating sections of this specification, is not implied. Exposure to Ab-solute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.Table 5. Absolute Maximum RatingsNote: pliant with JEDEC Std J-STD-020C (for small body, Sn-Pb or Pb assembly), the ST ECOPACK ® 7191395 specification, andthe European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU2.AEC-Q100-002 (compliant with JEDEC Std JESD22-A114A, C1=100pF, R1=1500Ω, R2=500Ω)Symbol ParameterMin.Max.Unit T A Ambient Operating Temperature –40125°C T STG Storage Temperature–65150°C T LEAD Lead T emperature during Soldering 1°C V IO Input or Output range –0.50 6.5V V CC Supply Voltage–0.50 6.5V V ESDElectrostatic Discharge Voltage (Human Body model) 2–40004000V13/25DC AND AC PARAMETERSThis section summarizes the operating and mea-surement conditions, and the DC and AC charac-teristics of the device. The parameters in the DC and AC Characteristic tables that follow are de-rived from tests performed under the Measure-ment Conditions summarized in the relevant tables. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parame-ters.Table 6. Operating Conditions (M24Cxx-W)Table 7. Operating Conditions (M24Cxx-R)Table 8. DC Characteristics (M24Cxx-W, Device Grade 6)Note: 1.The voltage source driving only E0, E1 and E2 inputs must provide an impedance of less than 1kOhm.Symbol ParameterMin.Max.Unit V CC Supply Voltage2.5 5.5V T AAmbient Operating T emperature (Device Grade 6)–4085°C Ambient Operating T emperature (Device Grade 3)–40125°CSymbol ParameterMin.Max.Unit V CC Supply Voltage1.8 5.5V T AAmbient Operating T emperature–4085°CSymbol ParameterTest Condition(in addition to those in Table 6.)Min.Max.Unit I LI Input Leakage Current(SCL, SDA, E0, E1,and E2)V IN = V SS or V CC± 2µA I LO Output Leakage Current V OUT = V SS or V CC, SDA in Hi-Z ± 2µA I CCSupply CurrentV CC =5V , f c =400kHz (rise/fall time < 30ns)2mA V CC =2.5V , f c =400kHz (rise/fall time < 30ns)1mA I CC1Stand-by Supply Current V IN = V SS or V CC , V CC = 5V 1µA V IN = V SS or V CC , V CC = 2.5V0.5µA V IL Input Low Voltage (1)–0.450.3V CC V V IH Input High Voltage (1)0.7V CCV CC +1V V OLOutput Low VoltageI OL = 2.1mA, V CC = 2.5V0.4V14/25Table 9. DC Characteristics (M24Cxx-W, Device Grade 3)Note: 1.The voltage source driving only E0, E1 and E2 inputs must provide an impedance of less than 1kOhm.Table 10. DC Characteristics (M24Cxx-R)Note: 1.The voltage source driving only E0, E1 and E2 inputs must provide an impedance of less than 1kOhm.Table 11. AC Measurement ConditionsSymbol ParameterTest Condition(in addition to those in Table 6.)Min.Max.Unit I LI Input Leakage Current(SCL, SDA, E0, E1,and E2)V IN = V SS or V CC± 2µA I LO Output Leakage Current V OUT = V SS or V CC, SDA in Hi-Z ± 2µA I CCSupply CurrentV CC =5V , f C =400kHz (rise/fall time < 30ns)3mA V CC =2.5V , f C =400kHz (rise/fall time < 30ns)3mA I CC1Stand-by Supply Current V IN = V SS or V CC , V CC = 5V 5µA V IN = V SS or V CC , V CC = 2.5V2µA V IL Input Low Voltage (1)–0.450.3V CC V V IH Input High Voltage (1)0.7V CCV CC +1V V OLOutput Low VoltageI OL = 2.1mA, V CC = 2.5V0.4VSymbol ParameterTest Condition(in addition to those in Table 7.)Min.Max.Unit I LI Input Leakage Current(SCL, SDA, E0, E1,and E2)V IN = V SS or V CC± 2µA I LO Output Leakage Current V OUT = V SS or V CC, SDA in Hi-Z ± 2µA I CC Supply CurrentV CC =1.8V , f c =400kHz (rise/fall time < 30ns)0.8mA I CC1Stand-by Supply Current V IN = V SS or V CC , V CC = 1.8V0.3µA V IL Input Low Voltage (1) 2.5V ≤ V CC –0.450.3V CC V 1.8V ≤ V CC < 2.5V–0.450.25V CC V V IH Input High Voltage (1)0.7V CC V CC +1V V OLOutput Low VoltageI OL = 0.7mA, V CC = 1.8V 0.2VSymbol ParameterMin.Max.Unit C LLoad Capacitance 100pF Input Rise and Fall Times 50ns Input Levels0.2V CC to 0.8V CC V Input and Output Timing Reference Levels0.3V CC to 0.7V CCV15/25Table 12. Input ParametersNote: 1.T A = 25°C, f = 400kHz2.Sampled only, not 100% tested.Symbol Parameter 1,2Test ConditionMin.Max.Unit C IN Input Capacitance (SDA)8pF C IN Input Capacitance (other pins)6pF Z WCL WC Input Impedance V IN < 0.3V 1570k ΩZ WCH WC Input Impedance V IN > 0.7V CC 500k Ωt NSPulse width ignored(Input Filter on SCL and SDA)Single glitch100nsTable 13. AC Characteristics (M24Cxx-W)Test conditions specified in Table 6. and Table 11.Symbol Alt.Parameter Min.Max.Unitf C f SCL Clock Frequency400kHzt CHCL t HIGH Clock Pulse Width High600ns t CLCH t LOW Clock Pulse Width Low1300nst DL1DL2 2t F SDA Fall Time20300ns t DXCX t SU:DAT Data In Set Up Time100ns t CLDX t HD:DA T Data In Hold Time0ns t CLQX t DH Data Out Hold Time200ns t CLQV 3t AA Clock Low to Next Data Valid (Access Time)200900ns t CHDX 1t SU:ST A Start Condition Set Up Time600ns t DLCL t HD:ST A Start Condition Hold Time600ns t CHDH t SU:STO Stop Condition Set Up Time600ns t DHDL t BUF Time between Stop Condition and Next Start Condition1300ns t W 4t WR Write Time5ms Note: 1.For a reSTART condition, or following a Write cycle.2.Sampled only, not 100% tested.3.To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.4.Previous devices bearing the process letter “L” in the package marking guarantee a maximum write time of 10ms. For more infor-mation about these devices and their device identification, please ask your ST Sales Office for Process Change Notices PCN MPG/ EE/0061 and 0062 (PCEE0061 and PCEE0062).Table 14. AC Characteristics (M24Cxx-R)Test conditions specified in Table 7. and Table 10.Symbol Alt.Parameter Min. 4Max. 4Unitf C f SCL Clock Frequency400kHzt CHCL t HIGH Clock Pulse Width High600ns t CLCH t LOW Clock Pulse Width Low1300nst DL1DL2 2t F SDA Fall Time20300ns t DXCX t SU:DAT Data In Set Up Time100ns t CLDX t HD:DA T Data In Hold Time0ns t CLQX t DH Data Out Hold Time200ns t CLQV 3t AA Clock Low to Next Data Valid (Access Time)200900ns t CHDX 1t SU:ST A Start Condition Set Up Time600ns t DLCL t HD:ST A Start Condition Hold Time600ns t CHDH t SU:STO Stop Condition Set Up Time600ns t DHDL t BUF Time between Stop Condition and Next Start Condition1300ns t W t WR Write Time10ms Note: 1.For a reSTART condition, or following a Write cycle.2.Sampled only, not 100% tested.3.To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.4.This is preliminary information.16/2517/25PACKAGE MECHANICALTable 15. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Mechanical DataSymb.mm inchesTyp.Min.Max.Typ.Min.Max.A 5.330.210A10.380.015A2 3.30 2.92 4.950.1300.1150.195 b0.460.360.560.0180.0140.022 b2 1.52 1.14 1.780.0600.0450.070 c0.250.200.360.0100.0080.014 D9.279.0210.160.3650.3550.400 E7.877.628.260.3100.3000.325 E1 6.35 6.107.110.2500.2400.280e 2.54––0.100––eA7.62––0.300––eB10.920.430 L 3.30 2.92 3.810.1300.1150.15018/25Note:Drawing is not to scale.Table 16. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Mechanical DataSymb.mm inchesTyp.Min.Max.Typ.Min.Max.A 1.35 1.750.0530.069A10.100.250.0040.010B0.330.510.0130.020C0.190.250.0070.010D 4.80 5.000.1890.197E 3.80 4.000.1500.157e 1.27––0.050––H 5.80 6.200.2280.244h0.250.500.0100.020L0.400.900.0160.035α0°8°0°8°N88CP0.100.00419/25Note: 1.Drawing is not to scale.2.The central pad (the area E2 by D2 in the above illustration) is pulled, internally, to V SS. It must not be allowed to be connected toany other voltage or signal line on the PCB, for example during the soldering process.Table 17. UFDFPN8 (MLP8) 8-lead Ultra thin Fine pitch Dual Flat Package No lead 2x3mm², DataSymbolmm inchesTyp.Min.Max.Typ.Min.Max.A0.550.500.600.0220.0200.024 A10.000.050.0000.002 b0.250.200.300.0100.0080.012D 2.000.079D2 1.55 1.650.0610.065 ddd0.050.002E 3.000.118E20.150.250.0060.010 e0.50––0.020––L0.450.400.500.0180.0160.020 L10.150.006 L30.300.012N8820/25。

FM24C256-SE资料

This product conforms specifications per the terms of the Ramtron Ramtron International Corporationstandard warranty. Production processing does not necessarily 1850 Ramtron Drive, Colorado Springs, CO 80921 include testing of all parameters. (800) 545-FRAM, (719) 481-7000, Fax (719) 481-7058Low Power Operation A Active Current (100 kHz) A Standby Current DescriptionThe FM24C256 is a 256-kilobit nonvolatile memoryemploying an advanced ferroelectric process. A ferroelectric random access memory or FRAM is nonvolatile and performs reads and writes like a RAM. It provides reliable data retention for 10 years while eliminating the complexities, overhead, and system level reliability problems caused by EEPROM and other nonvolatile memories.The FM24C256 performs write operations at bus speed. No write delays are incurred. The next bus cycle may commence immediately without the need for data polling. In addition, the product offers write endurance orders of magnitude higher than EEPROM. Also, FRAM exhibits much lower power during writes than EEPROM since write operations do not require an internally elevated power supply voltage for write circuits.These capabilities make the FM24C256 ideal for nonvolatile memory applications requiring frequent or rapid writes. Examples range from data collection where the number of write cycles may be critical, to demanding industrial controls where the long write time of EEPROM can cause data loss. The combination of features allows more frequent data writing with less overhead for the system.The FM24C256 is available in a 8-pin EIAJ SO IC package using an industry standard two-wire protocol. Specifications are guaranteed over an industrial temperature range of -40°C to +85°C. Pin ConfigurationA0A1A2VSSVDD WP SCL SDAPin Names Function A0-A2 Device Select Address SDA Serial Data/Address SCL Serial Clock WP Write Protect VSS Ground VDD Supply Voltage 5VOrdering InformationFM24C256-SE 8-pin EIAJ SO ICNOTE: Top side part marking is “FM24C256-S” whereas “FM24C256-SE” is used only for ordering.Figure 1. Block DiagramPin DescriptionPin Name Type Pin DescriptionA0-A2 Input Address 2-0: These pins are used to select one of up to 8 devices of the same type on the same two-wire bus. To select the device, the address value on the three pins mustmatch the corresponding bits contained in the device address. The address pins arepulled down internally.WP Input Write Protect: When WP is high, the entire array will be write-protected. When WP is low, all addresses may be written. This pin is internally pulled down.SDA I/O Serial Data/Address: This is a bi-directional input used to shift serial data and addresses for the two-wire interface. It employs an open-drain output and is intendedto be wire-OR’d with other devices on the two-wire bus. The input buffer incorporatesa Schmitt trigger for improved noise immunity and the output driver has slope controlfor falling edges. An external pull-up resistor is required.SCL Input Serial Clock: The serial clock input for the two-wire interface. Data is clocked out of the device on the SCL falling edge, and clocked in on the SCL rising edge. The SCLinput also incorporates a Schmitt trigger input for improved noise immunity.VDD Supply Supply Voltage: 5VGroundVSS SupplyOverviewThe FM24C256 is a serial FRAM memory. The memory array is logically organized as 32,768 x 8 bit memory array and is accessed using an industry standard two-wire interface. Functional operation of the FRAM is similar to serial EEPROMs. The major difference between the FM24C256 and a serial EEPROM relates to its superior write performance. Memory ArchitectureWhen accessing the FM24C256, the user addresses 32,768 locations each with 8 data bits. These data bits are shifted serially. The 32,768 addresses are accessed using the two-wire protocol, which includes a slave address (to distinguish from other non-memory devices), and an extended 16-bit address. Only the lower 15 bits are used by the decoder for accessing the memory. The upper address bit should be set to 0 for compatibility with higher density devices in the future.The memory is read or written at the speed of the two-wire bus. Unlike an EEPROM, it is not necessary to poll the device for a ready condition since writes occur at bus speed. By the time a new bus transaction can be shifted into the part, a write operation is complete. This is explained in more detail in the interface section below.Users can expect several obvious system benefits from the FM24C256 due to its fast write cycle and high endurance as compared with EEPROM. However there are less obvious benefits as well. For example in a high noise environment, the fast-write operation is less susceptible to corruption than an EEPROM since the write cycle is completed quickly. By contrast, an EEPROM requiring milliseconds to write is vulnerable to noise during much of the cycle. Note that the FM24C256 contains no power management circuits other than a simple internal power-on reset. It is the user’s responsibility to ensure that V DD is maintained within data sheet tolerances to prevent incorrect operation. Two-wire InterfaceThe FM24C256 employs a bi-directional two-wire bus protocol using few pins and little board space. Figure 2 illustrates a typical system configuration using the FM24C256 in a microcontroller-based system. The industry standard two-wire bus is familiar to many users but is described in this section. By convention, any device that is sending data onto the bus is the transmitter while the target device for this data is the receiver. The device that is controlling the bus is the master. The master is responsible for generating the clock signal for all operations. Any device on the bus that is being controlled is a slave. The FM24C256 is always a slave device.The bus protocol is controlled by transition states in the SDA and SCL signals. There are four conditions including Start, Stop, Data bit, and Acknowledge. Figure 3 illustrates the signal conditions that specify the four states. Detailed timing diagrams are shown in the electrical specifications.VDD Figure 2. Typical System Configuration(Master)(Master)(Transmitter)(Transmitter)(Receiver)Figure 3. Data Transfer ProtocolStop ConditionA Stop condition is indicated when the bus master drives SDA from low to high while the SCL signal is high. All operations using the FM24C256 must end with a Stop condition. If an operation is pending when a Stop is asserted, the operation will be aborted. The master must have control of SDA (not a memory read) in order to assert a Stop condition.Start ConditionA Start condition is indicated when the bus master drives SDA from high to low while the SCL signal is high. All read and write transactions begin with a Start condition. An operation in progress can be aborted by asserting a Start condition at any time. Aborting an operation using the Start condition will ready the FM24C256 for a new operation.If during operation the power supply drops below the specified VDD minimum, the system should issue a Start condition prior to performing another operation. Data/Address TransferAll data transfers (including addresses) take place while the SCL signal is high. Except under the two conditions described above, the SDA signal should not change while SCL is high.AcknowledgeThe Acknowledge takes place after the 8th data bit has been transferred in any transaction. During this state the transmitter should release the SDA bus to allow the receiver to drive it. The receiver drives the SDA signal low to acknowledge receipt of the byte. If the receiver does not drive SDA low, the condition is a No-Acknowledge and the operation is aborted. The receiver would fail to acknowledge for two distinct reasons. First is that a byte transfer fails. In this case, the No-Acknowledge ends the current operation so that the part can be addressed again. This allows the last byte to be recovered in the event of a communication error. Second and most common, the receiver does not acknowledge to deliberately end an operation. For example, during a read operation, the FM24C256 will continue to place data onto the bus as long as the receiver sends Acknowledges (and clocks). When a read operation is complete and no more data is needed, the receiver must not acknowledge the last byte. If the receiver acknowledges the last byte, this will cause the FM24C256 to attempt to drive the bus on the next clock while the master is sending a new command such as Stop.Slave AddressThe first byte that the FM24C256 expects after a Start condition is the slave address. As shown in Figure 4, the slave address contains the Slave ID (device type), the device select address bits, and a bit that specifies if the transaction is a read or a write. Bits 7-4 define the device type and must be set to 1010b for the FM24C256. These bits allow other types of function types to reside on the 2-wire bus within an identical address range. Bits 3-1 are the device select bits which are equivalent to chip select bits. They must match the corresponding value on the external address pins to select the device. Up to eight FM24C256 devices can reside on the same two-wire bus by assigning a different address to each. Bit 0 is the read/write bit. A 1 indicates a read operation, and a 0 indicates a write.1010A2A1A0R/WSlaveIDDeviceSelect76543210Figure 4. Slave AddressAddressing OverviewAfter the FM24C256 (as receiver) acknowledges the device address, the master can place the memory address on the bus for a write operation. The address requires two bytes. The first is the MSB (upper byte). Since the device uses only 15 address bits, the value of the upper bits is a “don’t care”. Following the MSB is the LSB (lower byte) with the remaining eight address bits. The address value is latched internally. Each access causes the latched address value to be incremented automatically. The current address is the value that is held in the latch, either a newly written value or the address following the last access. The current address will be held as long as power remains or until a new value is written. Reads always use the current address. A random read address can be loaded by beginning a write operation as explained below.After transmission of each data byte, just prior to the acknowledge, the FM24C256 increments the internal address latch. This allows the next sequential byte to be accessed with no additional addressing externally. After the last address (7FFFh) is reached, the address latch will roll over to 0000h. There is no limit to the number of bytes that can be accessed with a single read or write operation.Data TransferAfter the address information has been transmitted, data transfer between the bus master and the FM24C256 can begin. For a read operation the FM24C256 will place 8 data bits on the bus then wait for an Acknowledge from the master. If the Acknowledge occurs, the FM24C256 will transfer the next sequential byte. If the Acknowledge is not sent, the FM24C256 will end the read operation. For a write operation, the FM24C256 will accept 8 data bits from the master then send an acknowledge. All data transfer occurs MSB (most significant bit) first. Memory OperationThe FM24C256 is designed to operate in a manner very similar to other 2-wire interface memory products. The major differences result from the higher performance write capability of FRAM technology. These improvements result in some differences between the FM24C256 and a similar configuration EEPROM during writes. The complete operation for both writes and reads is explained below. Write OperationAll writes begin with a device address, then a memory address. The bus master indicates a write operation by setting the LSB of the device address to a 0. After addressing, the bus master sends each byte of data to the memory and the memory generates an acknowledge condition. Any number of sequential bytes may be written. If the end of the address range is reached internally, the address counter will wrap from 7FFFh to 0000h.Unlike other nonvolatile memory technologies, there is essentially no write delay with FRAM. Since the read and write access times of the underlying memory are the same, the user experiences no delay on the bus. The entire memory cycle occurs in less time than a single bus clock. Therefore, any operation including a read or write can occur immediately following a write. Acknowledge polling, a technique used with EEPROMs to determine if a write has completed is unnecessary and will always return a ready condition.Internally, an actual memory write occurs after the 8th data bit is transferred. It will be complete before the Acknowledge is sent. Therefore, if the user desires to abort a write without altering the memory contents, this should be done using a Start or Stop condition prior to the 8th data bit. The FM24C256 uses no page buffering.The memory array can be write protected using the WP pin. Pulling the WP pin high will write-protect all addresses. The FM24C256 will not acknowledge data bytes that are written when WP is active. In addition, the address counter will not increment if writes are attempted to these addresses. Setting WP low will deactivate this feature. WP is internally pulled down. The state of WP should remain stable from the Start command until the address is complete.Figure 5 and 6 below illustrate both a single-byte and multiple-write.By MasterAcknowledgeFigure 5. Single Byte WriteFigure 6. Multiple Byte WriteRead OperationThere are two types of read operations. They arecurrent address read and selective address read. In acurrent address read, the FM24C256 uses the internaladdress latch to supply the address. In a selectiveread, the user performs a procedure to set the addressto a specific value.Current Address & Sequential ReadAs mentioned above the FM24C256 uses an internallatch to supply the address for a read operation. Acurrent address read uses the existing value in theaddress latch as a starting place for the readoperation. The system reads from the addressimmediately following that of the last operation.To perform a current address read, the bus mastersupplies a device address with the LSB set to 1. Thisindicates that a read operation is requested. Afterreceiving the complete device address, theFM24C256 will begin shifting out data from thecurrent address on the next clock. The current addressis the value held in the internal address latch.Beginning with the current address, the bus mastercan read any number of bytes. Thus, a sequential readis simply a current address read with multiple bytetransfers. After each byte, the internal addresscounter will be incremented.Each time the bus master acknowledges a byte, thisindicates that the FM24C256 should read out the nextsequential byte.There are four ways to properly terminate a readoperation. Failing to properly terminate the read willmost likely create a bus contention as the FM24C256attempts to read out additional data onto the bus. Thefour valid methods are as follows.1. The bus master issues a no-acknowledge in the9th clock cycle and a stop in the 10th clock cycle.This is illustrated in the diagrams below. This ispreferred.2. The bus master issues a no-acknowledge in the9th clock cycle and a start in the 10th.3. The bus master issues a stop in the 9th clockcycle.4. The bus master issues a start in the 9th clockcycle.If the internal address reaches 7FFFh, it will wraparound to 0000h on the next read cycle. Figures 7 and8 show the proper operation for current address reads.Selective (Random) ReadThere is a simple technique that allows a user toselect a random address location as the starting pointfor a read operation. This involves using the firstthree bytes of a write operation to set the internaladdress followed by subsequent read operations.To perform a selective read, the bus master sends outthe device address with the lsb set to 0. This specifiesa write operation. According to the write protocol,the bus master then sends the address bytes that areloaded into the internal address latch. After theFM24C256 acknowledges the address, the bus masterissues a Start condition. This simultaneously abortsthe write operation and allows the read command tobe issued with the device address LSB set to a 1. Theoperation is now a current address read.Electrical SpecificationsAbsolute Maximum RatingsSymbol Description RatingsV DD Voltage on V DD with respect to V SS-1.0V to +7.0VV IN Voltage on any signal pin with respect to V SS-1.0V to +7.0Vand V IN < V DD+1.0VT STG Storage Temperature -40°C to + 85°CT LEAD Lead temperature (Soldering, 10 seconds) 300° CStresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device.This is a stress rating only, and the functional operation of the device at these or any other conditions abovethose listed in the operational section of this specification is not implied. Exposure to absolute maximumratings conditions for extended periods may affect device reliabilityDC Operating Conditions (T A = -40° C to + 85° C, V DD = 4.5V to 5.5V unless otherwise specified)Symbol Parameter MinTypMaxUnitsNotes V DD MainPowerSupply 4.5 5.0 5.5 VI DD VDD Supply Current@ SCL = 100 kHz @ SCL = 400 kHz @ SCL = 1 MHz 2005001.2µAµAmA1I SB StandbyCurrent 100 µA 2I LI Input Leakage Current 10 µA 3I LO Output Leakage Current 10 µA 3V IH Input High Voltage 0.7 V DD V DD + 0.5 V 4V IL Input Low Voltage -0.3 0.3 V DD V 4V OL Output Low Voltage@ I OL = 3 mA 0.4VR IN Address Input Resistance (WP, A2-A0)For V IN = V IL(max) For V IN = V IH(min)201KΩMΩ5V HYS Input Hysteresis 0.05 V DD V 4 Notes1. SCL toggling between V DD-0.3V and V SS, other inputs V SS or V DD-0.3V2. SCL = SDA = V DD. All inputs V SS or V DD. Stop command issued.3. V IN or V OUT = V SS to V DD. Does not apply to pins with internal pull down resistors.4. This parameter is characterized but not tested.5. The input pull-down circuit is strong (20KΩ) when the input voltage is below V IL and weak (1MΩ) when the input voltageis above V IH. This resistance is characterized and not tested.AC Parameters (T A = -40° C to + 85° C, V DD = 4.5V to 5.5V, C L = 100 pF unless otherwise specified) Symbol Parameter Min Max Min Max Min Max Units Notes f SCL SCL Clock Frequency 0 100 0 400 0 1000 kHz t LOW Clock Low Period 4.7 1.3 0.6 µs t HIGH Clock High Period 4.0 0.6 0.4 µs t AA SCL Low to SDA Data Out Valid 3 0.9 0.55 µs t BUFBus Free Before NewTransmission4.7 1.3 0.5 µs t HD:STA Start Condition Hold Time 4.0 0.6 0.25 µst SU:STA Start Condition Setup for RepeatedStart4.7 0.6 0.25 µst HD:DAT Data In Hold 0 0 0 ns t SU:DAT Data In Setup 250 100 100 ns t R Input Rise Time 1000 300 300 ns 1 t F Input Fall Time 300 300 100 ns 1 t SU:STO Stop Condition Setup 4.0 0.6 0.25 µst DH Data Output Hold(from SCL @ VIL)0 0 0 ns t SP Noise Suppression Time Constanton SCL, SDA50 50 50 nsNotes : All SCL specifications as well as start and stop conditions apply to both read and write operations.1 This parameter is periodically sampled and not 100% tested.Data Retention (V DD = 4.5V to 5.5V unless otherwise specified)Parameter Min Units NotesData Retention 10 Years 1Notes1. The relationship between retention, temperature, and the associated reliability level ischaracterized separately.Capacitance (T A = 25° C, f=1.0 MHz, V DD = 5V)Symbol Parameter Max Units Notes C I/O Input/output capacitance (SDA) 8 pF 1C IN Input capacitance 6 pF 1Notes1 This parameter is periodically sampled and not 100% tested.AC Test ConditionsEquivalent AC Load CircuitInput Pulse Levels0.1 V DD to 0.9 V DD Input rise and fall times10 ns Input and output timing levels 0.5 V DDOutputDiagram NotesAll start and stop timing parameters apply to both read and write cycles. Clock specifications are identical for read and write cycles. Write timing parameters apply to slave address, word address, and write data bits. Functional relationships are illustrated in the relevant data sheet sections. These diagrams illustrate the timing parameters only.Read Bus TimingSCLSDAWrite Bus TimingStartSCLSDA8-pin EIAJ SO ICControlling dimensions in millimeters.Conversions to inches are not necessarily exact. Symbol Dim Min Nom. Max A mm in. 1.78 0.07 2.030.08A1 mm in. 0.05 0.002 0.250.0098B mm in. 0.36 0.014 0.480.019C mm in. 0.19 0.0075 0.240.0095D mm in. 5.13 0.202 5.33 0.210E mm in. 5.18 0.2045.380.212e mm in. 1.27 BSC 0.050 BSCH mm in. 7.75 0.305 8.260.325L mm in. 0.51 0.02 0.760.03 α 0° 8°Pin 1Revision HistoryRevision Date SummaryInitialRelease1.0 4/10/011.1 9/28/01 Changed Idd and Isb specifications. Changed test load to 1700 ohms to reflect3mA V OL test condition.1.2 1/31/02 Updated package drawing and dimensions. Rewrote description of theinternal memory architecture and endurance section.1.3 2/3/04 Added “part marking” note to Ordering Information (pg 1).。

MT-24AC-4系列光源控制器说明书-OEM

MT-24AC-4系列LED数字式远程光源控制器使用说明书1温馨提示1、请仔细阅读该使用说明书。

2、使用电源前，请确认电源的输出规格（电压、功率）与所用LED光源的电源规格是否相同。

3、接线时务必切断输入电源。

通电前仔细检查输入输出线是否连接正确，确保电源可靠工作。

4、测量电源外壳与输入输出的绝缘电阻，以免触电。

5、为保证使用的安全性和减少干扰，请确保输入电源的地线可靠接地。

6、为确保电源正常可靠地工作，在使用电源时请不要超载。

7、对电源输入频繁开关（即频繁开通和切断输入电压）将会影响电源的寿命。

2MT-24AC-4型电源是本公司为驱动LED光源而设计的可编程数字控制器。

其具有以下几种功能：255级亮度调节功能、计算机通信功能（RS232接口）、触发功能（软件触发和硬件触发均可）。

通过RS232接口将电源控制器与计算机相连，即可通过软件远程对LED光源实现256级亮度调节功能，并可远程控制LED光源的开关，可大大延长LED光源的使用寿命，尤适用于机器视觉行业的LED型光源的应用。

亮度等级：255级连续可调控制方式：PWM输出电流：0~400mA电流（整机输出电流应小于1.6A）RS232通讯波特率：9600bps外部触发控制：触发电平：高电平—OFF，低电平—ON触发延迟时间：10uS外形尺寸：145×127×55mm工作环境：温度0~45℃湿度20~80%存贮环境：温度-10~70℃湿度10~90%二、主要功能⇳手动调节亮度可通过面板上的“+”、“-”按键分别对每一个输出通道进行亮度等级的增加或减少⇳远程数字调节亮度通过RS232接口，在计算机应用软件的界面上，设置每一个输出通道的电流级别。

远程触发开关通过触发信号，可远程控制光源的开关三、使用说明控制器的使用非常简单，前后面板极为简洁，前面板四位数码管的第一位显示为“通道”显示位，可通过“SEL”按键来选择要设定的通道号，后三位则为当前指示通道输出的亮度等级。

24C02C芯片介绍

24C02C介绍24C02C是一款由Microchip Technology Inc.（微芯科技股份有限公司）生产的EEPROM（Electrically Erasable Programmable Read-Only Memory，电可擦可编程只读存储器）芯片。

以下是关于该芯片的主要特性和参数的详细介绍：基本参数：容量：2Kb（即256字节），表示为256x8位。

接口：I²C（Inter-Integrated Circuit，集成电路总线）接口，支持最高400kHz的时钟频率。

供电电压：4.5V至5.5V。

工作温度：0°C至70°C。

封装形式：8-SOIC（0.154", 3.90mm宽），提供PDIP/SOIC和TSSOP 两种封装选项。

引脚定义：Vss：接地。

SDA：串行数据线。

SCL：串行时钟。

Vcc：+4.5到5.5V电源。

A0、A1、A2：片选信号。

WP：硬件写保护。

特性：非易失性：数据在电源关闭后仍能保持。

数据保留时间超过200年。

保证的擦除/写入周期达到1,000,000次。

串行接口允许与各种微控制器和处理器进行简单的通信。

应用：由于其小容量和非易失性特性，24C02C通常用于存储需要持久保存但数据量不大的数据，如配置信息、校准参数等。

它常见于各种嵌入式系统、微控制器应用以及需要长期存储数据的场合。

其他信息：数据手册提供了详细的规格参数和应用指南，包括读写时序、操作命令等。

可以通过I²C接口进行读写操作，具体的读写过程需要遵循EEPROM 的通信协议。

综上所述，24C02C是一款功能强大、体积小巧的EEPROM芯片，适用于各种需要长期存储小量数据的嵌入式系统和微控制器应用。