OX2551A中文资料
东芝2051-2551维修手册Weiss故障排除手册
感谢您购买东芝多功能彩色数码复印机。本手册描述如何解决使用设备时发生的问题。请把本手册放在触手可及的地方， 并用它来配置一个能最佳使用 e-STUDIO 功能的环境。 公司拥有手册的最终解释权。手册中的不当之处在所难免，敬请谅解。手册中的相关图片请以实际安装后的图片为准。
前言 1
2 前言
目录
第一章
第二章 第三章
前言 ............................................................................................................................................ 1
指出操作设备时您应注意的信息。
此外，本手册也使用以下标记，描述了便于操作本设备的有用信息：
ᦤ冫
描述了有利于设备操作的便捷信息。 表示页面所描述的内容与您当前所做的有关。根据需要，参见这些页面。
选购件
关于可用的选购件，请参阅随机的 《快速开始手册》中的 “选购件”。
屏幕
y 根据设备的使用环境，例如：选购件的安装状态，本手册中的屏幕可能会与实际情况不同。 y 本手册中的屏幕以使用 A/B 型纸张为例。如果使用 LT 型纸张时，则按键的显示或顺序可能会与您的设备不同。
清除卡纸 ................................................................................................................................... 14 确定卡纸位置 ....................................................................................................................... 14 清除卡纸 .............................................................................................................................. 15 自动双面输稿器（下部）中的卡纸 ........................................................................................ 16 自动双面输稿器（上部）中的卡纸 ........................................................................................ 17 纸盒供纸区域中的卡纸 ........................................................................................................ 18 大容量供纸器中的卡纸 ........................................................................................................ 19 供纸工作台中的卡纸 ............................................................................................................ 19 第一纸盒中的卡纸................................................................................................................ 20 第二到第四纸盒中的卡纸 ..................................................................................................... 20 大容量供纸器纸盒中的卡纸 ................................................................................................. 21 旁路供纸托盘中的卡纸 ........................................................................................................ 22 自动双面单元中的卡纸 ........................................................................................................ 23 纸张输送通路中的卡纸 ........................................................................................................ 24 定影单元中的卡纸................................................................................................................ 25 作业分类托盘和交错分页托盘中的卡纸 ............................................................................... 27 中继桥单元中的卡纸 ............................................................................................................ 28 内置式整理器和打孔单元中的卡纸....................................................................................... 28 脊缝式装订整理器和打孔单元中的卡纸 ............................................................................... 31 脊缝式装订整理器的脊缝式装订单元中的卡纸..................................................................... 33 清除由错误的纸张尺寸设置引起的卡纸 ............................................................................... 34
OX2150A-LX中文资料
OCXO SERIES 5100"FEATURESMiniature OCXO in modified CO-15 packageLow current cnsumptionFrequencies up to 155.520 MHz"ELECTRICAL PERFORMANCEPARAMETER OCXO SERIES 5000AT CUT CRYSTAL SC CUT CRYSTAL Supply voltage, nom. 5V ±5% (3.3V Optional)Power dissipation steady state 1.5 Watt Max.Heat up power 3 Watt MaxHeat up time. 3 min MaxFrequency range 1 To 155.520 MHz StandardFrequency Adjustment ±10PPM Min (0 to 5V) ±0.7PPM Min (0 to 5V)±0.05 PPM ±0.1 PPM±0.25 PPM ±0.01 PPM ±0.02 PPM ±0.03 PPMFreq. stability vs. temperatureLX: 0°C to 60°CFZ: -30°C to 70°CD3: -40°C to 85°(Standard, contact factory for different temp ranges and stabilities) Freq. stability vs. supplychanges±0.015 PPM Max for ±5% Change ±0.010 PPM Max for ±5% Change Freq. stability vs. load changes ±0.01 PPM Max for ±5% Change ±0.005 PPM Max for ±5% ChangeLong term stability (Aging) ±4 PPM Max for 10 Years±0.005 PPM/Day Max. ±1 PPM Max for 10 Years ±0.002 PPM/Day Max.Output HCMOS/TTL/Sine 0 to +7dBm (Low voltage CMOS Available)Harmonics -30dBc(SineOutput) Spurious -75dBc(SineOutput) Duty cycle 40/60% to 60/40%(HCMOS)Rise / fall time 10nS Max. (HCMOS,10%~90%Vout, 90%~10%Vout)Short term Stability 1 E-10 /Sec 5 E-11 /SecPhase Noise Offset Phase Noise10Hz -90 dBc/Hz100Hz -125 dBc/Hz1000Hz -135 dBc/Hz10000Hz -150 dBc/Hz Offset Phase Noise 10Hz -110 dBc/Hz 100Hz -125 dBc/Hz 1000Hz -140 dBc/Hz 10000Hz -150 dBc/Hz" HOW TO ORDER (PART NUMBER)Prefix Output Type Cut Type Series Revision Temperature Range Stability Frequency OX2:HCMOS 4:LVCMOS 6:SINE0:AT (No Vcontrol ) 1: SC (No Vcontrol ) 4: AT (Elect Vcontrol) 5: SC (Elect Vcontrol)50:5000AFirst letter Lowest Temperature,Second letter Highest Temperature:From A=-55°C to Z=+70°C, Then: 1=+75°C, 2=+80°C, 3=+85°C… in 5°C steps Example: LZ: +0°C to +70°C LX: +0°C to +60°C FZ: -30°C to +70°C D3: -40°C to +85°CValue x 10E-2 in PPMExample 28= 0.28PP M 10= 0.1PPMIn MHZ。
2-PXA255开发系统
和工业控制计算机相比，嵌入式微处理器具有体积小、重量轻 、成本低、可靠性高的优点。目前主要的嵌入式处理器类型有 Am186/88、386EX、SC-400、Power PC、68000、MIPS、ARM/ StrongARM系列等
（4）嵌入式片上系统(System On Chip)
• • • • SoC 就是System on Chip ，SoC嵌入式系统微处理器就是一种 电路系统。 一般说来, SoC称为系统级芯片,也有称片上系统,意指它是一个产 品,是一个有专用目标的集成电路,其中包含完整系统并有嵌入软 件的全部内容。 国内外学术界一般倾向将SoC定义为将微处理器、模拟IP核、数 字IP核和存储器(或片外存储控制接口)集成在单一芯片上,它通常 是客户定制的,或是面向特定用途的标准产品。 它结合了许多功能区块，将功能做在一个芯片上，像是ARM RISC、MIPS RISC、DSP或是其他的微处理器核心，加上通信 的接口单元，像是万用串行端口（USB）、TCP/IP通信单元、 GPRS通信接口、GSM通信接口、IEEE1394、蓝牙模块接口等 等，这些单元以往都是依照各单元的功能做成一个个独立的处理 芯片。
高 速 缓 存 控 制 器
数据
CACHE 主存
CPU
地址 数据
系统连接的枢纽：总线和总线桥
CPU 低速设备
高速总线
桥
低速总线
存储器
高速设备
数据
高速设备
存储器系统
RAM：随机存取存储器（Random Access Memory ）
SRAM：静态随机存储器（static RAM）
DRAM：动态随机存储器(Dynamic RAM) ROM：只读存储器(Read Only Memory )
NPort W2150A W2250A 系列无线串行设备服务器说明文档说明书
NPort W2150A/W2250A系列1和2埠RS-232/422/485IEEE802.11a/b/g無線串列設備伺服器特色與優點•可將任何串列裝置連接至IEEE802.11a/b/g網路•透過內建乙太網路或WLAN執行Web-based設定•強化的區域網路、串列和電力突波保護•利用HTTPS和SSH強化遠端設定•透過WEP、WPA和WPA2保護存取資料的安全性•快速漫遊，可在存取點之間快速自動切換•具備離線埠緩衝和串列資料記錄功能•雙電源輸入(1螺旋式電源接頭、1端子台)認證簡介NPort®W2150A和W2250A是將串列和乙太網路裝置（例如PLC、儀表和感測器）連接到無線LAN的理想選擇。
您的通訊軟體將能夠透過無線LAN隨處存取串列裝置。
此外，無線裝置伺服器需要較少纜線，相當適合不便佈線的應用。
在基礎架構模式或Ad-Hoc模式中，NPort®W2150A和NPort®W2250A可以連接辦公室和工廠的Wi-Fi網路，以便使用者在多個AP（存取點）之間移動或漫遊，並且對於經常在不同的地點之間移動的裝置提供絕佳的解決方案。
規格Ethernet Interface10/100BaseT(X)Ports(RJ45connector)1Magnetic Isolation Protection 1.5kV(built-in)Standards IEEE802.3for10BaseTIEEE802.3u for100BaseT(X)Ethernet Software FeaturesConfiguration Options Web Console(HTTP/HTTPS),Windows UtilityManagement DHCP Option82,HTTP,IPv4,SMTP,SNMPv1/v2c/v3,Syslog,Telnet,Web Console Windows Real COM Drivers Windows95/98/ME/NT/2000,Windows XP/2003/Vista/2008/7/8/8.1/10(x86/x64),Windows2008R2/2012/2012R2/2016/2019(x64),Windows Embedded CE5.0/6.0,Windows XP EmbeddedLinux Real TTY Drivers Kernel versions:2.4.x,2.6.x,3.x,4.x,and5.xFixed TTY Drivers SCO UNIX,SCO OpenServer,UnixWare7,QNX4.25,QNX6,Solaris10,FreeBSD,AIX5.x,HP-UX11i,Mac OS XAndroid API Android3.1.x and laterMIB Device Settings MIB,RFC1213,RFC1317Security HTTPS/SSL,User Authentication Management:local database,RADIUS,SecureProtocols:HTTPS(TLSv1.2),SSH,SNMPv3,Cryptography:HMAC,SHA-1,SHA-256,SHA-384,RSA-1024,AES-128,AES-256Time Management NTP Client,SNTP ClientWLAN InterfaceWLAN Standards802.11a/b/g/nReceiver Sensitivity for802.11a(measured at5.680 GHz)Typ.-91@6Mbps Typ.-74@54MbpsReceiver Sensitivity for802.11b(measured at2.437 GHz)Typ.-92dBm@1Mbps Typ.-84dBm@11MbpsReceiver Sensitivity for802.11g(measured at2.437 GHz)Typ.-91dBm@6Mbps Typ.-73dBm@54MbpsReceiver Sensitivity for802.11n(2.4GHz;measured at2.437GHz)Typ.-89dBm@6.5Mbps(20MHz) Typ.-71dBm@72.2Mbps(20MHz)Receiver Sensitivity for802.11n(5GHz;measured at 5.680GHz)Typ.-89dBm@6.5Mbps(20MHz) Typ.-71dBm@72.2Mbps(20MHz) Typ.-85dBm@13.5Mbps(40MHz) Typ.-67dBm@150Mbps(40MHz)Modulation Type DSSSOFDMTransmission Distance Up to100meters(in open areas) Transmission Rate802.11a/g:54Mbps802.11b:11Mbps802.11n:6.5to150Mbps Transmitter Power for802.11b16±1.5dBm@1Mbps16±1.5dBm@11Mbps Transmitter Power for802.11g16±1.5dBm@6Mbps14±1.5dBm@54Mbps Transmitter Power for802.11a15±1.5dBm@6Mbps14±1.5dBm@54Mbps Transmitter Power for802.11n(2.4GHz)16dBm@1.5Mbps(6.5MHz)12dBm@1.5Mbps(72.2MHz) Transmitter Power for802.11n(5GHz)15dBm@1.5Mbps(6.5MHz)12dBm@1.5Mbps(150MHz) Frequency Band for CN(20MHz operating channels) 2.412to2.472GHz(13channels)5.180to5.240GHz(4channels)5.260to5.320GHz(4channels)15.745to5.825GHz(5channels) Frequency Band for EU(20MHz operating channels) 2.412to2.472GHz(13channels)5.180to5.240GHz(4channels)5.260to5.320GHz(4channels)15.500to5.700GHz(11channels)1 Frequency Band for JP(20MHz operating channels) 2.412to2.484GHz(14channels)5.180to5.240GHz(4channels)5.260to5.320GHz(4channels)15.500to5.700GHz(11channels)1 Frequency Band for US(20MHz operating channels) 2.412to2.462GHz(11channels)5.180to5.240GHz(4channels)5.260to5.320GHz(4channels)25.500to5.700GHz(11channels)25.745to5.825GHz(5channels)Wireless Security WEP encryption(64-bit and128-bit)WPA/WPA2-Enterprise(IEEE802.1X/RADIUS,TKIP,AES)WPA/WPA2-PersonalWLAN Modes Ad-hoc Mode,Infrastructure modeSerial InterfaceConnector DB9maleNo.of Ports NPort W2150A/W2150A-T:1NPort W2250A/W2250A-T:2Serial Standards RS-232,RS-422,RS-485Operation Modes Real COM mode,TCP Server mode,TCP Client mode,UDP mode,RFC2217mode,PairConnection mode,Ethernet Modem mode,DisabledBaudrate50bps to921.6kbpsData Bits5,6,7,8Stop Bits1,1.5,2Parity None,Even,Odd,Space,MarkFlow Control None,RTS/CTS,XON/XOFFRS-485Data Direction Control ADDC®(automatic data direction control)Pull High/Low Resistor for RS-4851kilo-ohm,150kilo-ohmsTerminator for RS-485120ohmsSurge1kVPhysical CharacteristicsHousing MetalInstallation Desktop,DIN-rail mounting(with optional kit),Wall mountingDimensions(with ears,without antenna)77x111x26mm(3.03x4.37x1.02in)Dimensions(without ears or antenna)100x111x26mm(3.94x4.37x1.02in)Weight NPort W2150A/W2150A-T:547g(1.21lb)NPort W2250A/W2250A-T:557g(1.23lb)Antenna Length109.79mm(4.32in)Environmental LimitsOperating Temperature Standard Models:0to55°C(32to131°F)Wide Temp.Models:-40to75°C(-40to167°F)Storage Temperature(package included)-40to75°C(-40to167°F)Ambient Relative Humidity5to95%(non-condensing)Power ParametersInput Current NPort W2150A/W2150A-T:179mA@12VDCNPort W2250A/W2250A-T:200mA@12VDCInput Voltage12to48VDCStandards and CertificationsEMC EN55032/24EMI CISPR32,FCC Part15B Class AEMS IEC61000-4-2ESD:Contact:4kV;Air:8kVIEC61000-4-3RS:80MHz to1GHz:3V/mIEC61000-4-4EFT:Power:2kV;Signal:2kVIEC61000-4-5Surge:Power:2kV;Signal:1kVIEC61000-4-6CS:150kHz to80MHz:3V/m;Signal:3V/mIEC61000-4-8PFMFIEC61000-4-11Radio Frequency CE(ETSI EN301893,ETSI EN300328,ETSI EN301489-17,ETSI EN301489-1),ARIBRCR STD-33,ARIB STD-66ReliabilityAlert Tools RTC(real-time clock)Automatic Reboot Trigger Built-in WDTMTBFTime NPort W2150A/W2150A-T:383,187hrsNPort W2250A/W2250A-T:363,327hrsStandards Telcordia(Bellcore)Standard TR/SRWarrantyWarranty Period5yearsDetails See /tw/warrantyPackage ContentsDevice1x NPort W2150A/W2250A Series device serverPower Supply1x power adapter,suitable for your region(standard temp.models only)Antenna1x2.4/5GHz antennaDocumentation1x quick installation guide1x warranty card尺寸訂購資訊Model Name No.of serial portsWLAN Channels Input Current Operating Temp.Power Adapter inBox Notes NPort W2150A-CN 1China bands 179mA @12VDC 0to 55°C Yes (CN plug)—NPort W2150A-EU 1Europe bands 179mA @12VDC 0to 55°C Yes (EU/UK/AUplug)—NPort W2150A-EU/KC 1Europe bands 179mA @12VDC 0to 55°C Yes (EU plug)KC certificateNPort W2150A-JP 1Japan bands 179mA @12VDC 0to 55°C Yes (JP plug)—NPort W2150A-US 1US bands 179mA @12VDC 0to 55°C Yes (US plug)—NPort W2150A-T-CN 1China bands 179mA @12VDC -40to 75°C No —NPort W2150A-T-EU 1Europe bands 179mA @12VDC -40to 75°C No —NPort W2150A-T-JP 1Japan bands 179mA @12VDC -40to 75°C No —NPort W2150A-T-US 1US bands 179mA @12VDC -40to 75°C No —NPort W2250A-CN 2China bands 200mA @12VDC 0to 55°C Yes (CN plug)—NPort W2250A-EU 2Europe bands 200mA @12VDC 0to 55°C Yes (EU/UK/AUplug)—NPort W2250A-EU/KC 2Europe bands 200mA @12VDC 0to 55°C Yes (EU plug)KC certificateNPort W2250A-JP 2Japan bands 200mA @12VDC 0to 55°C Yes (JP plug)—NPort W2250A-US 2US bands 200mA @12VDC 0to 55°C Yes (US plug)—NPort W2250A-T-CN 2China bands 200mA @12VDC -40to 75°C No —NPort W2250A-T-EU 2Europe bands 200mA @12VDC -40to 75°C No —NPort W2250A-T-JP 2Japan bands 200mA @12VDC -40to 75°C No —NPort W2250A-T-US2US bands200mA @12VDC-40to 75°CNo—配件（選購）AntennasANT-WDB-ARM-02 2.4/5GHz,omni-directional rubber duck antenna,2dBi,RP-SMA(male)CablesCBL-F9M9-150DB9female to DB9male serial cable,1.5mCBL-F9M9-20DB9female to DB9male serial cable,20cmConnectorsADP-RJ458P-DB9F DB9female to RJ45connectorMini DB9F-to-TB DB9female to terminal block connectorDIN-Rail Mounting KitsDK35A DIN-rail mounting kit,35mmPower AdaptersPWR-12050-WPAU-S1Locking barrel plug,12VDC,0.5A,100-240VAC,Australia(AU)plug,0to40°C operating temperature PWR-12050-WPCN-S1Locking barrel plug,12VDC,0.5A,100to240VAC,China(CN)plug,0to40°C operating temperature PWR-12050-WPEU-S1Locking barrel plug,12VDC,0.5A,100-240VAC,Continental Europe(EU)plug,0to40°C operatingtemperaturePWR-12050-WPUK-S1Locking barrel plug,12VDC,0.5A,100-240VAC,United Kingdom(UK)plug,0to40°C operatingtemperaturePWR-12050-WPUSJP-S1Locking barrel plug,12VDC,0.5A,100-240VAC,United States/Japan(US/JP)plug,0to40°C operatingtemperaturePWR-12150-AU-SA-T Locking barrel plug,12VDC,1.5A,100-240VAC,Australia(AU)plug,-40to75°C operating temperatureApplicable Models:NPort W2150A-TNPort W2250A-TPWR-12150-CN-SA-T Wide-temperature(-40to75°C)locking barrel plug,12VDC,1.5A,100to240VAC,China(CN)plugApplicable Models:NPort W2150A-TNPort W2250A-TPWR-12150-EU-SA-T Locking barrel plug,12VDC,1.5A,100-240VAC,Continental Europe(EU)plug,-40to75°C operatingtemperatureApplicable Models:NPort W2150A-TNPort W2250A-TPWR-12150-UK-SA-T Locking barrel plug,12VDC,1.5A,100-240VAC,United Kingdom(UK)plug,-40to75°C operatingtemperatureApplicable Models:NPort W2150A-TNPort W2250A-TPWR-12150-USJP-SA-T Locking barrel plug,12VDC1.5A,100-240VAC,United States/Japan(US/JP)plug,-40to75°Coperating temperatureApplicable Models:NPort W2150A-TNPort W2250A-TPower CordsCBL-PJ21NOPEN-BK-30Locking barrel plug to bare-wire cable©Moxa Inc.版權所有.2021年1月25日更新。
25AA256_07中文资料
• Block Write Protection:
- Protect none, 1/4, 1/2 or all of array
• Built-In Write Protection:
- Power-on/off data protection circuitry
- Write enable latch
-0.3
— 0.3 VCC V
-0.3
— 0.2 VCC V
D004 VOL D005 VOL
Low-level output voltage
—
—
0.4
V
—
—
0.2
V
D006 VOH
High-level output
VCC -0.5 —
—
V
voltage
D007 ILI
Input leakage current —
VCC = 5.5V; FCLK = 10.0 MHz; SO = Open VCC = 2.5V; FCLK = 5.0 MHz; SO = Open VCC = 5.5V VCC = 2.5V CS = VCC = 5.5V, Inputs tied to VCC or VSS, 125°C CS = VCC = 5.5V, Inputs tied to VCC or VSS, 85°C
DS21822F-page 2
© 2007 Microchip Technology Inc.
元器件交易网
25AA256/25LC256
TABLE 1-2: AC CHARACTERISTICS
AC CHARACTERISTICS
Industrial (I): TA = -40°C to +85°C Automotive (E): TA = -40°C to +125°C
OXuPCI954_DS
External—Free ReleaseOxford Semiconductor, Inc.1900 McCarthy Boulevard, Suite 210 © Oxford Semiconductor, Inc. 2007F EATURES• Four 16C950 High performance UART channels • 8-bit Pass-through Local Bus (PCI Bridge )• IEEE1284 Compliant SPP/EPP/ECP parallel port (with external transceiver)• Efficient 32-bit, 33 MHz, multi-function target-only PCIcontroller, fully compliant to PCI Local Bus Specification 3.0 and PCI Power Management Specification 1.1 • Software compatible with OXmPCI954• UARTs fully software compatible with 16C550-type devices • UART operation up to 60 MHz via external clock source. Up to 20 MHz with the crystal oscillator• Baud rates up to 60 Mbps in external 1x clock mode and 15 Mbps in asynchronous mode• 128-byte deep FIFO per transmitter and receiver • Flexible clock prescaler, from 1 to 31.875• Automated in-band flow control using programmable Xon/Xoff in both directions•Automated out-of-band flow control using CTS#/RTS# and/or DSR#/DTR#• Programmable RS485 turnaround delay• Arbitrary trigger levels for receiver and transmitter FIFO interrupts and automatic in-band and out-of-band flow control• Infra-red (IrDA) receiver and transmitter operation • 9-bit data framing, as well as 5, 6, 7, and 8 bits • Detection of bad data in the receiver FIFO• Global Interrupt Status and readable FIFO levels to facilitate implementation of efficient device drivers.• Local registers to provide status/control of device functions • 11 multi-purpose I/O pins, which can be configured as input interrupt pins or ‘wake-up’• Auto-detection of a wide range of optional MICROWIRE TM compatible EEPROMs, to re-configure device parameters • Function access , to pre-configure each function prior to handover to generic device drivers • Operation via I/O or memory mapping• 3.3 V or 5 V operation (PCI Universal Voltage)• Extended operating temperature range: -40° C to 85° C •176-pin LQFP packageD ESCRIPTIONThe OXuPCI954 is a single chip solution for PCI-based serial and parallel expansion add-in cards. It is a dual function PCI device, where function 0 offers four ultra-high performance OX16C950 UARTs, and function 1 is configurable either as an 8-bit local bus or a bi-directional parallel port.Each UART channel in the OXuPCI954 is the fastest available PC-compatible UART, offering data rates up to 15 Mbps and 128-byte deep transmitter and receiver FIFOs. The deep FIFOs reduce CPU overhead and allow utilization of higher data rates. Each UART channel is software compatible with the widely used industry-standard 16C550 devices (and compatibles), as well as the OX16C95x family of high performance UARTs. In addition to increased performance and FIFO size, the UARTs also provide the full set of OX16C95x enhanced features including automated in-band flow control, readable FIFO levels, etc.To enhance device driver efficiency and reduce interrupt latency, internal UARTs have multi-port features such as shadowed FIFO fill levels, a global interrupt source register and Good-Data Status, readable in four adjacent DWORD registers visible to logical functions in I/O space and memory space.Expansion of serial ports beyond four channels is possible using the 8-bit pass-through Local Bus function. This provides a general address/data bus and interrupt capability to a discrete UART part, such as the Oxford SemiconductorOX16C954. Other controllers could be used to provide capabilities beyond additional UART ports. The addressable space provided by the Local Bus can be increased up to 256 bytes, and divided into four chip-select regions. This flexible expansion scheme caters for cards with up to 20 serial ports using external 16C950, 16C954 or compatible devices, or composite applications such as combined serial and parallel port expansion cards. Serial port cards with up to 20 ports (or with 4 serial ports and a parallel port) can be designed without redefining any device or timing parameters.The parallel port is an IEEE 1284 compliant SPP/EPP/ECP parallel port that fully supports the existing Centronics interface. The parallel port can be enabled in place of the local bus. A n external bus transceiver is required for 5V parallel port operation if device is 3.3V sourced.For full flexibility, all the default configuration register values can be overwritten using an optional M ICROWIRE compatibleserial EEPROM. This EEPROM can also be used to provide function access to pre-configure devices on the local bus/parallel port, prior to any PCI configuration accesses and before control is handed to (generic) device drivers.The OXuPCI954 can be used to replace the OXmPCI954 in a PCI application where quad UARTs and a local bus/parallel port functionality are required.OXuPCI954 DATA SHEETIntegrated High Performance Quad UARTs,8-bit Local Bus/Parallel Port,3.3 V and 5 V (Universal Voltage) PCI Interface .Improvements of the OXuPCI954 over Discrete SolutionsHigher degree of integrationThe OXuPCI954 device offers four internal 16C950 high-performance UARTs and an 8-bit local bus or abi-directional parallel port.Multi-function deviceThe OXuPCI954 is a multi-function device to enable users to load individual device drivers for the internal serial ports, drivers for the peripheral devices connected to the local bus or drivers for the internal parallel port.Quad Internal OX16C950 UARTsThe OXuPCI954 device contains four ultra-high performance UARTs, which can increase driver efficiency by using features such as the 128-byte deep transmitter and receiver FIFOs, flexible clock options, automatic flow control, programmable interrupt and flow control trigger levels and readable FIFO levels. Data rates are up to 60 Mbps.Improved access timingAccess to the internal UARTs require zero or one PCI wait state. A PCI read transaction from an internal UART can complete within five PCI clock cycles and a write transaction to an internal UART can complete within four PCI clock cycles. Reduces interrupt latencyThe OXuPCI954 device offers shadowed FIFO levels and Interrupt status registers on the internal UARTs and the MIO pins. This reduces the device driver interrupt latency. Power managementThe OXuPCI954 device complies with the PCI Power Management Specification 1.1 and the Microsoft Communications Device-class Power Management Specification 2.0 (2000). Both functions offer the extended capabilities for Power Management. This achieves significant power savings by enabling device drivers to power down the PCI functions. For function 0, this is through switching off the channel clock, in power state D3. Wake-up (PME# generation) can be requested by either functions. For function 0, this is via the RI# inputs of the UARTs in the power-state D3 or any modem line and SIN inputs of the UARTs in power-state D2. For function 1, this is via the MIO[2] input.Optional EEPROMThe OXuPCI954 device can be reconfigured from an external EEPROM to the end-user’s requirements. However, this is not required in many applications as the default values are sufficient for typical applications. An overrun detection mechanism built into the EEPROM controller prevents the PCI system from ‘hanging’ due to an incorrectly programmed EEPROM.R EVISION H ISTORYRevision Modification May 2007 First publication.Sep 2007 Feature revision, including removal of D3coldT ABLE OF C ONTENTS1OXuPCI954 Device Modes (6)2Block Diagram (7)3Pin Information—176-Pin LQFP (8)3.1Mode ‘0’ Quad UARTs + 8-bit Local Bus (8)3.1.1Mode ‘1’ : Quad UARTs + Parallel Port (9)3.2Pin Descriptions (10)4Configuration and Operation (16)5PCI Target Controller (17)5.1Operation (17)5.2Configuration Space (17)5.2.1PCI Configuration Space Register Map (18)5.3Accessing Logical Functions (20)5.3.1PCI Access to Internal UARTs (21)5.3.2PCI Access to 8-bit Local Bus (22)5.3.3PCI Access to Parallel Port (22)5.4Accessing Local Configuration Registers (23)5.4.1Local Configuration and Control Register ‘LCC’ (Offset 0x00) (23)5.4.2Multi-purpose I/O Configuration Register ‘MIC’ (Offset 0x04) (24)5.4.3Local Bus Timing Parameter Register 1 ‘LT1’ (Offset 0x08) (26)5.4.4Local Bus Timing Parameter Register 2 ‘LT2’ (Offset 0x0C) (27)5.4.5UART Receiver FIFO Levels ‘URL’ (Offset 0x10) (28)5.4.6UART Transmitter FIFO Levels ‘UTL’ (Offset 0x14) (29)5.4.7UART Interrupt Source Register ‘UIS’ (Offset 0x18) (29)5.4.8Global Interrupt Status and Control Register ‘GIS’ (Offset 0x1C) (30)5.5PCI Interrupts (31)5.6Power Management (32)5.6.1Power Management of Function 0 (32)5.6.2Power Management of Function 1 (33)5.6.3Universal Voltage (34)5.7Unique Bar Option – for Function 0 (35)6Internal OX16C950 UARTs (36)6.1Operation – Mode Selection (36)6.1.1450 Mode (36)6.1.2550 Mode (36)6.1.3Extended 550 Mode (36)6.1.4750 Mode (36)6.1.5650 Mode (36)6.1.6950 Mode (37)6.2Register Description Tables (38)6.3UART Reset Configuration (41)6.3.1Hardware Reset (41)6.3.2Software Reset (41)6.4Transmitter and Receiver FIFOs (42)6.4.1FIFO Control Register ‘FCR’ (42)6.5Line Control and Status (43)6.5.1False Start Bit Detection (43)6.5.2Line Control Register ‘LCR’ (43)6.5.3Line Status Register ‘LSR’ (44)6.6Interrupts and Sleep Mode (45)6.6.1Interrupt Enable Register ‘IER’ (45)6.6.2Interrupt Status Register ‘ISR’ (46)6.6.3Interrupt Description (46)6.6.4Sleep Mode (47)6.7Modem Interface (47)6.7.1Modem Control Register ‘MCR’ (47)6.7.2Modem Status Register ‘MSR’ (48)6.8Other Standard Registers (48)6.8.1Divisor Latch Registers ‘DLL and DLM’ (48)6.8.2Scratch Pad Register ‘SPR’ (48)6.9Automatic Flow Control (49)6.9.1Enhanced Features Register ‘EFR’ (49)6.9.2Special Character Detection (50)6.9.3Automatic In-band Flow Control (50)6.9.4Automatic Out-of-band Flow Control (50)6.10Baud Rate Generation (51)6.10.1General Operation (51)6.10.2Clock Prescaler Register ‘CPR’ (51)6.10.3Times Clock Register ‘TCR’ (51)6.10.4External 1x Clock Mode (53)6.10.5Crystal Oscillator Circuit (53)6.11Additional Features (54)6.11.1Additional Status Register ‘ASR’ (54)6.11.2FIFO Fill Levels ‘TFL and RFL’ (54)6.11.3Additional Control Register ‘ACR’ (54)6.11.4Transmitter Trigger Level ‘TTL’ (55)6.11.5Receiver Interrupt. Trigger Level ‘RTL’ (55)6.11.6Flow Control Levels ‘FCL’ and ‘FCH’ (56)6.11.7Device Identification Registers (56)6.11.8Clock Select Register ‘CKS’ (56)6.11.9Nine-bit Mode Register ‘NMR’ (57)6.11.10Modem Disable Mask ‘MDM’ (57)6.11.11Readable FCR ‘RFC’ (58)6.11.12Good-data Status Register ‘GDS’ (58)6.11.13Port Index Register ‘PIX’ (58)6.11.14Clock Alteration Register ‘CKA’ (58)6.11.15RS485 Delay Enable ‘RS485_DLYEN’ (58)6.11.16RS485 Delay Count ‘RS485_DLYCNT’ (59)7Local bus (60)7.1Overview (60)7.2Operation (60)7.3Configuration and Programming (61)8Bidirectional Parallel Port (62)8.1Operation and Mode Selection (62)8.1.1SPP Mode (62)8.1.2PS2 Mode (62)8.1.3EPP Mode (62)8.1.4ECP Mode (62)8.2Parallel Port Interrupt (63)8.3Register Description (63)8.3.1Parallel Port Data Register ‘PDR’ (64)8.3.2ECP FIFO Address / RLE (64)8.3.3Device Status Register ‘DSR’ (64)8.3.4Device Control Register ‘DCR’ (64)8.3.5EPP Address register ‘EPPA’ (65)8.3.6EPP Data Registers ‘EPPD1-4’ (65)8.3.7ECP Data FIFO (65)8.3.8Test FIFO (65)8.3.9Configuration A Register (65)8.3.10Configuration B Register (65)8.3.11Extended Control Register ‘ECR’ (65)9Serial EEPROM (66)9.1Specification (66)9.1.1Zone 0: Header (67)9.1.2Zone 1: Local Configuration Registers (68)9.1.3Zone 2: Identification Registers (69)9.1.4Zone 3: PCI Configuration Registers (69)9.1.5Zone 4: Power Management DATA (and DATA_SCALE Zone) (70)9.1.6Zone 5: Function Access (70)10Operating Conditions (72)10.1DC Electrical Characteristics (72)11AC Electrical Characteristics (76)11.1PCI Bus Timings (76)11.2Local Bus (77)11.3Serial Ports (79)12Timing Waveforms (80)13Package Information (95)13.1176-Pin LQFP (95)14Ordering Information (96)1OX U PCI954D EVICE M ODESThe OXuPCI954 supports two modes of operation. These modes are summarized in the following table.Device Mode Mode Pin Selection Functionality0 MODE = 0 Function 0 : Quad UARTs Function 1 : 8-bit local bus1 MODE = 1 Function 0 : Quad UARTs Function 1 : Parallel Port* The OXuPCI954 is not pin-compatible with the OX16PCI954 or the OXmPCI954, but is the same in all other aspects.2B LOCK D IAGRAMFIFOSELMODEAD[31:0]C/BE[3:0]#PCI_CLKFRAME#DEVSEL#IRDY#TRDY#STOP#PARPERR#IDSELRST#INTA#PME#XTLIXTLOUART_Clk_Out Local_Bus ClkEE_DIEE_CSEE_CKEE_DOSOUT[3:0]SIN[3:0]RTS[3:0]DTR[3:0]CTS[3:0]DSR[3:0]DCD[3:0]RI[3:0]MIO[10:0]PD[7:0]ACK#PEBUSYSLCTERR#SLIN#INIT#AFD#STB#LBA[7:0]LBD[7:0]LBCS[3:0]LBWR#LBRD#LBRSTDATA_DIR OXuPCI954 Block DiagramOSCDIS XTLSEL3P IN I NFORMATION—176-P IN LQFP 3.1Mode ‘0’ Quad UARTs + 8-bit Local Bus7 NC. Do not connect these pins:23, 40, 41, 136, 137, 138, 1393.1.1Mode ‘1’ : Quad UARTs + Parallel Port15 NC. Do not connect these pins:23, 40, 41, 74, 112, 113, 114, 115, 116, 117, 124, 136, 137, 138, 1393.2Pin DescriptionsFor the actual pinouts of the OXuPCI954 device (for the various modes), refer to the Section 3, Pin Information. The I/O direction key table is on page 15.PCI Interface – All ModesPin Dir1Name Description149, 150, 151, 154, 155,157, 158, 160, 164, 165,167, 168, 169, 170, 171,174, 13, 14, 15, 17, 18, 20,24, 25, 27, 28, 31, 32, 33,34, 35, 39P_I/O AD[31:0] Multiplexed PCI Address/Data bus161, 175, 12, 26 P_I C/BE[3:0]# PCI Command/Byte enable146 P_I CLK PCI system clock (33MHz)176 P_IFRAME#CycleFrame5 P_ODEVSEL#DeviceSelect1 P_IIRDY#Initiatorready2 P_OTRDY#Targetready6 P_O STOP# Target Stop request10 P_I/OPAR Parity8 P_OSERR#Systemerror7 P_I/OPERR#Parityerror163 P_I IDSEL Initialization device select144 P_I RST# PCI system reset142 P_ODINTA# PCIinterrupt147 P_OD PME# Power management eventSerial Port Pins – All ModesPin Dir1Name Description50 I FIFOSEL FIFO select. For backward compatibility with 16C550,16C650 and 16C750 devices the UARTs’ FIFO depth is 16when FIFOSEL is low. The FIFO size is increased to 128when FIFOSEL is high. The unlatched state of this pin isreadable by software. The FIFO size may also be set to 128by setting FCR[5] when LCR[7] is set, or by putting thedevice into Enhanced mode.82, 81, 63, 62 O(h)SOUT[3:0]IrDA_Out[3:0] These four pins are present in all modes but they can serve one of two functions, as follows:UART serial data outputs.UART IrDA data output when MCR[6] of the corresponding channel is set in Enhanced mode.91, 73, 72, 55I(h) I(h) SIN[3:0]IrDA_In[3:0]These four pins are present in all modes but they can serveone of two functions, as follows:UART serial data inputs.UART IrDA data input when IrDA mode is enabled (seeabove).Serial Port Pins – All ModesPin Dir1Name Description89, 76, 71, 57 I(h) DCD[3:0]# Active-low modem data-carrier-detect input 84, 79, 65, 60O(h) O(h) O(h) DTR[3:0]#485_En[3:0]Tx_Clk_Out[3:0]These four pins are present in all modes but they can serveone of three functions, as follows:Active-low modem data-terminal-ready output. If automatedDTR# flow control is enabled, the DTR# pin is asserted anddeasserted if the receiver FIFO reaches or falls below theprogrammed thresholds, respectively.In RS485 half-duplex mode, the DTR# pin may beprogrammed to reflect the state of the transmitter empty bitto automatically control the direction of the RS485transceiver buffer (see register ACR[4:3]).Transmitter 1x clock (baud rate generator output). Forisochronous applications, the 1x (or Nx) transmitter clockmay be asserted on the DTR# pins (see register CKS[5:4]).83, 80, 64, 61 O(h) RTS[3:0]# Active-low modem request-to-send output. If automatedRTS# flow control is enabled, the RTS# pin is deassertedand reasserted whenever the receiver FIFO reaches or fallsbelow the programmed thresholds, respectively.85, 78, 67, 59 I(h) CTS[3:0]# Active-low modem clear-to-send input. If automated CTS#flow control is enabled, upon deassertion of the CTS# pin,the transmitter will complete the current character and enterthe idle mode until the CTS# pin is reasserted. Note: any in-band flow control characters are transmitted regardless ofthe state of the CTS# pin.86, 77, 66, 58I(h) I(h) DSR[3:0]#Rx_Clk_In[3:0]These four pins are present in all modes but they can serveone of two functions, as follows:Active-low modem data-set-ready input. If automated DSR#flow control is enabled, upon deassertion of the DSR# pin,the transmitter will complete the current character and enterthe idle mode until the DSR# pin is reasserted. Note: any in-band flow control characters are transmitted regardless ofthe state of the DSR# pin.External receiver clock for isochronous applications. TheRx_Clk_In is selected when CKS[1:0] = ‘01’.90, 75, 70, 56 I(h)I(h) RI[3:0]#Tx_Clk_In[3:0]Active-low modem Ring-Indicator inputExternal transmitter clock. This clock can be used by thetransmitter (and indirectly by the receiver) when CKS[6]=’1’.Clock Interface Pins – All ModesPin Dir 1 Name Description49 I/OXTLOCrystal oscillator output when OSCDIS = ‘0’.External clock source input when OSCDIS = ‘1’48 I XTLI Crystal oscillator input when OSCDIS = ‘0’, up to 20MHz.N/C when OSCDIS = ‘1’45 I OSCDIS Oscillator disable.When 0, the internal crystal oscillator is enabled and a crystal needs to be attached to XTLI/XTLO.XTLSEL must be set according to the crystal frequency that is used (up to 20Mhz).When 1, the internal crystal oscillator is disabled and an external oscillator source (up to 60MHz) can be input to XTLO. XTLI is N/C and XTLSEL must be 0130 I XTLSEL Defines the frequency of the crystal attached to XTLI/XTLO(when OSCDIS = ‘0’)0 = 1 MHz – 12 MHz 1 = 12 MHz – 20 MHz8-bit Local Bus – Mode 0Pin Dir 1 Name Description 111O UART_CLK_Out Buffered crystal output. This clock can drive external UARTsconnected to the local bus. Can be enabled / disabled by software.123 O(h) LBRST Local bus active-high reset. 124 O LBRST# Local bus active-low reset. 104 O LBDOUT Local bus data out enable. This pin can be used by externaltransceivers; it is high when LBD[7:0] are in output mode and low when they are in input mode.74 O LBCLK Buffered PCI clock. Can be enabled / disabled by software. 114, 115, 116, 117 O(h) O(h) LBCS[3:0]# LBDS[3:0]# Local bus active-low Chip-Select (Intel mode).Local bus active-low Data-Strobe (Motorola mode).112 O O LBWR# LBRDWR# Local bus active-low write-strobe (Intel mode).Local bus Read-not-Write control (Motorola mode).113 O Z LBRD# Hi-Z Local bus active-low read-strobe (Intel mode).Permanent high impedance (Motorola mode).105, 106, 108, 109 118, 119, 120, 122 O(h) LBA[7:0] Local bus address signals. 96, 97, 98, 99 100, 101, 102, 103I/O(h) LBD[7:0] Local bus data signals.Parallel Port – Mode 1Pin Dir 1 NameDescription123 I(h) I(h) ACK#INTR#Acknowledge (SPP mode). ACK# is asserted (low) by the peripheral to indicate that a successful data transfer has taken place.Identical function to ACK# (EPP mode).122 I(h) PEPaper Empty. Activated by printer when it runs out of paper. 120 I(h) I(h) BUSYWAIT#Busy (SPP mode). BUSY is asserted (high) by the peripheral when it is not ready to accept data.Wait (EPP mode). Handshake signal for interlocked IEEE 1284 compliant EPP cycles.109 OD(h) O(h) SLIN#ADDRSTB#Select (SPP mode). Asserted by host to select the peripheral.Address strobe (EPP mode) provides address read and write strobe.119 I(h) SLCT Peripheral selected. Asserted by peripheral when selected. 118 I(h) ERR#Error. Held low by the peripheral during an error condition. 108 OD(h) O(h) INIT#INIT#Initialize (SPP mode). Commands the peripheral to initialize.Initialize (EPP mode). Identical function to SPP mode. 106 OD(h) O(h) AFD#DATASTB# Auto Feed (SPP mode, open-drain).Data strobe (EPP mode) provides data read and write strobe.105 OD(h) O(h) STB#WRITE#Strobe (SPP mode). Used by peripheral to latch data currently available on PD[7:0].Write (EPP mode). Indicates a write cycle when low and a read cycle when high . 96, 97, 98, 99, 100, 101, 102, 103I/O(h) PD[7:0] Parallel data bus.104OPDOUTParallel port data out enable. This pin should be used by external transceivers for 5 V signaling; it is high when PD[7:0] are in output mode and low when they are in input mode.Multi-purpose and External Interrupt Pins – All ModesPin Dir1Name DescriptionMODE0 1135 --135I/O(h)OMIO0NCMulti-purpose I/O 0. Can drive high or low, or assert a PCIinterrupt.Output Driving ‘0’. Can be left as a No-connect.134 134 134134I/O(h)MIO1NCMulti-purpose I/O 1. Can drive high or low, or assert a PCIinterrupt (as long as LCC[6:5] = “00”).Output Driving ‘0’ (when LCC[6:5] ≠ ‘00’)Can be left as a No-Connect.133 133 133133I/O(h)IMIO2PME_InMulti-purpose I/O 2. When LCC[7] = 0, this pin can drive highor low, or assert a PCI interrupt.Input power management event. When LCC[7] is set thisinput pin can assert a function 1 PME#.93, 94, 95, 125, 126, 127, 128, 132 I/O(h) MIO[10:3] Multi-purpose I/O pins. Can drive high or low, or assert a PCIinterrupt.EEPROM Pins – All ModesPin Dir1Name Description53 OEE_CKEEPROMclock.52 O EE_CS EEPROM active-high Chip Select.54 IU(h) EE_DI EEPROM data in, with internal pull-up.When the serial EEPROM is connected, this pin should bepulled up using a 1-10k resistor. When the EEPROM is notused the internal pull-up is sufficient.Pin to be connected to the external EEPROM’s EE_DO pin(if used).51 O EE_DO EEPROM data out.Pin to be connected to the external EEPROM’s EE_DI pin(if used).Table 1: Pin DescriptionsI/O Direction Key P_I PCI input 3.3 V Only P_O PCI output / PCITristates 3.3 V Only P_I/O PCI bi-directional 3.3 V Only P_OD PCI open drain 3.3 V OnlyI Input LVTTL level I(h) Input LVTTL level, 5 V tolerant IU(h) Input with internal pull-up LVTTL level, 5 V tolerant I/O(h) Bi-Directional LVTTL level, 5 V tolerantO Output Standard Output O(h) Output 5 V tolerant (High Voltage BI-Direct in output mode) OD Open drain Standard Open-drain Output OD(h) Open drain 5 V tolerant (High Voltage BI-Direct in open-drain mode) NC No connectG Ground V VoltageMiscellaneous PinsPin Dir 1 NameDescription44 IMODEMode selector Pin0 : Function 0 : Quad UART. Function 1 : 8-bit local bus.1 : Function 0 : Quad UART. Function 1 : Parallel port.Power and GroundPinType Name Description19, 42, 47, 69, 88, 107, 131, 148VVDDPower Supply (3.3 V)11, 22, 36, 140, 156, 162, 173 V VIOPCI I/O Universal VoltageDefines the (clamping) voltage of the PCI I/O Buffers.To be connected to the VIO pin of the PCI connector. 3, 4, 9, 16, 21, 29, 30, 37, 38, 43, 46, 68, 87, 92, 110, 121, 129, 141, 143, 145, 152, 153, 159, 166, 172G GNDPower Supply Ground (0 V)4C ONFIGURATION AND O PERATIONThe OXuPCI954 is a multi-function, target-only PCI device, compliant with the PCI Local Bus Specification, Revision 3.0 and the PCI Power Management Specification, Revision 1.1.The OXuPCI954 affords maximum configuration flexibility by treating the internal UARTs, the local bus and the parallel port as separate logical functions. Each function has its own configuration space and is therefore recognized and configured by the PCI BIOS separately. The functions used are configured by the Mode Selection Pin as shown in Section 1 OXuPCI954 Device Modes.The OXuPCI954 is configured by system start-up software during the bootstrap process that follows bus reset. The system scans the bus and reads the vendor and device identification codes from any devices it finds. It then loads device-driver software according to this information and configures the I/O, memory and interrupt resources. Device drivers can then access the functions at the assigned addresses in the usual fashion, with the improved data throughput provided by PCI.Each function operates as though it was a separate device. However there are a set of Local Configuration Registers that can be used to enable signals and interrupts, configure timings, and improve the efficiency of multi-port drivers. This architecture enables separate drivers to be installed for each function. Generic port drivers can be hooked to use the functions individually, or more efficient multi-port drivers can hook both functions, accessing the Local Configuration Registers from either.All registers default after reset to suitable values for typical applications such a 4/8 port serial, or combo 4-port serial/1-port parallel add-in cards. However, all identification, control and timing registers can be redefined using an optional serial EEPROM.5PCI T ARGET C ONTROLLER5.1OperationThe OXuPCI954 responds to the following PCI transactions:-•Configuration access: The OXuPCI954 responds to type 0 configuration reads and writes if the IDSELsignal is asserted and the bus address is selecting theconfiguration registers for function 0 or 1. The devicewill respond to the configuration transaction by asserting DEVSEL#. Data transfer then follows. Anyother configuration transaction will be ignored by theOXuPCI954.•I/O reads/writes: The address is compared with the addresses reserved in the I/O Base Address Registers(BARs). If the address falls within one of the assignedranges, the device will respond to the I/O transactionby asserting DEVSEL#. Data transfer follows thisaddress phase. For the UARTs and 8-bit local buscontroller, only byte accesses are possible. For I/Oaccesses to these regions, the controller comparesAD[1:0] with the byte-enable signals as defined in thePCI specification. The access is always completed;however if the correct BE signal is not present thetransaction will have no effect.•Memory reads/writes: These are treated in the same way as I/O transactions, except that the memoryranges are used. Memory access to single-byte regions is always expanded to DWORDs in theOXuPCI954. In other words, OXuPCI954 reserves aDWORD per byte in single-byte regions. The deviceallows the user to define the active byte lane usingLCC[4:3] so that in Big-Endian systems the hardwarecan swap the byte lane automatically. For Memorymapped access in single-byte regions, the OXuPCI954 compares the asserted byte-enable withthe selected byte-lane in LCC[4:3] and completes theoperation if a match occurs, otherwise the access willcomplete normally on the PCI bus, but it will have noeffect on either the internal UARTs or the local buscontroller.•All other cycles (64-bit, special cycles, reserved encoding etc.) are ignored.The OXuPCI954 will complete all transactions as disconnect-with-data, i.e. the device will assert the STOP# signal alongside TRDY#, to ensure that the Bus Master does not continue with a burst access. The exception to this is Retry, which will be signaled in response to any access while the OXuPCI954 is reading from the serial EEPROM.The OXuPCI954 performs medium-speed address decoding as defined by the PCI specification. It asserts the DEVSEL# bus signal two clocks after FRAME# is first sampled low on all bus transaction frames which address the chip. The internal UARTs are accessed with zero wait states inserted. Fast back-to-back transactions are supported by the OXuPCI954 as a target, so a bus master can perform faster sequences of write transactions to the UARTs or local bus when an inter-frame turn-around cycle is not required.The device supports any combination of byte-enables to the PCI Configuration Registers and the Local Configuration Registers. If a byte-enable is not asserted, that byte is unaffected by a write operation and undefined data is returned upon a read.The OXuPCI954 performs parity generation and checking on all PCI bus transactions as defined by the standard. Note this is entirely unrelated to serial data parity which is handled within the UART functional modules themselves. If a parity error occurs during the PCI bus address phase, the device will report the error in the standard way by asserting the SERR# bus signal. However if that address/command combination is decoded as a valid access, it will still complete the transaction as though the parity check was correct.The OXuPCI954 does not support any kind of caching or data buffering in addition to that already provided within the UARTs by the transmit and receive data FIFOs. In general, registers in the UARTs and on the local bus can not be pre-fetched because there may be side-effects on read.5.2Configuration SpaceThe OXuPCI954 is a dual-function device, where each logical function has its own configuration space. All required fields in the standard header are implemented, plus the Power Management Extended Capability register set. The format of the configuration space is shown in the following tables.In general, writes to any registers that are not implemented are ignored, and all reads from unimplemented registers return 0.。
PRIMERGY BX2560 M1 系统配置器和订单信息指南说明书
PRIMERGY BX2560 M1System configurator and order-information guide ContentsInstructionsConfiguration diagramConfigurator10X BX2560 M1 Dual Socket11XI Processor12XII Storage13XIII Memory14XIV iRMC S4, Graphics15XV Mezzanine Cards16PRIMERGY ServerSystem configurator and order-information guidePRIMERGY BX2560 M1 Status: 2016-04-01 InstructionsThis document contains basic product and configuration information that will enable you to configure your system viaSystem-Architect.Only the tool "System-Arcitect" will ensure a fast and proper configuration of your PRIMERGY server or your complete PRIMERGY Rack system.Please pay attention to the naming conventions: BX2560 M1Dual Server Blade M1You can configure your individual PRIMERGY server in order to adjust your specific requirements.The System configurator is divided into several chapters that are identical to the current price list and PC-/ System-Architect. Please follow the lines. If there is a junction, you can choose which way or component you would like to take. Go throughthe configurator by following the lines from the top to the bottom.In one chapter you can only select as many components (here 3x) as the arrow indicates.3xPlease note that there are information symbols which indicate necessary information.For further information see:/products/standard_servers/index.html(internet)https:///com/order-supply/configurators/primergy_config/Pages/Currentconfigurators.aspx(extranet)Prices and availability see price list and PC-/ System-ArchitectSubject to change and errors exceptedSystem configurator and order-information guidePRIMERGY BX2560 M1 Status: 2016-04-01Configuration diagram Dual Server Blade BX2560 M1Key:Included in basic unit OptionThe population order for the DIMMs: for each CPU, the DIMM row 1 (DIMMS 1A 1B 1C 1D) (DIMMS1E 1F 1G 1H) first,then row 2 (DIMMs 2A 2B 2C 2D) (DIMMs 2E 2F 2G 2H)Section XII Storage / RAID Functionality on Server BladeOne UFM can be installed independent from the disk drivesRemark: UFM is part of the VMWare Embedded solution (26361-F2341-E433)Configuration Hint - Second CPU needed for PCIe x4 Gen3 SSD/HDD OptionThe PCIe HDD/SSD Option is only supported if the second CPU is installedPlease refer the following configuration matrix for your desired confuration.S26361-F3823-E410S26361-F3823-E400S26361-F4008-E100S26361-F4008-E101PRAID EM400i PRAID CM400i PCH connection Kit PCIe x4 Gen3PY SAS 12G RAID HDD Module PY SAS 12G RAID HDD Module supports up to 2 HDD/SSDw/ 1 GB Cache w/o Cache connected to onboard PCHMegaRAID MegaRAIDRAID level 0/1/1E/10/5/50/6/60RAID level 0/1/10Hint: 2nd CPU is mandatorySAS 12 Gb/sec SAS 12 Gb/sec for this Optionincl. PRAID EM400i Riser incl. PRAID EM400i Riser for this Optionpluggable on the main board pluggable on the main boardPCIe Gen3 interface PCIe Gen3 interface SATA interface PCIe x4 Gen3 interface4x SAS links to midplane2x SAS links to internal HDD's2x PCIe x4 Gen3 links2x SAS links to internal HDD's2x SATA links to int. HDD's to internal HDD'smax. 1x per Server Blade max. 1x per Server Blade max. 1x per Server Blade max. 1x per Server BladeS26361-F3823-E10PRAID EM400i FBUPY FBU03 ModuleFlash Backup Unitincl. FBU holder SATA HDD / SSD PCIe-SSD / HDDS26361-F3823-E30PRAID EM400i MezzPY SAS Expander Mezzanine Cardconnection to SAS CBincl. SAS cableS26361-F3823-E20S26361-F3823-E20PRAID EM400i BP PRAID EM400i BPPY SAS 12G HDD Backplane PY SAS 12G HDD Backplane2 internal SAS links 2 internal SAS linksto PY SAS 12G RAID HDD Modul to PY SAS 12G RAID HDD ModulGSystem configurator and order-information guide PRIMERGY BX2560 M1 Status: 2016-04-01Memory Configuration PRIMERGY BX2560 M1Each CPU offers 8 Slots for DDR4 Memory Modules organised in 2 Banks and 4 Channels.If you need more than 8 Slots you have to configure the 2nd CPU.Depending on the amount of memory configured you can decide between 4 basic modes of operation (see explanation below).There are 2 different kinds of DDR4 Memory Modules available: RDIMM and LRDIMM Mix of RDIMM and LRDIMM is not allowed.ModeConfigurationApplication SDDC (chipkill) support any no yes detect multi-bit errors Independant Channel Mode 1, 2 or 3 Modules per Bank yes yes offers max. flexibility, upgradeability, capacity Mirrored Channel Mode *) 4 identical Modules / Bank noyes offers maximum security Performance Mode 4 identical Modules / Bank yes yes offers maximum performance and capacity Rank Sparing Mode *)min. 2 Ranks / Channel no yes balances security and capacity *) For the delivery ex works the system will be prepared with dedicated BIOS setting.CapacityConfiguration RDIMM LRDIMM NotesMin. Memory per CPU 1 Module / CPU with one CPU Max. Memory per CPU 8/12 Modules / CPU with one CPUMax. Memory per System16/24 Modules / System512GB 1024GBif second CPU is configuredMemory-Speed:Max. DDR4 memory speed depends on the memory configuration on one memory channel and the speed of the CPU The memory channel with the lowest speed defines the speed of all CPU channels in the system1R - Single Rank4R - Quad Rank 2R - Dual Rank 8R - Eight Rank1DPC = 1 DIMM per Channel 2DPC = 2 DIMM per Channel Configuration hints:- The memory sockets on the systemboard offer a color coding:Bank I black sockets Bank II blue sockets- A so called Bank consits of 1 memory module on every Channel available on one CPU (examples see below)Bank I on CPU 1/2up to 4 memory modules connected to Channel A - H on the 1st/2nd CPU Bank II on CPU 1/2up to 4 memory modules connected to Channel A - E on the 1st/2nd CPU - See below and next page for a detailed descriptions of the memory configuration supported.1x32GB 8x32GB 8x64GB RDIMMRDIMM LRDIMM x8x41x8GBrequiredrequired if 2nd CPU is configured Bank Ioptional, same type in Bank per CPU Bank IIoptional, any type--------not usedIndependent Channel Mode allows all channels to be populated in any orderCan run with differently rated DIMMs and use the settings of the slowest DIMM installed in the system2. Mirrored Channel Moderequiredrequired if 2nd CPU is configuredBank I optional, same type in Bank per CPUBank II Mirrored Channel Mode requires identical modules on channel A,B, C, D (1st CPU) or channel E, F, G and H (2nd CPU)50% of the capacity is used for the mirror => the available memory for applications is only half of the installed memory If this mode is used, a multiple of 4 identical modules has to be ordered.3. Performance Channel Moderequiredrequired if 2nd CPU is configured Bank I optional, same type in Bank per CPU Bank II optional, any typePerformance Channel Mode requires identical modules on all channels of each Bank per CPU.If this mode is used, a multiple of 4 identical modules has to be ordered.C h a n n e l AC h a n n e l BC h a n n e l CC h a n n e l DC h a n n e l EC h a n n e l FC h a n n e l EC h a n n e l Fh a n n e l HC h a n n e l AC h a n n e l BC h a n n e l CC h a n n e l Dh a n n e l Eh a n n e l FC h a n n e l GC h a n n e l HC h a n n e l GC h a n n e l Ha n n e l Aa n n e l Ba n n e l Ca n n e l Dh a n n e l Grequiredrequired if 2nd CPU is configured Bank Ioptional, same type in Channel per CPU Bank IIoptional, any typeBank Irequired(black)required if 2nd CPU is configured Bank II (blue)optional, same type in Channel per CPU optional, any typeBank I required(black)required if 2nd CPU is configured optional, same type in Channel per CPUBank II (blue)optional, any typeRank Sparing Mode requires identical modules (same capacity and technology) within the same channel.The available memory for applications will vary depending on configuration. Please refer to the spreadsheet above "Effective Memory capacity with active Rank Sparing Mode". Population rule for Rank sparing mode is to achieve max.available memory, e.g. 8 DIMMs will be spread across two channels, each with 4DPCC h a n n e l GC h a n n e l H4-Rank Memory modules (LRDIMM)C h a n n e l AC h a n n e l BC h a n n e l CC h a n n e l FC h a n n e l GC h a n n e l HC h a n n e l FC h a n n e l GC h a n n e l HC h a n n e l AC h a n n e l BC h a n n e l CC h a n n e l FC h a n n e l EC h a n n e l D2-Rank Memory modules (RDIMM)C h a n n e l AC h a n n e l BC h a n n e l CC h a n n e l DC h a n n e l EC h a n n e l EC h a n n e l D1-Rank Memory modules (RDIMM)System configurator and order-information guidePRIMERGY BX2560 M1 Status: 2016-04-01 Change Report。
IBM ThinkPad各种错误代码
IBM ThinkPad各种错误代码-深度解析在大家平时工作,生活中使用IBM 的笔记本电脑经常会出现各种各样的故障提示代码,有的时候其实只是小问题,只要知道代码其所代表的含意,解决问题就是件非常轻松的事情了.0175：Bad CRC1, stop POST task（CRC1 错误,停止POST 任务）0176：System Security - The system has been tampered with.（系统安全性- 系统受到了干扰.）0177：Bad SVP data, stop POST task.（SVP 数据错误,停止POST 任务.）0182：Bad CRC2.Enter BIOS Setup and load Setup defaults.（CRC2 错误.请进入BIOS Setup 并装入Setup 缺省值.）0185：Bad startup sequence settings. Enter BIOS Setup and load Setup defaults.（启动顺序设置错误.请进入BIOS Setup 并装入Setup 缺省值.）0187：EAIA data access error（EAIA 数据访问错误）0188：Invalid RFID Serialization Information Area.（无效的RFID 序列化信息区域.）0189：Invalid RFID configuration information area（无效的RFID 配置信息区域）0190：Critical low-battery error（电池电量严重不足错误）0191：Sytem Security - Invalid remote change requested.（系统安全性- 请求了无效的远程更改.）0192：System Security - IBM Embedded Security hardware tamper detected.（系统安全性- 检测到IBM Embedded Security 硬件干扰.）0199：System Security - IBM Security password retry count exceeded.（系统安全性- 超出IBM 安全性密码重试次数.）01C8：More than one modem devices are found. Remove one of them. Press to continue.（找到多个调制解调器设备.请卸下其中之一.按键继续.）01C9：More than one Ethernet devices are found. Remove one of them. Press to continue.（找到多个以太网设备.请卸下其中之一.按键继续.）0200：Hard disk error（硬盘错误）021x：Keyboard error（键盘错误）0230：Shadow RAM error（影子RAM 错误）0231：System RAM error（系统RAM 错误）0232：Extended RAM error（扩展RAM 错误）0250：System battery error（系统电池错误）0251：System CMOS checksum bad（系统CMOS 校验和错误）0260：System timer error（系统定时器错误）0270：Real time clock error（实时时钟错误）0271：Date and time error（日期和时间错误）0280：Previous boot incomplete（先前的引导未完成）02D0：System cache error（系统高速缓存错误）02F4：EISA CMOS not writable（EISA CMOS 不可写）02F5：DMA test failed（DMA 测试失败）02F6：Software NMI failed（软件NMI 失败）02F7：Fail-safe timer NMI failed（故障安全定时器NMI 失败）1802：Unauthorized network card is plugged in - Power off and remove the miniPCI network card.（插入了未授权的网卡- 关闭电源,然后卸下小型P 网卡）.1803：Unauthorized daughter card is plugged in - Power off and remove the daughter card.（插入了未授权的子卡－关闭电源,然后卸下子卡.）1810：Hard disk partition layout error（硬盘分区布局错误）The power-on password prompt（出现开机密码提示）The hard disk password prompt（出现硬盘密码提示）Hibernation error（休眠错误）Operating system not found.（未找到操作系统.）Fan error（风扇错误）EMM386 Not Installed--Unable to Set Page Frame Base Address.（未安装EMM386 - 无法设置页帧基地址.）CardBus Configuration Error--Device Disabled.（CardBus 配置错误- 设备禁用.）Thermal sensing error（热检测错误）Authentication of system services failed. Press to resume.（系统服务认证失败.按恢复.）消息：0175：Bad CRC1, stop POST task（CRC1 错误,停止POST 任务）解决方案：EEPROM 校验和不正确（块#6）.将计算机送去维修.消息：0176：System Security - The System has been tampered with.（系统安全性- 系统受到了干扰.）解决方案：如果您卸下了安全芯片并将其重新安装,或安装了一个新的安全芯片,则显示此消息.要清除该错误,请进入BIOS Setup Utility.如果这样不能解决问题,请将计算机送去维修.消息：0177：Bad SVP data, stop POST task.（SVP 数据错误,停止POST 任务.）解决方案：EEPROM 中的超级用户密码的校验和不正确.应该更换系统板. 将计算机送去维修.消息：0182：Bad CRC2.Enter BIOS Setup and load Setup defaults.（CRC2 错误.进入BIOS Setup 并装入Setup 缺省值.）解决方案：EEPROM 中的CRC2 设置的校验和不正确.请转至BIOS Setup Utility.按F9,然后按Enter 键来装入缺省设置.按F10,然后按Enter 键来重新启动系统.消息：0185：Bad startup sequence settings.Enter BIOS Setup and load Setup defaults.（启动顺序设置错误.进入BIOS Setup 并装入Setup 缺省值.）解决方案：EEPROM 中的启动顺序设置不正确.请转至BIOS Setup Utility.按F9,然后按Enter 键来装入缺省设置.按F10,然后按Enter 键来重新启动系统.消息：0187：EAIA data access error（EAIA 数据访问错误）解决方案：访问EEPROM 失败.将计算机送去维修.消息：0188：Invalid RFID Serialization Information Area.（无效的RFID 序列化信息区域.）解决方案：EEPROM 校验和不正确（块# 0 和1）.应更换系统板,并且需要重新安装计算机序列号.将计算机送去维修.消息：0189：Invalid RFID configuration information area（无效的RFID 配置信息区域）解决方案：EEPROM 校验和不正确（块# 4 和5）.应该更换系统板,并且需要重新安装UUID.将计算机送去维修.消息：0190：Critical low-battery error（电池电量严重不足错误）解决方案：由于电池电量过低,计算机关闭.将交流电源适配器连接到计算机并给电池充电,也可用充足电的电池替换此电池.消息：0191：System Security - Invalid remote change requested.（系统安全性- 请求了无效的远程更改.）解决方案：系统配置更改出现故障.请确认此操作并重试.要清除该错误,请进入BIOS Setup Utility.消息：0192：System Security - IBM Embedded Security hardware tamper detected.（系统安全性- 检测到IBM Embedded Security 硬件干扰.）解决方案：用另一芯片更换了安全芯片.将计算机送去维修.消息：0199：System Security - IBM Security password retry count exceeded.（系统安全性- 超出IBM 安全性密码重试次数.）解决方案：如果您输入错误的超级用户密码超过三次,则显示此消息.请确认超级用户密码并重试.要清除该错误,请进入BIOS Setup Utility.消息：01C8：More than one modem devices are found. Remove one of them. Press to continue.（找到多个调制解调器设备.请卸下其中之一.按继续.）解决方案：卸下调制解调器小型PCI 卡.否则,按Esc 忽略警告消息.如果这样不能解决问题,请将计算机送去维修.消息：01C9：More than one Ethernet devices are found. Remove one of them. Press to continue.（找到多个以太网设备.请卸下其中之一.按继续.）解决方案：您的ThinkPad 计算机具有内置的以太网功能部件,您不能通过安装以太网设备来添加另外一个这样的功能部件.如果显示此错误消息,请卸下您安装的以太网设备.否则,按Esc 忽略警告消息.如果这样不能解决问题,请将计算机送去维修.消息：0200：Hard disk error（硬盘错误）解决方案：硬盘不工作.确保硬盘驱动器连接牢固.运行BIOS Setup Utility；然后确保未在Startup 菜单中禁用该硬盘驱动器.消息：021x：Keyboard error（键盘错误）解决方案：确保键盘或外接键盘（如果有）上没有放置任何物体.关闭计算机,然后关闭所有连接设备的电源.首先打开计算机,然后打开所有连接设备的电源.如果仍看到相同的错误代码,请执行以下操作：如果连接了外接键盘,请执行以下操作：关闭计算机,断开外接键盘的连接；然后打开计算机.确保内置键盘工作正常.如果内置键盘工作正常,请将外接键盘送去维修.确保外接键盘连接到了正确的接口.使用PC-Doctor 测试计算机.如果计算机在测试过程中停止,应将计算机送去维修.0210:F1<—>3A; F2<—>3C; F3<—>3D; F4<—>3E; F5<—>3F; F6<—>40; F7<—>41; F8<—>42; F9<—>43; F10<—>44; F11<—>45; F12<—>46; Q<—>10; W<—>11; E<—>12; R<—>13; T<—>14; Y<—>15; U<—>16; I<—>17; O<—>18; P<—>19; A<—>1E; S<—>1F; D<—>20; F<—>21; G<—>22; H<—>23; J<—>24; K<—>25; L：26; ;<—>27 ; <—>28; Z<—>2C; X<—>2D; C<—>2E; V<—>2F; B<—>30; N<—>31; M<—>32 <<—>33; ><—>34; ?<—>35; Space<—>39; Capslock<—>3A; Enter<—>1C; left shift<—>2A; left ctrl<—>1D; left alt<—>38Stuck key : 0C ——主板故障原文地址:/bbs/dispbbs.asp?boardid=36&Id=217消息：0230：Shadow RAM error（影子RAM 错误）解决方案：影子RAM 失败.使用PC-Doctor 测试计算机内存.如果恰好在打开计算机之前添加了内存条,请重新安装它.然后使用PC-Doctor 测试内存.消息：0231：System RAM error（系统RAM 错误）解决方案：系统RAM 失败.使用PC-Doctor 测试计算机内存.如果恰好在打开计算机之前添加了内存条,请重新安装它.然后使用PC-Doctor 测试内存.消息：0232：Extended RAM error（扩展RAM 错误）解决方案：扩展RAM 失败.使用PC-Doctor 测试计算机内存.如果恰好在打开计算机电源之前增加了内存,应重新安装它.然后使用PC-Doctor 测试内存.消息：0250：System battery error（系统电池错误）解决方案：当计算机关闭时用来保存配置信息（例如日期和时间）的备份电池被耗尽.更换电池,并运行BIOS Setup Utility 以验证配置.如果仍有问题,应将计算机送去维修.消息：0251：System CMOS checksum bad（系统CMOS 校验和错误）解决方案：系统CMOS 可能已被应用程序毁坏.计算机使用缺省设置.运行BIOS Setup Utility 以重新配置设置.如果仍看到相同的错误代码,应将计算机送去维修.消息：0260：System timer error（系统定时器错误）解决方案：将计算机送去维修.消息：0270：Real time clock error（实时时钟错误）解决方案：将计算机送去维修.消息：0271：Date and time error（日期和时间错误）解决方案：计算机中既没有设置日期也没有设置时间.使用BIOS Setup Utility 设置日期和时间.消息：0280：Previous boot incomplete（先前的引导未完成）解决方案：计算机先前无法完成引导过程.关闭计算机；然后再打开,以启动BIOS Setup Utility.验证配置,然后通过选择Restart 项下的Exit Saving Changes 选项或按F10 重新启动计算机.如果仍看到相同的错误代码,应将计算机送去维修.消息：02D0：System cache error（系统高速缓存错误）解决方案：高速缓存禁用.将计算机送去维修.消息：02F4：EISA CMOS not writable（EISA CMOS 不可写）解决方案：将计算机送去维修.消息：02F5：DMA test failed（DMA 测试失败）解决方案：将计算机送去维修.消息：02F6：Software NMI failed（软件NMI 失败）解决方案：将计算机送去维修.消息：02F7：Fail-safe timer NMI failed（故障安全定时器NMI 失败）解决方案：将计算机送去维修.消息：1802：Unauthorized network card is plugged in - Power off and remove the miniPCI network card.（插入了未经认证的网卡- 关闭电源,然后卸下小型PCI 网卡.）解决方案：此计算机上不支持小型PCI 网卡.请卸下它.消息：1803：Unauthorized daughter card is plugged in - Power off and remove the daughter card.（插入了未授权的子卡－关闭电源并卸下子卡.）解决方案：子卡在本计算机上不受支持.将其卸下.消息：1810：Hard disk partition layout error（硬盘分区布局错误）解决方案：在识别硬盘上分区布局的过程中出现的问题停止了计算机启动.IBM Predesktop Area 已经被删除或硬盘包含毁坏的数据.要尝试重新启动计算机,请完成以下操作之一：如果IBM Predesktop Area 已被删除按F1 打开IBM BIOS Setup Utility.选择Security --> IBM Predesktop Area --> Access IBM Predesktop Area.将该项设置为Disabled.保存并退出.如果以上操作失败按Enter 键.单击RECOVER TO FACTORY CONTENTS 并按照屏幕上的指示信息操作.注：这将永久擦除硬盘上的所有内容,然后恢复IBM 预安装的软件.按F1 打开IBM BIOS Setup Utility 或按Enter 键启动IBM Predesktop Area.如果计算机仍然无法启动,则请致电IBM HelpCenter(R).消息：The power-on password prompt（出现开机密码提示）解决方案：设置了开机密码或超级用户密码.输入密码并按Enter 键即可使用计算机（请参考使用密码）.如果不接受开机密码,可能是设置了超级用户密码.输入超级用户密码并按Enter 键.如果仍看到相同的错误消息,应将计算机送去维修.消息：The hard disk password prompt（出现硬盘密码提示）解决方案：设置了硬盘密码.输入密码并按Enter 键即可使用计算机（请参考硬盘密码）.如果仍看到相同的错误消息,应将计算机送去维修.消息：Hibernation error（休眠错误）解决方案：在计算机进入休眠方式和结束该方式之间的时间内,系统配置发生了变化,计算机无法恢复正常运行.将系统配置恢复到计算机进入休眠方式之前的状态.如果改变了内存大小,应重新创建休眠文件.消息：Operating system not found.（未找到操作系统.）解决方案：请验证以下内容：正确地安装了硬盘驱动器.软盘驱动器中有可启动软盘如果仍看见相同的错误消息,请使用BIOS Setup Utility 检查引导顺序.消息：Fan error（风扇错误）解决方案：散热风扇出现故障.将计算机送去维修.消息：EMM386 Not Installed--Unable to Set Page Frame Base Address.（未安装EMM386 - 无法设置页帧基地址）解决方案：编辑C:\CONFIG.SYS 并将此行device=C:\WINDOWS\EMM386.EXE RAM更改为device=C:\WINDOWS\EMM386.EXE NOEMS然后保存此文件.消息：CardBus Configuration Error--Device Disabled（CardBus 配置错误- 设备禁用）解决方案：转至IBM BIOS Setup Utility.按F9,然后按Enter 键装入缺省设置.按F10,然后按Enter 键重新启动系统.消息：Thermal sensing error（热检测错误）解决方案：热传感器未正确工作.将计算机送去维修.消息：Authentication of system services failed. Press to resume.（系统服务认证失败.按恢复.）解决方案：HDD 中的IBM Predesktop Area 毁坏.要使用IBM Predesktop Area,获取一张恢复CD,并使用它来恢复IBM Predesktop Area.。
ATMEGA2561V资料
Features•High Performance, Low Power AVR® 8-Bit Microcontroller •Advanced RISC Architecture–135 Powerful Instructions – Most Single Clock Cycle Execution –32 x 8 General Purpose Working Registers–Fully Static Operation–Up to 16 MIPS Throughput at 16 MHz–On-Chip 2-cycle Multiplier•Non-volatile Program and Data Memories–64K/128K/256K Bytes of In-System Self-Programmable FlashEndurance: 10,000 Write/Erase Cycles–Optional Boot Code Section with Independent Lock BitsIn-System Programming by On-chip Boot ProgramTrue Read-While-Write Operation–4K Bytes EEPROMEndurance: 100,000 Write/Erase Cycles–8K Bytes Internal SRAM–Up to 64K Bytes Optional External Memory Space–Programming Lock for Software Security•JTAG (IEEE std. 1149.1 compliant) Interface–Boundary-scan Capabilities According to the JTAG Standard–Extensive On-chip Debug Support–Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface •Peripheral Features–Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode–Four 16-bit Timer/Counter with Separate Prescaler, Compare- and Capture Mode –Real Time Counter with Separate Oscillator–Four 8-bit PWM Channels–Six/Twelve PWM Channels with Programmable Resolution from 2 to 16 Bits(ATmega1281/2561, ATmega640/1280/2560)–Output Compare Modulator–8/16-channel, 10-bit ADC (ATmega1281/2561, ATmega640/1280/2560)–Two/Four Programmable Serial USART (ATmega1281/2561,ATmega640/1280/2560)–Master/Slave SPI Serial Interface–Byte Oriented 2-wire Serial Interface–Programmable Watchdog Timer with Separate On-chip Oscillator–On-chip Analog Comparator–Interrupt and Wake-up on Pin Change•Special Microcontroller Features–Power-on Reset and Programmable Brown-out Detection–Internal Calibrated Oscillator–External and Internal Interrupt Sources–Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby, and Extended Standby•I/O and Packages–54/86 Programmable I/O Lines (ATmega1281/2561, ATmega640/1280/2560)–64-pad QFN/MLF, 64-lead TQFP (ATmega1281/2561)–100-lead TQFP, 100-ball CBGA (ATmega640/1280/2560)–RoHS/Fully Green•Temperature Range:–-40°C to 85°C Industrial•Ultra-Low Power Consumption–Active Mode: 1 MHz, 1.8V: 510 µA–Power-down Mode: 0.1 µA at 1.8V•Speed Grade (see “Maximum speed vs. VCC” on page 377):–ATmega640V/ATmega1280V/ATmega1281V:0 - 4 MHz @ 1.8 - 5.5V, 0 - 8 MHz @ 2.7 - 5.5V–ATmega2560V/ATmega2561V:0 - 2 MHz @ 1.8 - 5.5V, 0 - 8 MHz @ 2.7 - 5.5V–ATmega640/ATmega1280/ATmega1281:0 - 8 MHz @ 2.7 - 5.5V, 0 - 16 MHz @ 4.5 - 5.5V–ATmega2560/ATmega2561:0 - 16 MHz @ 4.5 - 5.5V 8-bit Microcontroller64K/128K/256K Bytes In-System ProgrammableATmega640/V ATmega1280/V ATmega1281/V2ATmega640/1280/1281/2560/25612549KS–AVR–01/07Pin ConfigurationsFigure 1. TQFP-pinout ATmega640/1280/25603ATmega640/1280/1281/2560/25612549KS–AVR–01/07Figure 2. CBGA-pinout ATmega640/1280/2560Table 1. CBGA-pinout ATmega640/1280/2560.12345678910A G N D AREF PF0PF2PF5PK0PK3PK6G N D VCC B AVCC PG5PF1PF3PF6PK1PK4PK7PA0PA2C PE2PE0PE1PF4PF7PK2PK5PJ7PA1PA3D PE3PE4PE5PE6PH2PA4PA5PA6PA7PG2E PE7PH0PH1PH3PH5PJ6PJ5PJ4PJ3PJ2F VCC PH4PH6PB0PL4PD1PJ1PJ0PC7G N D G G N D PB1PB2PB5PL2PD0PD5PC5PC6VCC H PB3PB4RESET PL1PL3PL7PD4PC4PC3PC2J PH7PG3PB6PL0XT AL2PL6PD3PC1PC0PG1KPB7PG4VCCG N DXT AL1PL5PD2PD6PD7PG04ATmega640/1280/1281/2560/25612549KS–AVR–01/07Figure 3. Pinout ATmega1281/2561N ote:The large center pad underneath the QF N /MLF package is made of metal and internally connected to G N D. It should be soldered or glued to the board to ensure good mechani-cal stability. If the center pad is left unconnected, the package might loosen from the board.DisclaimerTypical values contained in this datasheet are based on simulations and characteriza-tion of other AVR microcontrollers manufactured on the same process technology. Min.and Max values will be available after the device is characterized.5ATmega640/1280/1281/2560/25612549KS–AVR–01/07OverviewThe ATmega640/1280/1281/2560/2561 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega640/1280/1281/2560/2561 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.Block DiagramFigure 4. Block Diagram6ATmega640/1280/1281/2560/25612549KS–AVR–01/07The AVR core combines a rich instruction set with 32 general purpose working registers.All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.The ATmega640/1280/1281/2560/2561 provides the following features: 64K/128K/256K bytes of In-System Programmable Flash with Read-W hile-W rite capabilities, 4K bytes EEPROM, 8K bytes SRAM, 54/86 general purpose I/O lines, 32 general purpose work-ing registers, Real Time Counter (RTC), six flexible Timer/Counters with compare modes and P W M, 4 USARTs, a byte oriented 2-wire Serial Interface, a 16-channel, 10-bit ADC with optional differential input stage with programmable gain, programmable W atchdog Timer with Internal Oscillator, an SPI serial port, IEEE std. 1149.1 compliant JTAG test interface, also used for accessing the On-chip Debug system and program-ming and six software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscilla-tor, disabling all other chip functions until the next interrupt or Hardware Reset. In Power-save mode, the asynchronous timer continues to run, allowing the user to main-tain a timer base while the rest of the device is sleeping. The ADC N oise Reduction mode stops the CPU and all I/O modules except Asynchronous Timer and ADC, to min-imize switching noise during ADC conversions. In Standby mode, the Crystal/Resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low power consumption. In Extended Standby mode, both the main Oscillator and the Asynchronous Timer continue to run.The device is manufactured using Atmel’s high-density nonvolatile memory technology.The On-chip ISP Flash allows the program memory to be reprogrammed in-system through an SPI serial interface, by a conventional nonvolatile memory programmer, or by an On-chip Boot program running on the AVR core. The boot program can use any interface to download the application program in the application Flash memory. Soft-ware in the Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-W hile-W rite operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega640/1280/1281/2560/2561 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications.The ATmega640/1280/1281/2560/2561 AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits.7ATmega640/1280/1281/2560/25612549KS–AVR–01/07Comparison Between ATmega1281/2561 and ATmega640/1280/2560Each device in the ATmega640/1280/1281/2560/2561 family differs only in memory size and number of pins. Table 2 summarizes the different configurations for the six devices.Pin DescriptionsVCC Digital supply voltage.GNDGround.Port A (PA7..PA0)Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running.P o r t A a l s o s e r v e s t h e f u n c t i o n s o f v a r i o u s s p e c i a l f e a t u r e s o f t h e ATmega640/1280/1281/2560/2561 as listed on page 91.Port B (PB7..PB0)Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running.Port B has better driving capabilities than the other ports.P o r t B a l s o s e r v e s t h e f u n c t i o n s o f v a r i o u s s p e c i a l f e a t u r e s o f t h e ATmega640/1280/1281/2560/2561 as listed on page 92.Port C (PC7..PC0)Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running.P o r t C a l s o s e r v e s t h e f u n c t i o n s o f s p e c i a l f e a t u r e s o f t h e ATmega640/1280/1281/2560/2561 as listed on page 95.Port D (PD7..PD0)Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will sourceTable 2. Configuration SummaryDevice Flash EEPROM RAM GeneralPurpose I/O pins16 bits resolution PWM channelsSerial USARTsADC ChannelsA Tmega64064KB 4KB 8KB 8612416A Tmega1280128KB 4KB 8KB 8612416A Tmega1281128KB 4KB 8KB 54628A Tmega2560256KB 4KB 8KB 8612416A Tmega2561256KB4KB8KB546288ATmega640/1280/1281/2560/25612549KS–AVR–01/07current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running.P o r t D a l s o s e r v e s t h e f u n c t i o n s o f v a r i o u s s p e c i a l f e a t u r e s o f t h e ATmega640/1280/1281/2560/2561 as listed on page 97.Port E (PE7..PE0)Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port E output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up resistors are activated. The Port E pins are tri-stated when a reset condition becomes active, even if the clock is not running.P o r t E a l s o s e r v e s t h e f u n c t i o n s o f v a r i o u s s p e c i a l f e a t u r e s o f t h e ATmega640/1280/1281/2560/2561 as listed on page 99.Port F (PF7..PF0)Port F serves as analog inputs to the A/D Converter.Port F also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used.Port pins can provide internal pull-up resistors (selected for each bit). The Port F output buffers have symmetrical drive characteristics with both high sink and source capability.As inputs, Port F pins that are externally pulled low will source current if the pull-up resistors are activated. The Port F pins are tri-stated when a reset condition becomes active, even if the clock is not running. If the JTAG interface is enabled, the pull-up resis-tors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will be activated even if a reset occurs.Port F also serves the functions of the JTAG interface.Port G (PG5..PG0)Port G is a 6-bit I/O port with internal pull-up resistors (selected for each bit). The Port G output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port G pins that are externally pulled low will source current if the pull-up resistors are activated. The Port G pins are tri-stated when a reset condition becomes active, even if the clock is not running.P o r t G a l s o s e r v e s t h e f u n c t i o n s o f v a r i o u s s p e c i a l f e a t u r e s o f t h e ATmega640/1280/1281/2560/2561 as listed on page 105.Port H (PH7..PH0)Port H is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port H output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port H pins that are externally pulled low will source current if the pull-up resistors are activated. The Port H pins are tri-stated when a reset condition becomes active, even if the clock is not running.P o r t H a l s o s e r v e s t h e f u n c t i o n s o f v a r i o u s s p e c i a l f e a t u r e s o f t h e ATmega640/1280/2560 as listed on page 107.Port J (PJ7..PJ0)Port J is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port J output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port J pins that are externally pulled low will source current if the pull-up resistors are activated. The Port J pins are tri-stated when a reset condition becomes active, even if the clock is not running.P o r t J a l s o s e r v e s t h e f u n c t i o n s o f v a r i o u s s p e c i a l f e a t u r e s o f t h e ATmega640/1280/2560 as listed on page 109.Port K (PK7..PK0)Port K serves as analog inputs to the A/D Converter.9ATmega640/1280/1281/2560/25612549KS–AVR–01/07Port K is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port K output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port K pins that are externally pulled low will source current if the pull-up resistors are activated. The Port K pins are tri-stated when a reset condition becomes active, even if the clock is not running.P o r t K a l s o s e r v e s t h e f u n c t i o n s o f v a r i o u s s p e c i a l f e a t u r e s o f t h e ATmega640/1280/2560 as listed on page 111.Port L (PL7..PL0)Port L is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port L output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port L pins that are externally pulled low will source current if the pull-up resistors are activated. The Port L pins are tri-stated when a reset condition becomes active, even if the clock is not running.P o r t L a l s o s e r v e s t h e f u n c t i o n s o f v a r i o u s s p e c i a l f e a t u r e s o f t h e ATmega640/1280/2560 as listed on page 113.Reset input. A low level on this pin for longer than the minimum pulse length will gener-ate a reset, even if the clock is not running. The minimum pulse length is given in Table 26 on page 58. Shorter pulses are not guaranteed to generate a reset.XTAL1Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.XTAL2Output from the inverting Oscillator amplifier.AVCCAVCC is the supply voltage pin for Port F and the A/D Converter. It should be externally connected to V CC , even if the ADC is not used. If the ADC is used, it should be con-nected to V CC through a low-pass filter.AREFThis is the analog reference pin for the A/D Converter.ResourcesA comprehensive set of development tools and application notes, and datasheets are available for download on /avr.10ATmega640/1280/1281/2560/25612549KS–AVR–01/07Register SummaryAddressNameBit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0Page(0x1FF)Reserved --------...Reserved --------(0x13F)Reserved (0x13E)Reserved (0x13D)Reserved (0x13C)Reserved (0x13B)Reserved (0x13A)Reserved (0x139)Reserved (0x138)Reserved (0x137)Reserved (0x136)UDR3 USART3 I/O Data Registerpage 227(0x135)UBRR3H ----USART3 Baud Rate Register High Bytepage 231(0x134)UBRR3L USART3 Baud Rate Register Low Bytepage 231(0x133)Reserved --------(0x132)UCSR3C UMSEL31UMSEL30UPM31UPM30USBS3UCSZ31UCSZ30UCPOL3page 244(0x131)UCSR3B RXCIE3TXCIE3UDRIE3RXE N 3TXE N 3UCSZ32RXB83TXB83page 243(0x130)UCSR3A RXC3TXC3UDRE3FE3DOR3UPE3U2X3MPCM3page 242(0x12F)Reserved --------(0x12E)Reserved --------(0x12D)OCR5CH Timer/Counter5 - Output Compare Register C High Byte page 167(0x12C)OCR5CL Timer/Counter5 - Output Compare Register C Low Byte page 167(0x12B)OCR5BH Timer/Counter5 - Output Compare Register B High Byte page 167(0x12A)OCR5BL Timer/Counter5 - Output Compare Register B Low Byte page 167(0x129)OCR5AH Timer/Counter5 - Output Compare Register A High Byte page 167(0x128)OCR5AL Timer/Counter5 - Output Compare Register A Low Byte page 167(0x127)ICR5H Timer/Counter5 - Input Capture Register High Byte page 168(0x126)ICR5L Timer/Counter5 - Input Capture Register Low Byte page 168(0x125)TC N T5H Timer/Counter5 - Counter Register High Byte page 165(0x124)TC N T5L Timer/Counter5 - Counter Register Low Bytepage 165(0x123)Reserved --------(0x122)TCCR5C FOC5A FOC5B FOC5C-----page 164(0x121)TCCR5B IC N C5ICES5-W GM53W GM52CS52CS51CS50page 162(0x120)TCCR5A COM5A1COM5A0COM5B1COM5B0COM5C1COM5C0W GM51W GM50page 160(0x11F)Reserved --------(0x11E)Reserved --------(0x11D)Reserved --------(0x11C)Reserved --------(0x11B)Reserved --------(0x11A)Reserved --------(0x119)Reserved --------(0x118)Reserved --------(0x117)Reserved --------(0x116)Reserved --------(0x115)Reserved --------(0x114)Reserved --------(0x113)Reserved --------(0x112)Reserved --------(0x111)Reserved --------(0x110)Reserved --------(0x10F)Reserved --------(0x10E)Reserved --------(0x10D)Reserved --------(0x10C)Reserved --------(0x10B)PORTL PORTL7PORTL6PORTL5PORTL4PORTL3PORTL2PORTL1PORTL0page 118(0x10A)DDRL DDL7DDL6DDL5DDL4DDL3DDL2DDL1DDL0page 118(0x109)PI N L PI N L7PI N L6PI N L5PI N L4PI N L3PI N L2PI N L1PI N L0page 118(0x108)PORTK PORTK7PORTK6PORTK5PORTK4PORTK3PORTK2PORTK1PORTK0page 118(0x107)DDRK DDK7DDK6DDK5DDK4DDK3DDK2DDK1DDK0page 118(0x106)PI N K PI N K7PI N K6PI N K5PI N K4PI N K3PI N K2PI N K1PI N K0page 118(0x105)PORTJ PORTJ7PORTJ6PORTJ5PORTJ4PORTJ3PORTJ2PORTJ1PORTJ0page 118(0x104)DDRJ DDJ7DDJ6DDJ5DDJ4DDJ3DDJ2DDJ1DDJ0page 118(0x103)PI N J PI N J7PI N J6PI N J5PI N J4PI N J3PI N J2PI N J1PI N J0page 118(0x102)PORTHPORTH7PORTH6PORTH5PORTH4PORTH3PORTH2PORTH1PORTH0page 117ATmega640/1280/1281/2560/2561Address Name Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0Page(0x101)DDRH DDH7DDH6DDH5DDH4DDH3DDH2DDH1DDH0page 117(0x100)PI N H PI N H7PI N H6PI N H5PI N H4PI N H3PI N H2PI N H1PI N H0page 117 (0xFF)Reserved--------(0xFE)Reserved--------(0xFD)Reserved--------(0xFC)Reserved--------(0xFB)Reserved--------(0xFA)Reserved--------(0xF9)Reserved--------(0xF8)Reserved--------(0xF7)Reserved--------(0xF6)Reserved--------(0xF5)Reserved--------(0xF4)Reserved--------(0xF3)Reserved--------(0xF2)Reserved--------(0xF1)Reserved--------(0xF0)Reserved--------(0xEF)Reserved--------(0xEE)Reserved--------(0xED)Reserved--------(0xEC)Reserved--------(0xEB)Reserved-------(0xEA)Reserved--------(0xE9)Reserved--------(0xE8)Reserved--------(0xE7)Reserved-------(0xE6)Reserved--------(0xE5)Reserved--------(0xE4)Reserved--------(0xE3)Reserved-------(0xE2)Reserved--------(0xE1)Reserved-------(0xE0)Reserved-------(0xDF)Reserved--------(0xDE)Reserved--------(0xDD)Reserved-------(0xDC)Reserved--------(0xDB)Reserved--------(0xDA)Reserved--------(0xD9)Reserved-------(0xD8)Reserved--------(0xD7)Reserved--------(0xD6)UDR2 USART2 I/O Data Register page 227 (0xD5)UBRR2H----USART2 Baud Rate Register High Byte page 231 (0xD4)UBRR2L USART2 Baud Rate Register Low Byte page 231 (0xD3)Reserved--------(0xD2)UCSR2C UMSEL21UMSEL20UPM21UPM20USBS2UCSZ21UCSZ20UCPOL2page 244 (0xD1)UCSR2B RXCIE2TXCIE2UDRIE2RXE N2TXE N2UCSZ22RXB82TXB82page 243 (0xD0)UCSR2A RXC2TXC2UDRE2FE2DOR2UPE2U2X2MPCM2page 242 (0xCF)Reserved--------(0xCE)UDR1 USART1 I/O Data Register page 227 (0xCD)UBRR1H----USART1 Baud Rate Register High Byte page 231 (0xCC)UBRR1L USART1 Baud Rate Register Low Byte page 231 (0xCB)Reserved--------(0xCA)UCSR1C UMSEL11UMSEL10UPM11UPM10USBS1UCSZ11UCSZ10UCPOL1page 244 (0xC9)UCSR1B RXCIE1TXCIE1UDRIE1RXE N1TXE N1UCSZ12RXB81TXB81page 243 (0xC8)UCSR1A RXC1TXC1UDRE1FE1DOR1UPE1U2X1MPCM1page 242 (0xC7)Reserved--------(0xC6)UDR0 USART0 I/O Data Register page 227 (0xC5)UBRR0H----USART0 Baud Rate Register High Byte page 231 (0xC4)UBRR0L USART0 Baud Rate Register Low Byte page 231 (0xC3)Reserved--------(0xC2)UCSR0C UMSEL01UMSEL00UPM01UPM00USBS0UCSZ01UCSZ00UCPOL0page 244 (0xC1)UCSR0B RXCIE0TXCIE0UDRIE0RXE N0TXE N0UCSZ02RXB80TXB80page 243 (0xC0)UCSR0A RXC0TXC0UDRE0FE0DOR0UPE0U2X0MPCM0page 243Address Name Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0Page (0xBF)Reserved--------(0xBE)Reserved--------(0xBD)T W AMR T W AM6T W AM5T W AM4T W AM3T W AM2T W AM1T W AM0-page 274 (0xBC)T W CR T W I N T T W EA T W STA T W STO T WW C T W E N-T W IE page 271 (0xBB)T W DR 2-wire Serial Interface Data Register page 273 (0xBA)T W AR T W A6T W A5T W A4T W A3T W A2T W A1T W A0T W GCE page 273 (0xB9)T W SR T W S7T W S6T W S5T W S4T W S3-T W PS1T W PS0page 272 (0xB8)T W BR2-wire Serial Interface Bit Rate Register page 271 (0xB7)Reserved--------(0xB6)ASSR-EXCLK AS2TC N2UB OCR2AUB OCR2BUB TCR2AUB TCR2BUB page 188 (0xB5)Reserved--------(0xB4)OCR2B Timer/Counter2 Output Compare Register B page 195 (0xB3)OCR2A Timer/Counter2 Output Compare Register A page 195 (0xB2)TC N T2 Timer/Counter2 (8 Bit)page 195 (0xB1)TCCR2B FOC2A FOC2B--W GM22CS22CS21CS20page 194 (0xB0)TCCR2A COM2A1COM2A0COM2B1COM2B0--W GM21W GM20page 195 (0xAF)Reserved--------(0xAE)Reserved--------(0xAD)OCR4CH Timer/Counter4 - Output Compare Register C High Byte page 167 (0xAC)OCR4CL Timer/Counter4 - Output Compare Register C Low Byte page 167 (0xAB)OCR4BH Timer/Counter4 - Output Compare Register B High Byte page 166 (0xAA)OCR4BL Timer/Counter4 - Output Compare Register B Low Byte page 166 (0xA9)OCR4AH Timer/Counter4 - Output Compare Register A High Byte page 166 (0xA8)OCR4AL Timer/Counter4 - Output Compare Register A Low Byte page 166 (0xA7)ICR4H Timer/Counter4 - Input Capture Register High Byte page 168 (0xA6)ICR4L Timer/Counter4 - Input Capture Register Low Byte page 168 (0xA5)TC N T4H Timer/Counter4 - Counter Register High Byte page 165 (0xA4)TC N T4L Timer/Counter4 - Counter Register Low Byte page 165 (0xA3)Reserved--------(0xA2)TCCR4C FOC4A FOC4B FOC4C-----page 164 (0xA1)TCCR4B IC N C4ICES4-W GM43W GM42CS42CS41CS40page 162 (0xA0)TCCR4A COM4A1COM4A0COM4B1COM4B0COM4C1COM4C0W GM41W GM40page 160 (0x9F)Reserved--------(0x9E)Reserved--------(0x9D)OCR3CH Timer/Counter3 - Output Compare Register C High Byte page 166 (0x9C)OCR3CL Timer/Counter3 - Output Compare Register C Low Byte page 166 (0x9B)OCR3BH Timer/Counter3 - Output Compare Register B High Byte page 166 (0x9A)OCR3BL Timer/Counter3 - Output Compare Register B Low Byte page 166 (0x99)OCR3AH Timer/Counter3 - Output Compare Register A High Byte page 166 (0x98)OCR3AL Timer/Counter3 - Output Compare Register A Low Byte page 166 (0x97)ICR3H Timer/Counter3 - Input Capture Register High Byte page 168 (0x96)ICR3L Timer/Counter3 - Input Capture Register Low Byte page 168 (0x95)TC N T3H Timer/Counter3 - Counter Register High Byte page 165 (0x94)TC N T3L Timer/Counter3 - Counter Register Low Byte page 165 (0x93)Reserved--------(0x92)TCCR3C FOC3A FOC3B FOC3C-----page 164 (0x91)TCCR3B IC N C3ICES3-W GM33W GM32CS32CS31CS30page 162 (0x90)TCCR3A COM3A1COM3A0COM3B1COM3B0COM3C1COM3C0W GM31W GM30page 160 (0x8F)Reserved--------(0x8E)Reserved--------(0x8D)OCR1CH Timer/Counter1 - Output Compare Register C High Byte page 166 (0x8C)OCR1CL Timer/Counter1 - Output Compare Register C Low Byte page 166 (0x8B)OCR1BH Timer/Counter1 - Output Compare Register B High Byte page 166 (0x8A)OCR1BL Timer/Counter1 - Output Compare Register B Low Byte page 166 (0x89)OCR1AH Timer/Counter1 - Output Compare Register A High Byte page 166 (0x88)OCR1AL Timer/Counter1 - Output Compare Register A Low Byte page 166 (0x87)ICR1H Timer/Counter1 - Input Capture Register High Byte page 168 (0x86)ICR1L Timer/Counter1 - Input Capture Register Low Byte page 168 (0x85)TC N T1H Timer/Counter1 - Counter Register High Byte page 165 (0x84)TC N T1L Timer/Counter1 - Counter Register Low Byte page 165 (0x83)Reserved--------(0x82)TCCR1C FOC1A FOC1B FOC1C-----page 164 (0x81)TCCR1B IC N C1ICES1-W GM13W GM12CS12CS11CS10page 162 (0x80)TCCR1A COM1A1COM1A0COM1B1COM1B0COM1C1COM1C0W GM11W GM10page 160 (0x7F)DIDR1------AI N1D AI N0D page 278 (0x7E)DIDR0ADC7D ADC6D ADC5D ADC4D ADC3D ADC2D ADC1D ADC0D page 300ATmega640/1280/1281/2560/2561Address Name Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0Page (0x7D)DIDR2ADC15D ADC14D ADC13D ADC12D ADC11D ADC10D ADC9D ADC8D page 300 (0x7C)ADMUX REFS1REFS0ADLAR MUX4MUX3MUX2MUX1MUX0page 294 (0x7B)ADCSRB-ACME--MUX5ADTS2ADTS1ADTS0page 277,295,,299 (0x7A)ADCSRA ADE N ADSC ADATE ADIF ADIE ADPS2ADPS1ADPS0page 297 (0x79)ADCH ADC Data Register High byte page 298 (0x78)ADCL ADC Data Register Low byte page 298 (0x77)Reserved--------(0x76)Reserved--------(0x75)XMCRB XMBK----XMM2XMM1XMM0page 36 (0x74)XMCRA SRE SRL2SRL1SRL0SR W11SR W10SR W01SR W00page 34 (0x73)TIMSK5--ICIE5-OCIE5C OCIE5B OCIE5A TOIE5page 169 (0x72)TIMSK4--ICIE4-OCIE4C OCIE4B OCIE4A TOIE4page 169 (0x71)TIMSK3--ICIE3-OCIE3C OCIE3B OCIE3A TOIE3page 169 (0x70)TIMSK2-----OCIE2B OCIE2A TOIE2page 197 (0x6F)TIMSK1--ICIE1-OCIE1C OCIE1B OCIE1A TOIE1page 169 (0x6E)TIMSK0-----OCIE0B OCIE0A TOIE0page 135 (0x6D)PCMSK2PCI N T23PCI N T22PCI N T21PCI N T20PCI N T19PCI N T18PCI N T17PCI N T16page 81 (0x6C)PCMSK1PCI N T15PCI N T14PCI N T13PCI N T12PCI N T11PCI N T10PCI N T9PCI N T8page 81 (0x6B)PCMSK0PCI N T7PCI N T6PCI N T5PCI N T4PCI N T3PCI N T2PCI N T1PCI N T0page 82 (0x6A)EICRB ISC71ISC70ISC61ISC60ISC51ISC50ISC41ISC40page 79 (0x69)EICRA ISC31ISC30ISC21ISC20ISC11ISC10ISC01ISC00page 78 (0x68)PCICR-----PCIE2PCIE1PCIE0page 80 (0x67)Reserved--------(0x66)OSCCAL Oscillator Calibration Register page 48 (0x65)PRR1--PRTIM5PRTIM4PRTIM3PRUSART3PRUSART2PRUSART1page 56 (0x64)PRR0PRT W I PRTIM2PRTIM0-PRTIM1PRSPI PRUSART0PRADC page 55 (0x63)Reserved--------(0x62)Reserved--------(0x61)CLKPR CLKPCE---CLKPS3CLKPS2CLKPS1CLKPS0page 48 (0x60)W DTCSR W DIF W DIE W DP3W DCE W DE W DP2W DP1W DP0page 660x3F (0x5F)SREG I T H S V N Z C page 120x3E (0x5E)SPH SP15SP14SP13SP12SP11SP10SP9SP8page 140x3D (0x5D)SPL SP7SP6SP5SP4SP3SP2SP1SP0page 140x3C (0x5C)EI N D-------EI N D0page 150x3B (0x5B)RAMPZ------RAMPZ1RAMPZ0page 150x3A (0x5A)Reserved--------0x39 (0x59)Reserved--------0x38 (0x58)Reserved--------0x37 (0x57)SPMCSR SPMIE R WW SB SIGRD R WW SRE BLBSET PG W RT PGERS SPME N page 3400x36 (0x56)Reserved--------0x35 (0x55)MCUCR JTD--PUD--IVSEL IVCE page 66,76,115,3140x34 (0x54)MCUSR---JTRF W DRF BORF EXTRF PORF page 3140x33 (0x53)SMCR----SM2SM1SM0SE page 510x32 (0x52)Reserved--------0x31 (0x51)OCDR OCDR7OCDR6OCDR5OCDR4OCDR3OCDR2OCDR1OCDR0page 3070x30 (0x50)ACSR ACD ACBG ACO ACI ACIE ACIC ACIS1ACIS0page 2770x2F (0x4F)Reserved--------0x2E (0x4E)SPDR SPI Data Register page 2080x2D (0x4D)SPSR SPIF W COL-----SPI2X page 2070x2C (0x4C)SPCR SPIE SPE DORD MSTR CPOL CPHA SPR1SPR0page 2060x2B (0x4B)GPIOR2General Purpose I/O Register 2page 340x2A (0x4A)GPIOR1General Purpose I/O Register 1page 340x29 (0x49)Reserved--------0x28 (0x48)OCR0B Timer/Counter0 Output Compare Register B page 1340x27 (0x47)OCR0A Timer/Counter0 Output Compare Register A page 1340x26 (0x46)TC N T0 Timer/Counter0 (8 Bit)page 1340x25 (0x45)TCCR0B FOC0A FOC0B--W GM02CS02CS01CS00page 1330x24 (0x44)TCCR0A COM0A1COM0A0COM0B1COM0B0--W GM01W GM00page 1300x23 (0x43)GTCCR TSM-----PSRASY PSRSY N C page 173, 1980x22 (0x42)EEARH----EEPROM Address Register High Byte page 320x21 (0x41)EEARL EEPROM Address Register Low Byte page 320x20 (0x40)EEDR EEPROM Data Register page 320x1F (0x3F)EECR--EEPM1EEPM0EERIE EEMPE EEPE EERE page 320x1E (0x3E)GPIOR0General Purpose I/O Register 0page 340x1D (0x3D)EIMSK I N T7I N T6I N T5I N T4I N T3I N T2I N T1I N T0page 790x1C (0x3C)EIFR I N TF7I N TF6I N TF5I N TF4I N TF3I N TF2I N TF1I N TF0page 80。
CS5451资料
LIST OF FIGURES
Figure 1. Serial Port Timing............................................................................................................. 6 Figure 2. Typical Connection Diagram ............................................................................................ 7 Figure 3. Serial Port Data Transfer ................................................................................................. 8 Figure 4. Close-up of One Data Frame ........................................................................................... 9 Figure 5. Generating VA- with a Charge Pump............................................................................. 10
Decimation Filter
IIN2+ IIN2VIN2+ VIN2-
x1, 20
4th Order ∆Σ Modulator
Decimation Filter
8251A的编程字
8251A的编程字(1)工作方式控制字D1D0确定是工作于同步方式还是异步方式。
D1D0=00为同步方式，当方式设为同步时，方式控制字后必须装入同步字符，并由同一个方式控制字规定装入单同步字符还是双同步字符；D1D0≠00为异步方式，且有3种组合来选择输入的时钟频率与波特率之间的系数。
D3D2确定每个字符的数据位（不包括奇偶校验位）。
D5D4确定是否校验和奇偶校验的性质。
D7D6含义因同步方式或异步方式而异。
异步方式（D1D0≠00）时用来确定停止位个数。
同步方式时D6用来确定是内同步（SYNDET脚为输出）还是外同步（SYNDET为输入），D7用来确定同步字符个数。
外同步方式时，同步字符只用于发送，接收时不作用。
例：某异步通讯，数据位为8位，1位起始位、2位停止位、奇校验、波特率系数为16。
则有：11011110B=0DEHMOV DX，309H ；8251A命令口MOV AL，0DEHOUT DX，AL（2）工作命令控制字D0设置为1允许8251A开始发送操作。
只有命令字的D0=1，引脚T X DRY（通知CPU：发送器准备好）才可能有效（为1）。
可作为发送中断屏蔽位。
D1设置为1强制引脚DTR有效，表示数据终端准备好，通知调制解调器：8251A已准备好。
D2设置为1允许8251A开始接收数据。
只有命令字D2=1，RXRDY（通知CPU接收器准备好的引脚）才有可能为1。
允许接收时必须使错误标志复位（见D4）。
在同步方式时还必须指定进入同步搜索操作（见D7）。
D3设置为1迫使TXD端发送低电平，以此作断点字符。
D4设置为1则对状态字中的所有操作出错标志（FE，OE，PE）复位。
D5设置为1强制RTS引脚（请求发送）有效，向调制解调器提出发送请求。
D6设置为1强制8251A内部复位，使之回到准备接收方式字的状态。
D7只用于同步方式。
为使8251A进入同步搜索操作，将输入的信息和同步字符比较，一致则使SYNDET/BRKDET（同步/断点检测）引脚有效，开始对数据的接收操作。
521A资料
Absolute Maximum Ratings1Parameter Rating Supply Voltage, V DD-0.3, +3.63VVoltage on any Digital Input or Output3-0.3V to V DD +0.3VInput Current on any pin3±5mA Package Input Current3±20mARelative Humidity (non-operating)5% - 85% RH @ 25°C to 70°CMaximum Junction Temperature, TJmax 150°C Storage Temperature Range-60°C to +150°C IR Reflow Peak Temperature 260°C Lead Soldering Temperature (10 sec.) 300°CHuman Body Model 2000 VMachine Model 250 V ESD5Charged-Device Model >1000 V Notes:1. Absolute maximum ratings are limits beyond which operationmay cause permanent damage to the device. These arestress ratings only; functional operation at or above theselimits is not implied. For guaranteed specifications and testconditions, see the Electrical Characteristics. The guaranteedspecifications apply only for the test conditions listed. Someperformance characteristics may degrade when the device isnot operated under the listed test conditions.2. All voltages are measured with respect to GND, unlessotherwise specified.3. When the input voltage (VIN) at any pin exceeds the powersupplies (VIN< (GND or GNDA) or VIN>V+, except for SSTand analog voltage inputs), the current at that pin should belimited to 5mA. The 20mA maximum package input currentrating limits to number of pins that can safely exceed thepower supplies with an input current of 5mA to four.4. The maximum power dissipation must be de-rated at elevatedtemperatures and is dictated by TJmax, θJA and the ambienttemperature, T A. The maximum allowable power dissipation atany temperature is PD = (TJmax - TA) / θJA. It must also takeinto account self-heating that can adversely affect theaccuracy of internal sensors.5. Human Body Model: 100pF capacitor discharged through a1.5kΩ resistor into each pin. Machine Model: 200pF capacitordischarged directly into each pin. Charged-Device Model isper JESD22-C101C.Electrical Characteristics6(-40°C≤T≤+125°C, V= 3.3V unless otherwise noted. Specifications subject to change without notice)A D DParameter Conditions Min Typ Max UnitsSupply Voltage V DD 3.03.33.6VSST SignalMeets SST Specification Version 1.0for 1.5V interface-40°C≤T A≤+125°C ±3°CLocal Sensor Accuracy7, 840°C≤T A≤70°C ±2 °C Local Sensor Resolution 0.125 °C0°C≤T A≤70°C, -40°C≤T D ≤+125°C ±3 °CRemote Diode Sensor Accuracy7, 8, 90°C≤T A≤70°C,50°C≤T D ≤70°C±1 °CRemote Diode Sensor Resolution 0.125 °CTemperature Monitor Cycle Time10t C0.2SecNotes:6. These specifications are guaranteed only for the test conditions listed.7. Accuracy (expressed in °C) = Difference between the aSC7521A reported temperature and the device temperature.8. The aSC7521A can be read at any time without interrupting the temperature conversion process.9. Calibration of the remote diode sensor input is set to meet the accuracy limits with a CPU thermal diode that has a non-ideality factor of1.009 with a series resistance of 4.52Ω.10. Total monitoring cycle time for all temperature and analog input voltage measurements is 0.2 second.SST SensorsThe SST temperature sensor provides a means for an analog signal to travel over a single-wire digital bus enabling remote temperature sensing in areas previously not monitored in the PC. The temperature sensor supports an internal temperature sensor and external thermal diodes.This section outlines general requirements for Simple Serial Transport (SST) sensors intended for use in PC desktop applications that conform to SST Version 1.0 specification. The aSC7521A reports external temperature sensed by a remote diode-connected transistor and an internal temperature measurement.AddressingThe aSC7521A complies with the address range set aside for fixed-address, discoverable devices as defined in the SST Specification Version 1.0. Simple Temperature sensors use fixed addresses in the range of 0x48 to 0x50. The aSC7521A may be programmed to any of these addresses via the address select pins AD0 and AD1.Frame Check Sequence (FCS)Each message requires a frame check sequence byte to ensure reliable data exchange between host and client. The message originator and client both make an FCS calculation. One FCS byte must be returned from the message target to the originator after all bytes including the header and the data block are written. If data is read from the target, a second FCS byte must follow the data block read.The FCS byte is the result of an 8-bit cyclic redundancy check (CRC) of the each data block preceding the FCS up to the most recent, earlier FCS byte. The first FCS in the message does not include the two address timing negotiation ‘0’ bits that precede the address byte or the message timing negotiation bit after the address byte. The first FCS does include the address byte in its computation. The FCS is initialized at 0x00 and is calculated in a way that conforms to a CRC-8 represented by the CRC polynomial, C(x) = x8 + x2 + x + 1.Bus VoltageAll SST sensor devices used for PC applications must be capable of operating the SST interface portion of the sensor device at 1.5 volts as defined in 1.5 Volt Static (DC) Characteristics section of the SST Version 1.0 specification. Bus TimingAll SST sensor devices must be able to negotiate timing and operate at a maximum bus transfer rate of 2-Mbps. If the bus address timing is negotiated at a lower rate due to the performance limitations of other devices on the bus, the sensor device will operate at that lower rate. Device Power-on TimingFollowing a power-on reset, such as a system transitioning from S3-S5 to S0, the aSC7521A will be able to participate in the address and message timing negotiation and respond to required SST bus commands such as respond to a GetDIB() command within 10ms of the device’s V DD rail reaching 90%. The aSC7521A has an internal power on reset and will be fully functional within 50ms of power on.The aSC7521A does not employ any device power management.Voltage and Temperature Sensor DataLittle Endian FormatThe bit level transfer is defined in the SST specification. The 2-byte data values are returned in little Endian format, in other words, the LSB is sent first followed by MSB.For multi-function devices that allow access to multiple sensors, the data is returned LSB followed by the MSB for the first sensor, LSB followed by the MSB for the second sensor, and so on. The specific order is explicitly specified in the command description.Atomic ReadingsThe aSC7521A ensures that every value returned is derived from a single analog to digital conversion and is not skewed (e.g. the MSB and the LSB come from two different conversions).Conversion TimeThe maximum refresh time for all temperature values is200ms. The aSC7521A provides the logic to ensure all readings meet the conversion time requirements. Temperature DataData Precision, Accuracy and ResolutionThe temperature data meets the following minimum requirements:•Operational Range: -40°C to +125°C•Internal Sensor Accuracy:o+/- 3°C over operational rangeo+/- 2°C over 40°C to 70°C•Remote Sensor Accuracy (when TA is from 0°C to 70°C):o+/- 3°C over operational rangeo+/- 1°C over 50°C to 70°C• Resolution:0.125°CTemperature Data FormatThe data format is capable of reporting temperature values in the range of +/-512°C. The temperature sensor data is returned as a 2’s complement 16-bit binary value. It represents the number of 1/64°C increments in the actual reading. This allows temperatures to be represented with approximately a 0.016°C resolution.Values that would represent temperatures below -273.15°C (0 K or absolute zero) are reserved and are not be returned except as specifically noted.For the aSC7521A the required resolution is 0.125°C. Bits [2:0] will be defined but they are beyond the required resolution. The sign bit will indicate a negative temperature except when reporting an error condition (see Sensor Error Condition). Temperature 2’s complement representation 80°C 0001 0100 0000 0000 79.875°C 0001 0011 1111 1000 1°C 0000 0000 0100 0000 0°C 0000 0000 0000 0000-1°C 1111 1111 1100 0000-5°C 1111 1110 1100 0000 Table 1. Temperature RepresentationSign Integer Temperature 0°C to 512°CFractionalTemperatureLSB 0.125°CAlways Zero15 14 13 12 11 10 9 8 7 6 ● 5 4 3 2 1 0Figure 2. Temperature ReadingA to D Converter Resolution and MappingThe mapping of the A-D converter bit values is a two’s complement representation with the binary point between bits 5 and 6 of the 16-bit data word. Bit 15 is the sign, bits 14 through 6 are integer temperature in degrees, bits 5 down to 3 are the fractional part with 0.125°C as the LSB. The lowest 3 bits are set to zero.Temperature InputsThe simple temperature sensor has an internal thermal sensor plus an external sensor using a remote diode. Both temperature readings are internally corrected for lead resistance and non-ideality for the thermal diode of a Pentium™ 4, 65nM process (1.009 non-ideality, 4.35Ω lead resistance). The range of measurement currents falls within the Intel recommended range of 10μA and 170μA to minimize the impact of Beta variation in the CPU substrate thermal diode. Note that Pentium 4, 90 nM process is 1.011 non-ideality and series resistance of 3.33Ω.If a diode connected discrete transistor is used instead of a CPU diode, a correction must be applied to the reading to compensate for the difference in non-ideality. A 2N3904 NPN transistor has a non-ideality (η) factor of approximately 1.04. To correct the value reported to the actual temperature use the following formula:T ACTUAL = T REPORTED x ηTransistor / 1.009 It is recommended that the actual transistor type and manufacturers chosen for the remote sensor be characterized for non-ideality as part of system qualification. Sensor Error ConditionThe aSC7521A has the capability to detect and report open or shorted external diode inputs per Sensor Error Condition. When an error or failure condition is detected, the sensor device must return a large negative value in response to either the GetIntTemp() or GetExtTemp() command. In this manner software is provided with a means to determine whether or not the sensor is working normally and that the data returned is good.The aSC7521A will write one of the values from the table below to appropriate memory locations for GetIntTemp() and/or GetExtTemp().The aSC7521A uses the OEM defined values of 0x8102 (open) and 0x8103 (short) rather than the generic errors defined for codes 0x8000 to 0x8003.Error Code Description0x8000 to 0x80FF Reserved0x8102 Remote Diode Open0x8103 Remote Diode Short0x8100-0x81FF ReservedTable 2. Error CodesSST InterfaceMulti Client ModeSensors operate in multi-client mode for read bit timing. Reference the SST Specification Version 1.0 for details.SST Device CommandsGetDIB() Command (0xF7)Read the Device Identifier Block (DIB). The read length of the command is either 8 or 16 bytes. 8 bytes is the minimum number of bytes populated by a fixed address discoverable client.Write Data Length: 0x01Read Data Length: 0x08/0x10Command Code: 0xF7Note: Un-shaded table entries are created by the host. Shaded entries are the response bytes from the aSC7521A to the host.# Bits # BitsHost Sending aSC7521A SendingHex Value Hex Value8 8 8 8 8Target Address Write Length Read Length GetDIB Cmd FCS0x48 0x01 0x10 0xF7 0xDC8 8 8 8 8DIB Byte 1 … DIB Byte 15 DIB Byte 16 FCS(data) (data) (data) (data) (data dependent)Figure 3. GetDIB() Command (16-byte read length)8 8 8 8 8Target Address Write Length Read Length GetDIB Cmd FCS0x48 0x01 0x08 0xF7 0x238 8 8 8 8DIB Byte 1 … DIB Byte 7 DIB Byte 8 FCS (data) (data) (data) (data) (data dependent)Figure 4. GetDIB() Command (8-byte read length)Ping() CommandThe Ping() command provides a safe means for software to verify that a device is responding at a particular address.Write Data Length: 0x00Read Data Length: 0x00Command Code: none8 8 8 8Target Address Write Length Read Length FCS0x48 0x00 0x00 0xD7Figure 5. Example of Ping()ResetDevice() CommandThe ResetDevice() command is used to reset all device functions to their power-on reset values. It is used by the system to recover from serious hardware or bus errors.Write Data Length: 0x01Read Data Length: 0x00Command Code: 0xF68 8 8 8 8Target Address Write Length Read Length ResetDeviceCommandFCS0x48 0x01 0x00 0xF6 0x8C Figure 6. ResetDevice() format targeting a non-default address8 8 8 8Target Address Write Length Read Length ResetDevice Command0x00 0x01 0x00 0xF6Figure 7. ResetDevice() format targeting the default addressSensor Command SummaryGetIntTemp()Returns the temperature of the device’s internal thermal sensor.Write Data Length: 0x01Read Data Length: 0x02Command Code: 0x00Example bus transaction for a thermal sensor device located at address 0x48 returning a value of 60°C:8 8 8 8Target Address Write Length Read Length Command0x48 0x01 0x02 0x008 8 8 8FCS LSB MSB FCS0x6A0x000x0F0x2DFigure 8. Get Internal Temperature Command ExampleGetExtTemp()Returns the temperature of the external thermal diode.Write Data Length: 0x01Read Data Length: 0x02Command Code: 0x01GetAllTemps()Returns a 4-byte block of data containing both the Internal and External temperatures in the following order Internal then External temperatures.Write Data Length: 0x01Read Data Length: 0x04Command Code: 0x00Optional SST Device CommandsThe optional SST commands Alert(), Suspend() are not supported in the aSC7521A.Vendor Specific ExtensionsThe vendor specific command codes are in the range from 0xE0 and 0xE7. Reading and writing to specific internal registers is provided for custom tuning of sensor response characteristics.WriteReg()Writes to the sensor’s internal registers.Write Data Length: 2+N (command + address + Number of bytes to write)Read Data Length: 0x00Command Code: 0xE0Example bus transaction to write to a sensor located at address 0x48. This example writes 2 consecutive locations (0x20 and 0x21) to values 0x25 and 0x28.8 8 8 8Target Address Write Length Read Length Command0x48 0x04 0x00 0xE08 8 8 8RAM Addr Write Data Write Data FCS0x20 0x25 0x28 0x1BFigure 9. Example Register WriteReadReg()Reads from the sensor’s internal registers.Write Data Length: 0x02 (command + address)Read Data Length: N (Number of bytes to read)Command Code: 0xE1Example bus transaction to read a sensor located at address 0x48. This example reads 2 consecutive locations (0x20 and 0x21).8 8 8 8Target Address Write Length Read Length Command0x48 0x02 0x02 0xE18 8 8 8RAM Addr FCS Read Data Read Data FCS0x20 0x9D 0x25 0x28 0x37Figure 10. Example Register ReadVenCmdEnable()Vendor Command Enable enables the Vendor Specified Extensions.Write Data Length: 0x01Read Data Length: 0x00Command Code: 0xE28 8 8 8 8Target Address Write Length Read Length Command FCS0x48 0x01 0x00 0xE2 0xE0Figure 11. Vendor Command EnableVenCmdDisable()Vendor Command Disable disables the Vendor Specified Extensions.Write Data Length: 0x01Read Data Length: 0x00Command Code: 0xE38 8 8 8 8Target Address Write Length Read Length Command FCS0x48 0x01 0x00 0xE3 0xE7Figure 12. Vendor Command DisableReserved or Unsupported CommandsAttempts to access the sensor using a reserved or unsupported command will not result in the device or bus failure. The sensor will return a modified FCS when any of the following commands are received. To modify the FCS the sensor will invert all of the bits in the correct FCS (1’s complement). A modified FCS is also called an Abort FCS.The sensor will return an Abort FCS (modified FCS) for a reserved and unsupported command code (commands codes between0xE4 to 0xF5 and 0xF8 to 0xFF).The sensor will return an Abort FCS (modified FCS) for reserved commands (command codes 0x02 to 0xDF.The sensor will return an Abort FCS (modified FCS) for unused vendor specific test and manufacturing command codes (command codes 0xE8 to 0xEF). If any of these types of commands exist, they will be disabled during normal operation.Malformed CommandsA malformed command is one which is valid but has an incorrect write or read length for the given command.If a get temperature command with a write length not equal to 1 is sent, then the aSC7521A will send an Abort FCS and wait for a new command. An Abort FCS will be formed by creating a 1’s complement of the the good FCS.If a get temperature command and the read length is not equal to 2 or 4 then te aSC7521A will send an Abort FCS and wait for a stop on the SST bus. See the Command Summary section for the expected Write and Read lengths of the legal commands.There will be no checking for malformed WriteReg() and ReadReg() commands (Vendor Specific Extensions).Command SummaryHex CmdCommand NameReceived BytesWr LenRd LenBytes Sent by Client- Ping()3(target,wr,rd) 0 0 FCS 0x00 GetIntTemp()4(target,wr,rd,cmd) 1 2 FCS/2/FCS 0x01 GetExtTemp()4(target,wr,rd,cmd) 1 2 FCS/2/FCS 0x00 GetAllTemps()4(target,wr,rd,cmd) 1 4 FCS/4/FCS 0x02-0xDF Unsupported Abort FCS 0xE0 WriteReg()4(target,wr,rd,cmd) 3+ 0 FCS 0xE1 ReadReg()4(target,wr,rd,cmd) 2 1+ FCS/1+/FCS 0xE2 VenCmdEnable()4(target,wr,rd,cmd) 1 0 FCS 0xE3 VenCmdDisable()4(target,wr,rd,cmd) 1 0 FCS 0xE4-0xF5 Unsupported Abort FCS 0xF6 ResetDevice()4(target,wr,rd,cmd) 1 0 FCS 0xF6 ResetDevice()4(target,wr,rd,cmd) 1 0 None if default address (0x00) 0xF7 GetDIB()4(target,wr,rd,cmd) 1 8 FCS/8/FCS 0xF7 GetDIB()4(target,wr,rd,cmd) 1 16 FCS/16/FCS 0xF8-0xFF Unsupported Abort FCSTable 3. Command SummaryDevice Identifier Block (DIB)The Device Identifier Block describes the identity and functions of a client device on the SST bus. Sixteen bytes are allocated for this function as shown in Figure 13. Device Identifier Block is returned by the aSC7521A with a GetDIB() command. The aSC7521A returned values are shown with the description of each field below.8 8 16 16 8Vendor ID Device ID Device Capabilities Version/Revision LSB MSB LSB MSBDevice Interface8 8 8 16 24 8FunctionInterfaceDeviceInterface ExtensionReserved ReservedVendor Specific ID Client Device Address Figure 13. Device Identifier BlockDevice Capabilities Field (1-byte)MSB 6 5 4 3 2 1 LSBAddress Type ReservedWake Capable Alert Support Suspend SupportSlowDevice 110 0 0 0 0 0Figure 14. Device Capabilities FieldVersion / Revision Field (1-byte)MSB 65 4321LSBPre-release SST Version Minor Revision1 0010000 (default) for V1.0 Pre-production 00010000 for V1.0 ProductionFigure 15. Version / Revision FieldVendor ID Field (2-bytes)Andigilog Vendor ID is 16 bits = 0x19C9 (This field is stored in the format LS Byte, MS Byte = 0xC919). Vendor IDs can be foundat: /membership/vid_searchDevice ID Field (2-bytes)This field uniquely identifies the device from a specific vendor. Place the least significant byte as the first byte and the most significant byte as the second byte.Part Number Value (MS,LS) Stored Value (LS,MS) aSC7521A 0x7521 0x2175Device Interface Field (1-byte)The vendor sets to ‘1’, bit positions in this field in the event the device supports higher layer protocols that are industry specific using Table 4.Value = 0x02Bit Protocol Meaning 7 - Reserved for future use , must be set = ‘0’ 6 - Reserved for future use , must be set = ‘0’ 5 IPMI Device supports additional access and capabilities per the IPMI specification. 4 ASF Device supports additional access and capabilities per the ASF specification. 3 Serial-ATA Device supports additional access and capabilities per the serial-ATA specification.2 PCI-ExpressDevice supports additional access and capabilities per the PCI Expressspecification.1 SSTDevice supports additional access and capabilities per the SST FunctionalDescriptor Specification (to be published at a future date).0 OEMDevice supports vendor-specific additional access and capabilities per the VendorID and Device ID.Table 4. Device Interface FieldFunction Interface Field (1-byte)This field provides a mechanism for a device to pass higher-layer SST device-specific information.Value = 0x00Device Interface Extension Field (1-byte)This field is used to provide additional information about the device to the upper layers of software.Value = 0x00Reserved Field (3-bytes)Value = 0x00 0x00 0x00Vendor Specific ID Field (1-byte)This field is set by the vendor in a way that uniquely identifies this device apart from all others with an otherwise common DIB content.Value = 0x00 – For Fixed address devices this field may be set to zero.Client Device Address (1-byte)SST Client Device Address is set according to the connection of pins ADD0 and ADD1. Float is defined as an unconnected pin.ADD0 ADD1 AddressGround Ground 0x48Float Ground 0x49V DD Ground 0x4AGround Float 0x4BFloat Float 0x4CV DD Float 0x4DGround V DD0x4EFloat V DD0x4FV DD V DD0x50sensor is very close to the circuit board temperature and typically between the board and ambient.In order to measure PC board temperature in an area of interest, such as the area around the CPU where voltage regulator components generate significant heat, a remote diode-connected transistor should be used. A surface-mount SOT-23 or SOT-223 is recommended. The small size is advantageous in minimizing response time because of its low thermal mass, but at the same time it has low surface area and a high thermal resistance to ambient air. A compromise must be achieved between minimizing thermal mass and increasing the surface area to lower the junction-to-ambient thermal resistance.In order to sense temperature of air-flows near board-mounted heat sources, such as memory modules, the sensor should be mounted above the PC board. A TO-92 packaged transistor is recommended.The power consumption of the aSC7521A is relatively low and should have little self-heating effect on the local sensor reading. At the highest measurement rate the dissipation is less than 2mW, resulting in only a few tenths of a degree rise.Notes:Andigilog, Inc.8380 S. Kyrene Rd., Suite 101 Tempe, Arizona 85284Tel: (480) 940-6200Data Sheet ClassificationsPreliminary SpecificationThis classification is shown on the heading of each page of a specification for products that are either underdevelopment (design and qualification), or in the formative planning stages. Andigilog reserves the right to change ordiscontinue these products without notice.New Release SpecificationThis classification is shown on the heading of the first page only of a specification for products that are either underthe later stages of development (characterization and qualification), or in the early weeks of release to production.Andigilog reserves the right to change the specification and information for these products without notice.Fully Released SpecificationFully released datasheets do not contain any classification in the first page header. These documents containspecification on products that are in full production. Andigilog will not change any guaranteed limits without writtennotice to the customers. Obsolete datasheets that were written prior to January 1, 2001 without any headerclassification information should be considered as obsolete and non-active specifications, or in the best case asPreliminary Specifications.Pentium™ is a trademark of Intel CorporationLIFE SUPPORT POLICYANDIGILOG'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES ORSYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF ANDIGILOG,INC. As used herein:1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b)support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in thelabeling, can be reasonably expected to result in a significant injury to the user.2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expectedto cause the failure of the life support device or system, or to affect its safety or effectiveness.Andigilog, Inc.8380 S. Kyrene Rd., Suite 101Tempe, Arizona 85284Tel: (480) 940-6200。
LMX2531中文资料
--低工作电流 --支持 1.8V MICROWIRE --封装：LLP 36 引脚
内部功能块示意图
引脚连接图
引脚描述
Pin#
引脚名称 I/O
描述
数字 LDO 电路电源输入端。电压输入范围 2.8-3.2V。旁路电容应尽量靠近该
1
VccDIG -
引脚。
3
GND
接地端
2，4，5， 7，12，
NC 13，29，
19
GND
- VCO 电路接地端。
20
GND
- VCO 输出缓冲电路接地端。
21
Fout
o VCO RF 信号输出端。
VCO 缓冲电路电源输入端。输入电压范围 2.8-3.2V。旁路电容应尽量靠近该
22
VccBUF -
引脚。
23
Vtune I VCO 电压控制端。通过外部滤波电路连接到 Cpout。
电压 环境温度
符号
Vcc
VI
TA
最小值
2.8 0 -40
典型值
3.0
最大值
3.2
2.75 +85
单位
V V ℃
符号
Icc
IccPD IIHOSC IILOSC foscin Voscin
电器特性（Vcc=3.0V,-40℃≤TA≤85℃；）
参数
情况
最大值
电流消耗
供电电流
（
除
LMX2531LQ2265E，
存器，使之重新锁定。
14.15
NC
空脚，不连接，也不接地。
16
VccVCO
VCO 校准电路电源输入端。输入电压范围 2.8-3.2V。旁路电容应尽量靠近该 引脚。
2561a 工作原理
2561a 工作原理2561a作为一种常见的电源控制芯片，被广泛应用于各种电子产品中。
那么，它的工作原理是怎样的呢？首先，2561a是一种完全集成的电源管理IC，内置了多种保护电路和控制电路。
使用2561a可以简化电路设计、减小体积并提高效率。
其具体工作步骤如下：Step 1：输入电压检测当电源电压投入时，2561a开始检测输入电压。
如果输入电压低于芯片所设定的最小电压，则芯片本身不会工作，因为这时候电力系统的电压并不能带动IC。
Step 2：启动UVLO保护当输入电压超过芯片所允许的最大电压时，根据芯片设计，会启动低电压保护电路，断开电源电路，避免电路过压损坏。
Step 3：控制开关管接下来是控制开关管。
当芯片检测到输入电压符合工作范围要求，它会通过传给控制开关管的信号来控制开关管通断，根据实际情况控制输出电压。
Step 4：控制提升次数提升电源电压除了靠控制开关管，还需要控制提升次数。
也就是说，2561a可以控制开关管启闭的频率，然后通过升压控制来达到需要的输出电压。
Step 5：过电流保护当输出电流超过芯片的额定值时，2561a会自动启动过电流保护，保护整个电路不受损坏。
通过以上步骤，可以看出2561a有多种保护电路和控制电路，可以很好地保护电路不受损坏。
此外，2561a还有精密的反馈环路，它可以减小电路中的纹波，并调整输出电压的稳定性。
在使用2561a时，需要注意输入电压的范围和内部反馈网络的设置。
虽然2561a有很多保护电路，但如果使用不当，仍有可能损坏芯片，因此合理使用非常重要。
综上所述，2561a作为一种高度集成的电源管理IC，可以提高电路效率，减小电路体积。
其工作原理是经过精心设计的复杂过程，包括输入电压检测、启动低电压保护、开关管调节、提升次数控制、过电流保护等多个步骤。
只有合理使用，才能发挥它的最大性能，为各类电子产品提供高效稳定的电源。
8XC251TP资料
ADVANCE INFORMATION© INTEL CORPORATION, 1997November, 1997Order Number: 273129-001Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.The 8xC251TA/TB/TP/TQ may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from:Intel CorporationP.O. Box 5937Denver CO 80217-9808or call 1-800-548-4725.Many documents are available for download from Intel’s website at .Copyright © Intel Corporation 1997.*Third party brands and names are the property of their respective owners.ContentsADVANCE INFORMATION iiiContentsiv ADVANCE INFORMATION8xC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLERADVANCE INFORMATION18xC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER2ADVANCE INFORMATION8xC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER ADVANCE INFORMATION38xC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER4ADVANCE INFORMATION8xC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER ADVANCE INFORMATION58xC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER6ADVANCE INFORMATION。
USB充电电源开关控制器
备（例如： iPod® 和 iPhone®）
CTL1～CTL3 逻辑输入用于从 TPS2540 / 40A 和 TPS2541 所提供的多种充电模式中选择其一。 这些充 电模式允许主机设备在专用充电端口 (DCP) （模仿墙 上适配器）、充电下游端口 (CDP) （可支持 1.5A 充 电电流的有源 USB 2.0 数据通信） 或标准下游端口 (SDP) （可支持 500mA 电流的有源 USB 2.0 数据通 信） 之间进行主动选择。 此外，TPS2540 / 40A /41 还集成了一种自动检测功能，该功能既支持符合电池充 电规范 (BC1.2) 的 DCP 方案，同时也支持分频器模式 (Divider Mode)，无需用户从外部进行干预。
-65
150
°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
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OCXO SERIES 5100
"FEATURES
Miniature OCXO in modified CO-15 package
Low current cnsumption
Frequencies up to 155.520 MHz
"ELECTRICAL PERFORMANCE
PARAMETER OCXO SERIES 5000
AT CUT CRYSTAL SC CUT CRYSTAL Supply voltage, nom. 5V ±5% (3.3V Optional)
Power dissipation steady state 1.5 Watt Max.
Heat up power 3 Watt Max
Heat up time. 3 min Max
Frequency range 1 To 155.520 MHz Standard
Frequency Adjustment ±10PPM Min (0 to 5V) ±0.7PPM Min (0 to 5V)
±0.05 PPM ±0.1 PPM
±0.25 PPM ±0.01 PPM ±0.02 PPM ±0.03 PPM
Freq. stability vs. temperature
LX: 0°C to 60°C
FZ: -30°C to 70°C
D3: -40°C to 85°
(Standard, contact factory for different temp ranges and stabilities) Freq. stability vs. supply
changes
±0.015 PPM Max for ±5% Change ±0.010 PPM Max for ±5% Change Freq. stability vs. load changes ±0.01 PPM Max for ±5% Change ±0.005 PPM Max for ±5% Change
Long term stability (Aging) ±4 PPM Max for 10 Years
±0.005 PPM/Day Max. ±1 PPM Max for 10 Years ±0.002 PPM/Day Max.
Output HCMOS/TTL/Sine 0 to +7dBm (Low voltage CMOS Available)
Harmonics -30dBc(Sine
Output) Spurious -75dBc(Sine
Output) Duty cycle 40/60% to 60/40%(HCMOS)
Rise / fall time 10nS Max. (HCMOS,10%~90%Vout, 90%~10%Vout)
Short term Stability 1 E-10 /Sec 5 E-11 /Sec
Phase Noise Offset Phase Noise
10Hz -90 dBc/Hz
100Hz -125 dBc/Hz
1000Hz -135 dBc/Hz
10000Hz -150 dBc/Hz Offset Phase Noise 10Hz -110 dBc/Hz 100Hz -125 dBc/Hz 1000Hz -140 dBc/Hz 10000Hz -150 dBc/Hz
" HOW TO ORDER (PART NUMBER)
Prefix Output Type Cut Type Series Revision Temperature Range Stability Frequency OX
2:HCMOS 4:LVCMOS 6:SINE
0:AT (No Vcontrol ) 1: SC (No Vcontrol ) 4: AT (Elect Vcontrol) 5: SC (Elect Vcontrol)
50:5000
A
First letter Lowest Temperature,
Second letter Highest Temperature:
From A=-55°C to Z=+70°C, Then: 1=+75°C, 2=+80°C, 3=+85°C… in 5°C steps Example: LZ: +0°C to +70°C LX: +0°C to +60°C FZ: -30°C to +70°C D3: -40°C to +85°C
Value x 10E-2 in PPM
Example 28= 0.28PP M 10= 0.1PPM
In MHZ。