M5M5V108DFP-70H中文资料

1048576-BIT(131072-WORD BY8-BIT)CMOS STATIC RAMDESCRIPTIONFEATURESThe M5M5V108DFP,VP,KV are a 1048576-bit CMOS static RAM organized as 131072 word by 8-bit which are fabricated using high-performance triple-polysilicon and double metal CMOS technology. The use of thin film transistor (TFT) load cells and CMOS periphery result in a high density and low power static RAM.They are low standby current and low operation current and ideal for the battery back-up application.The M5M5V108DVP,KV are packaged in a 32-pin thin small outline package which is a high reliability and high density surface mount device(SMD).PackageAPPLICATIONSmall capacity memory unitsDirectly TTL compatible : All inputs and outputsEasy memory expansion and power down by S1,S2Data hold on +2V power supplyThree-state outputs : OR - tie capabilityOE prevents data contention in the I/O busCommon data I/OM5M5V108DFP ············32pin 525mil SOPM5M5V108DVP,RV············32pin 8 X 20 mm TSOPM5M5V108DKV,KR ············32pin 8 X 13.4 mm TSOP221048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAMFUNCTIONThe operation mode of the M5M5V108D series are determined by a combination of the device control inputs S 1,S 2,W and OE.Each mode is summarized in the function table.A write cycle is executed whenever the low level W overlaps with the low level S 1and the high level S 2. The address must be set up before the write cycle and must be stable during the entire cycle.The data is latched into a cell on the trailing edge of W,S 1or S 2,whichever occurs first,requiring the set-up and hold time relative directly controls the output stage. Setting the OE at a high level,the output stage is in a high-impedance state, and the data bus contention problem in the write cycle is eliminated.A read cycle is executed by setting W at a high level and OE at a low level while S 1and S 2are in an active state(S 1=L,S 2=H).When setting S 1at a high level or S 2at a low level, the chip are in a non-selectable mode in which both reading and writing are disabled. In this mode, the output stage is in a high- impedance state, allowing OR-tie with other chips and memory expansion by S 1and S 2. The power supply current is reduced as low as the stand-by current which is specified as I CC3or I CC4, and the memory data can be held at +2V power supply, enabling battery back-up operation during power failure or power-down operation in the non-selected mode.FUNCTION TABLE1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAMABSOLUTE MAXIMUM RATINGSCAPACITANCE Symbol ParameterTest conditionspF pFUnit Max 810TypMinLimits V I =GND, V I =25mVrms, f=1MHz V O =GND,V O =25mVrms, f=1MHzInput capacitance Output capacitanceC I C OParameterSupply voltage Input voltageOutput voltage Power dissipationOperating temperature Storage temperatureUnit V V V mW °C °CConditionsWith respect to GND Ta=25°C7000~70– 65~150Ratings Symbol V cc DC ELECTRICAL CHARACTERISTICS (Ta=0~70°C, Vcc=2.7~3.6V, unless otherwise noted)Symbol ParameterV V V Max TypLimitsMin Test conditionsUnit V µA – 0.3*~4.6– 0.3*~Vcc + 0.3(Ta=0~70°C, unless otherwise noted)0~Vcc * –3.0V in case of AC ( Pulse width ≤ 30ns )Note 1: Direction for current flowing into an IC is positive (no mark).2: Typical value is Vcc = 3V, Ta = 25°CmA * –3.0V in case of AC ( Pulse width ≤ 30ns )µAµAV Vcc + 0.30.62.0–0.3*2.40.33Stand-by current0.4±1Active supply current Active supply currentVcc – 0.5±135V IH V IL V OH1V OH2V OL I I I O I CC1I CC2I CC3I CC4High-level input voltage Low-level input voltage High-level output voltage 1High-level output voltage 2Low-level output voltage Input currentOutput current in off-state Stand-by currentI OH = – 0.5mA I OH = – 0.05mAI OL = 2mA V I =0~VccS 1=V IH or S 2=V IL or OE=V IH V I/O =0~V CCS 1=V IL ,S 2=V IH ,other inputs=V IH or V IL Output-open(duty 100%)1) S 2≤ 0.2Vother inputs=0~V CC 2) S 1≥ V CC –0.2V,S 2 ≥ V CC –0.2Vother inputs=0~V CC S 1=V IH or S 2=V IL ,other inputs=0~V CC~25°C (Max 4.6)~40°C ~70°C1.23.612570ns 1MHz V I V O P d T opr T stg-H1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM(2)READ CYCLE(3)WRITE CYCLESymbol Parametert CR Read cycle timeAddress access timeUnit ns ns ns ns ns ns ns ns ns ns ns nsSymbol ParameterUnit ns ns ns ns ns ns ns ns ns ns ns ns nsLimitst a(S1)t a(S2)t a(OE)t dis(S1)t dis(S2)t dis(OE)t en(S1)t en(S2)t en(OE)t V(A)t a(A)Limits AC ELECTRICAL CHARACTERISTICS (Ta=0~70°C, unless otherwise noted ) (1)MEASUREMENT CONDITIONSChip select 1 access time Chip select 2 access time Output enable access timeOutput disable time after S 1high Output disable time after S 2low Output disable time after OE high Output enable time after S 1low Output enable time after S 2high Output enable time after OE low Data valid time after address70707035252525701010510Write cycle time Write pulse width Address setup timeAddress setup time with respect to W Chip select 1 setup time Chip select 2 setup time Data setup time Data hold timeWrite recovery timeOutput disable time from W low Output disable time from OE high Output enable time from W high Output enable time from OE low252570550656565300055V CC 2.7~3.6VInput pulse level V IH =2.2V,V IL =0.4V Input rise and fall time 5nsReference level V OH =V OL =1.5V Output loads Fig.1, C L =30pFC L =5pF (for t en ,t dis )Transition is measured ± 500mV from steady state voltage. (for t en ,t dis ).....................................................................................includingscope and JIGDQFig.1 Output loadMin Max -70H Max Min t CW t w(W)t su(A)t su(A-WH)t su(S1)t su(S2)t su(D)t h(D)t rec(W)t dis(W)t dis(OE)t en(W)t en(OE)-70H1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAMRead cycleWrite (W (4)TIMINGDIAGRAMS DQ 1~8S 1S 2OEWA 0~16DQ 1~8S 1S 2OEA 0~161048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAMWrite cycle (S 1control mode)Write cycle (S 2control mode)DQ 1~8S 1S 2WA 0~16DQ 1~8S 1S 2WA 0~16Note 3: Hatching indicates the state is "don't care".4: Writing is executed while S 2high overlaps S 1and W low.5: When the falling edge of W is simultaneously or prior to the falling edge of S 1or rising edge of S 2, the outputs are maintained in the high impedance state.6: Don't apply inverted phase signal externally when DQ pin is output mode.1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAMV CC = 3V1) S 2 ≤ 0.2V,other inputs = 0~3V 2) S 1 ≥ V CC –0.2V,S 2 ≥ V CC –0.2Vother inputs = 0~3V(Ta=0~70°C, unless otherwise noted)(3)POWER DOWN CHARACTERISTICS S 1control modePOWER DOWN CHARACTERISTICS(1)ELECTRICAL CHARACTERISTICS Power down set up time Power down recovery time(2)TIMING REQUIREMENTS (Ta=0~70°C, unless otherwise noted )t su (PD)t rec (PD)Symbol Parameterns MaxTypLimits Min Test conditionsUnit 05msV CCS 1S 2≤ 0.2VS 2control modeV CCS 2Symbol ParameterV V MaxTypLimits Min Test conditionsUnit µAV 20.2V CC (PD)V I (S1)V I (S2)I CC (PD)Power down supply voltage Chip select input S 1Chip select input S 2Power down supply current2.0~25°C ~40°C ~70°C-H1310V 0.6Vcc(PD)2.7V ≤Vcc(PD)Vcc(PD)<2.7V Note 7: On the power down mode by controlling S 1,the input level of S 2 must be S 2 ≥Vcc - 0.2V orS 2 ≤ 0.2V. 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