660_thumb

合集下载

第三章第二节thumb2指令集及汇编格式资料

第三章第二节thumb2指令集及汇编格式资料
该文件也包含了所有寄存器的声明
用户文件与库文件通过stm32f10x_lib.h建立关系,该文件中 定义了所有外设头文件的头文件,用于声明头文件,因此需 要include在用户的文件中
而文件stm32f10x_conf.h则指定具体的参数,用户可以对此 文件进行修改
外设的操作步骤
PPP代表任意外设 1. 在主应用文件中,声明一个结构
程序入口,而是作为主堆栈的标志 可以在设置中修改,但一般不做修改 9 .code16和code32 作为16位指令和32位指令开始的标志 等同于THUMB和ARM
10 END
END指示符告诉编译器已经到了源程序结尾。
语法格式:
END 使用说明:
每一个汇编源程序都包含END指示符,以告诉本源程 序的结束。
}
IAR的固件库
由ST公司开发,包括驱动程序和应用函数的 函数库
版本:3.4 优点:
入手快 便于开发,节约时间
缺点:
结构复杂繁琐 原理不够清晰
PPP:某一外设名称
说明
每一个外设都有一个对应的源文件: stm32f10x_ppp.c和一个对应的头文件: stm32f10x_ppp.h
硬件资源分配:
PC6----PC9分别连到4个LED,定义为 LED1~4
跑马灯实验
控制过程
点亮LED
相应管脚输出高电平 即相应管脚置1
管脚如何控制?
特殊寄e:GPIO控制
GPIO寄存器结构
GPIO寄存器结构,GPIO_TypeDef和AFIO_TypeDef,在文件
Example:GPIO控制
一、什么是GPIO?
GPIO,英文全称为General-Purpose IO ports,也就是通 用IO口。嵌入式系统中常常有数量众多,但是结构却比较 简单的外部设备/电路,对这些设备/电路有的需要CPU为 之提供控制手段,有的则需要被CPU用作输入信号。而且, 许多这样的设备/电路只要求一位,即只要有开/关两种状 态就够了,比如灯亮与灭。对这些设备/电路的控制,使 用传统的串行口或并行口都不合适。所以在微控制器芯片 上一般都会提供一个“通用可编程IO接口”,即GPIO。

66164;66166;66167;66168;66169;中文规格书,Datasheet资料

66164;66166;66167;66168;66169;中文规格书,Datasheet资料

COMMON POINT GROUND
Per ANSI/ESD S6.1, Grounding section 4.1.1 “Every element to be grounded at an ESD protected station shall be connected to the same common point ground.” ESD Handbook ESD TR20.20 section 5.1.3 Basic Grounding Requirements “The first step in ensuring that everything in an EPA is at the same electrical potential is to ground all conductive components of the work area (worksurfaces, people, equipment, etc.) to the same electrical ground point. This point is called the common point ground. The next step in completing the ground circuit is to connect the common point ground to the equipment ground (third wire, green).”
General Grounding Guidelines
1. ANSI/ESD S20.20 requires that all conductors in an ESD protected area, including personnel, must be grounded. 2. The ESD ground must be tied directly to and at the same potential as the building or “green wire” equipment ground. 3. Per ANSI/ESD S20.20, the ESD control program can in no way replace or supercede any requirements for personnel safety. Ground fault circuit interrupters (GFCI) and other safety protection should be considered wherever personnel might come into contact with electrical sources. 4. All electrical outlets should be verified for proper wiring ­ configuration, resistance or impedance and GFCI function when the mat is installed and periodically thereafter.

x86 Assembly Language Reference Manual

x86 Assembly Language Reference Manual

x86Assembly Language ReferenceManual Sun Microsystems,Inc.4150Network CircleSanta Clara,CA95054U.S.A.Part No:817–5477–10January2005Copyright2005Sun Microsystems,Inc.4150Network Circle,Santa Clara,CA95054U.S.A.All rights reserved.This product or document is protected by copyright and distributed under licenses restricting its use,copying,distribution,and decompilation.No part of this product or document may be reproduced in any form by any means without prior written authorization of Sun and its licensors,if any. Third-party software,including font technology,is copyrighted and licensed from Sun suppliers.Parts of the product may be derived from Berkeley BSD systems,licensed from the University of California.UNIX is a registered trademark in the U.S. and other countries,exclusively licensed through X/Open Company,Ltd.Sun,Sun Microsystems,the Sun logo,,AnswerBook,AnswerBook2,and Solaris are trademarks or registered trademarks of Sun Microsystems,Inc.in the U.S.and other countries.The OPEN LOOK and Sun™Graphical User Interface was developed by Sun Microsystems,Inc.for its users and licensees.Sun acknowledges the pioneering efforts of Xerox in researching and developing the concept of visual or graphical user interfaces for the computer industry.Sun holds a non-exclusive license from Xerox to the Xerox Graphical User Interface,which license also covers Sun’s licensees who implement OPEN LOOK GUIs and otherwise comply with Sun’s written license agreements.ernment Rights–Commercial ernment users are subject to the Sun Microsystems,Inc.standard license agreement and applicable provisions of the FAR and its supplements.DOCUMENTATION IS PROVIDED“AS IS”AND ALL EXPRESS OR IMPLIED CONDITIONS,REPRESENTATIONS AND WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY,FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT,ARE DISCLAIMED,EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD TO BE LEGALLY INVALID.Copyright2005Sun Microsystems,Inc.4150Network Circle,Santa Clara,CA95054U.S.A.Tous droits réservés.Ce produit ou document est protégépar un copyright et distribuéavec des licences qui en restreignent l’utilisation,la copie,la distribution,et ladécompilation.Aucune partie de ce produit ou document ne peutêtre reproduite sous aucune forme,par quelque moyen que ce soit,sansl’autorisation préalable etécrite de Sun et de ses bailleurs de licence,s’il y en a.Le logiciel détenu par des tiers,et qui comprend la technologie relative aux polices de caractères,est protégépar un copyright et licenciépar des fournisseurs de Sun.Des parties de ce produit pourrontêtre dérivées du système Berkeley BSD licenciés par l’Universitéde Californie.UNIX est une marque déposée aux Etats-Unis et dans d’autres pays et licenciée exclusivement par X/Open Company,Ltd.Sun,Sun Microsystems,le logo Sun,,AnswerBook,AnswerBook2,et Solaris sont des marques de fabrique ou des marques déposées,de Sun Microsystems,Inc.aux Etats-Unis et dans d’autres pays.L’interface d’utilisation graphique OPEN LOOK et Sun™aétédéveloppée par Sun Microsystems,Inc.pour ses utilisateurs et licenciés.Sun reconnaît les efforts de pionniers de Xerox pour la recherche et le développement du concept des interfaces d’utilisation visuelle ou graphique pour l’industrie de l’informatique.Sun détient une licence non exclusive de Xerox sur l’interface d’utilisation graphique Xerox,cette licence couvrantégalement les licenciés de Sun qui mettent en place l’interface d’utilisation graphique OPEN LOOK et qui en outre se conforment aux licencesécrites de Sun. CETTE PUBLICATION EST FOURNIE“EN L’ETAT”ET AUCUNE GARANTIE,EXPRESSE OU IMPLICITE,N’EST ACCORDEE,Y COMPRIS DES GARANTIES CONCERNANT LA VALEUR MARCHANDE,L’APTITUDE DE LA PUBLICATION A REPONDRE A UNE UTILISATION PARTICULIERE,OU LE FAIT QU’ELLE NE SOIT PAS CONTREFAISANTE DE PRODUIT DE TIERS.CE DENI DE GARANTIE NES’APPLIQUERAIT PAS,DANS LA MESURE OU IL SERAIT TENU JURIDIQUEMENT NUL ET NON AVENU.040910@9495ContentsPreface71Overview of the Solaris x86Assembler11Assembler Overview11Syntax Differences Between x86Assemblers12Assembler Command Line122Solaris x86Assembly Language Syntax13Lexical Conventions13Statements13Tokens15Instructions,Operands,and Addressing17Instructions17Operands18Assembler Directives203Instruction Set Mapping25Instruction Overview25General-Purpose Instructions26Data Transfer Instructions26Binary Arithmetic Instructions30Decimal Arithmetic Instructions31Logical Instructions32Shift and Rotate Instructions32Bit and Byte Instructions333Control Transfer Instructions35String Instructions38I/O Instructions39Flag Control(EFLAG)Instructions40Segment Register Instructions41Miscellaneous Instructions41Floating-Point Instructions42Data Transfer Instructions(Floating Point)42Basic Arithmetic Instructions(Floating-Point)43Comparison Instructions(Floating-Point)45Transcendental Instructions(Floating-Point)46Load Constants(Floating-Point)Instructions47Control Instructions(Floating-Point)47SIMD State Management Instructions49MMX Instructions49Data Transfer Instructions(MMX)50Conversion Instructions(MMX)50Packed Arithmetic Instructions(MMX)51Comparison Instructions(MMX)52Logical Instructions(MMX)53Shift and Rotate Instructions(MMX)53State Management Instructions(MMX)54SSE Instructions54SIMD Single-Precision Floating-Point Instructions(SSE)55MXCSR State Management Instructions(SSE)6164–Bit SIMD Integer Instructions(SSE)61Miscellaneous Instructions(SSE)62SSE2Instructions63SSE2Packed and Scalar Double-Precision Floating-Point Instructions63SSE2Packed Single-Precision Floating-Point Instructions70SSE2128–Bit SIMD Integer Instructions70SSE2Miscellaneous Instructions72Operating System Support Instructions7364–Bit AMD Opteron Considerations75Index774x86Assembly Language Reference Manual•January2005TablesTABLE3–1Data Transfer Instructions26TABLE3–2Binary Arithmetic Instructions30TABLE3–3Decimal Arithmetic Instructions32TABLE3–4Logical Instructions32TABLE3–5Shift and Rotate Instructions33TABLE3–6Bit and Byte Instructions34TABLE3–7Control Transfer Instructions36TABLE3–8String Instructions38TABLE3–9I/O Instructions40TABLE3–10Flag Control Instructions40TABLE3–11Segment Register Instructions41TABLE3–12Miscellaneous Instructions42TABLE3–13Data Transfer Instructions(Floating-Point)42TABLE3–14Basic Arithmetic Instructions(Floating-Point)44TABLE3–15Comparison Instructions(Floating-Point)45TABLE3–16Transcendental Instructions(Floating-Point)46TABLE3–17Load Constants Instructions(Floating-Point)47TABLE3–18Control Instructions(Floating-Point)47TABLE3–19SIMD State Management Instructions49TABLE3–20Data Transfer Instructions(MMX)50TABLE3–21Conversion Instructions(MMX)50TABLE3–22Packed Arithmetic Instructions(MMX)51TABLE3–23Comparison Instructions(MMX)52TABLE3–24Logical Instructions(MMX)53TABLE3–25Shift and Rotate Instructions(MMX)53TABLE3–26State Management Instructions(MMX)54TABLE3–27Data Transfer Instructions(SSE)555TABLE3–28Packed Arithmetic Instructions(SSE)56TABLE3–29Comparison Instructions(SSE)58TABLE3–30Logical Instructions(SSE)59TABLE3–31Shuffle and Unpack Instructions(SSE)59TABLE3–32Conversion Instructions(SSE)60TABLE3–33MXCSR State Management Instructions(SSE)61TABLE3–3464–Bit SIMD Integer Instructions(SSE)61TABLE3–35Miscellaneous Instructions(SSE)62TABLE3–36SSE2Data Movement Instructions64TABLE3–37SSE2Packed Arithmetic Instructions65TABLE3–38SSE2Logical Instructions66TABLE3–39SSE2Compare Instructions67TABLE3–40SSE2Shuffle and Unpack Instructions67TABLE3–41SSE2Conversion Instructions68TABLE3–42SSE2Packed Single-Precision Floating-Point Instructions70TABLE3–43SSE2128–Bit SIMD Integer Instructions71TABLE3–44SSE2Miscellaneous Instructions72TABLE3–45Operating System Support Instructions736x86Assembly Language Reference Manual•January2005PrefaceThe x86Assembly Language Reference Manual documents the syntax of the Solaris™x86 assembly language.This manual is provided to help experienced programmers understand the assembly language output of Solaris compilers.This manual is neither an introductory book about assembly language programming nor a reference manual for the x86architecture.Note–In this document the term“x86”refers to64-bit and32-bit systems manufactured using processors compatible with the AMD64or Intel Xeon/Pentium product families.For supported systems,see the Solaris10Hardware Compatibility List.Who Should Use This BookThis manual is intended for experienced x86assembly language programmers who are familiar with the x86architecture.Before You Read This BookYou should have a thorough knowledge of assembly language programming in general and be familiar with the x86architecture in specific.You should be familiar with the ELF objectfile format.This manual assumes that you have the following documentation available for reference:I IA-32Intel Architecture Software Developer’s Manual(Intel Corporation,2004).Volume1:Basic Architecture.Volume2:Instruction Set Reference A-M.Volume3: Instruction Set Reference N-Z.Volume4:System Programming Guide.7I AMD64Architecture Programmer’s Manual(Advanced Micro Devices,2003).Volume1:Application Programming.Volume2:System Programming.Volume3:General-Purpose and System Instructions.Volume4:128-Bit Media Instructions.Volume5:64-Bit Media and x87Floating-Point Instructions.I Linker and Libraries GuideI Sun Studio9:C User’s GuideI Sun Studio9:Fortran User’s Guide and Fortran Programming GuideI Man pages for the as(1),ld(1),and dis(1)utilities.How This Book Is OrganizedChapter1provides an overview of the x86functionality supported by the Solaris x86assembler.Chapter2documents the syntax of the Solaris x86assembly language.Chapter3maps Solaris x86assembly language instruction mnemonics to the nativex86instruction set.Accessing Sun Documentation OnlineThe SM Web site enables you to access Sun technical documentationonline.You can browse the archive or search for a specific book title orsubject.The URL is .Ordering Sun DocumentationSun Microsystems offers select product documentation in print.For a list ofdocuments and how to order them,see“Buy printed documentation”at.8x86Assembly Language Reference Manual•January2005Typographic ConventionsThe following table describes the typographic changes that are used in this book. TABLE P–1Typographic ConventionsTypeface or Symbol Meaning ExampleAaBbCc123The names of commands,files,anddirectories,and onscreen computeroutput Edit your.loginfile.Use ls-a to list allfiles. machine_name%you have mail.AaBbCc123What you type,contrasted with onscreencomputer output machine_name%su Password:AaBbCc123Command-line placeholder:replace witha real name or value The command to remove afile is rmfilename.AaBbCc123Book titles,new terms,and terms to beemphasized Read Chapter6in the User’s Guide.Perform a patch analysis.Do not save thefile.[Note that some emphasized items appear bold online.]Shell Prompts in Command ExamplesThe following table shows the default system prompt and superuser prompt for theC shell,Bourne shell,and Korn shell.TABLE P–2Shell PromptsShell PromptC shell prompt machine_name%C shell superuser prompt machine_name#Bourne shell and Korn shell prompt$9TABLE P–2Shell Prompts(Continued)Shell PromptBourne shell and Korn shell superuser prompt#10x86Assembly Language Reference Manual•January2005CHAPTER1Overview of the Solaris x86AssemblerThis chapter provides a brief overview of the Solaris x86assembler as.This chapterdiscusses the following topics:I“Assembler Overview”on page11I“Syntax Differences Between x86Assemblers”on page12I“Assembler Command Line”on page12Assembler OverviewThe Solaris x86assembler as translates Solaris x86assembly language into Executableand Linking Format(ELF)relocatable objectfiles that can be linked with other objectfiles to create an executablefile or a shared objectfile.(See Chapter7,“Object FileFormat,”in Linker and Libraries Guide,for a complete discussion of ELF objectfileformat.)The assembler supports macro processing by the C preprocessor(cpp)or them4macro processor.The assembler supports the instruction sets of the followingCPUs:Intel8086/8088processorsIntel286processorIntel386processorIntel486processorIntel Pentium processorIntel Pentium Pro processorIntel Pentium II processorPentium II Xeon processorIntel Celeron processorIntel Pentium III processorPentium III Xeon processorAdvanced Micro Devices Athlon processor11Advanced Micro Devices Opteron processorSyntax Differences Between x86AssemblersThere is no standard assembly language for the x86architecture.Vendorimplementations of assemblers for the x86architecture instruction sets differ in syntaxand functionality.The syntax of the Solaris x86assembler is compatible with thesyntax of the assembler distributed with earlier releases of the UNIX operating system(this syntax is sometimes termed“AT&T syntax”).Developers familiar with otherassemblers derived from the original UNIX assemblers,such as the Free SoftwareFoundation’s gas,willfind the syntax of the Solaris x86assembler verystraightforward.However,the syntax of x86assemblers distributed by Intel and Microsoft(sometimestermed“Intel syntax”)differs significantly from the syntax of the Solaris x86assembler.These differences are most pronounced in the handling of instructionoperands:I The Solaris and Intel assemblers use the opposite order for source and destinationoperands.I The Solaris assembler specifies the size of memory operands by adding a suffix tothe instruction mnemonic,while the Intel assembler prefixes the memoryoperands.I The Solaris assembler prefixes immediate operands with a dollar sign($)(ASCII0x24),while the Intel assembler does not delimit immediate operands.See Chapter2for additional differences between x86assemblers.Assembler Command LineDuring the translation of higher-level languages such as C and Fortran,the compilersmight invoke as using the alias fbe(“Fortran back end”).You can invoke theassembler manually from the shell command line with either name,as or fbe.See theas(1)man page for the definitive discussion of command syntax and command lineoptions.12x86Assembly Language Reference Manual•January2005CHAPTER2Solaris x86Assembly Language SyntaxThis chapter documents the syntax of the Solaris x86assembly language.I“Lexical Conventions”on page13I“Instructions,Operands,and Addressing”on page17I“Assembler Directives”on page20Lexical ConventionsThis section discusses the lexical conventions of the Solaris x86assembly language.StatementsAn x86assembly language program consists of one or morefiles containing statements.A statement consists of tokens separated by whitespace and terminated by either anewline character(ASCII0x0A)or a semicolon(;)(ASCII0x3B).Whitespace consists ofspaces(ASCII0x20),tabs(ASCII0x09),and formfeeds(ASCII0x0B)that are notcontained in a string or comment.More than one statement can be placed on a singleinput line provided that each statement is terminated by a semicolon.A statement canconsist of a comment.Empty statements,consisting only of whitespace,are allowed.CommentsA comment can be appended to a statement.The comment consists of the slashcharacter(/)(ASCII0x2F)followed by the text of the comment.The comment isterminated by the newline that terminates the statement.13LabelsA label can be placed at the beginning of a statement.During assembly,the label isassigned the current value of the active location counter and serves as an instructionoperand.There are two types of lables:symbolic and numeric.Symbolic LabelsA symbolic label consists of an identifier(or symbol)followed by a colon(:)(ASCII0x3A).Symbolic labels must be defined only once.Symbolic labels have global scopeand appear in the objectfile’s symbol table.Symbolic labels with identifiers beginning with a period(.)(ASCII0x2E)areconsidered to have local scope and are not included in the objectfile’s symbol table.Numeric LabelsA numeric label consists of a single digit in the range zero(0)through nine(9)followedby a colon(:).Numeric labels are used only for local reference and are not included inthe objectfile’s symbol table.Numeric labels have limited scope and can be redefinedrepeatedly.When a numeric label is used as a reference(as an instruction operand,for example),the suffixes b(“backward”)or f(“forward”)should be added to the numeric label.Fornumeric label N,the reference N b refers to the nearest label N defined before thereference,and the reference N f refers to the nearest label N defined after the reference.The following example illustrates the use of numeric labels:1:/define numeric label"1"one:/define symbolic label"one"/...assembler code...jmp1f/jump to first numeric label"1"defined/after this instruction/(this reference is equivalent to label"two")jmp1b/jump to last numeric label"1"defined/before this instruction/(this reference is equivalent to label"one")1:/redefine label"1"two:/define symbolic label"two"jmp1b/jump to last numeric label"1"defined/before this instruction/(this reference is equivalent to label"two")14x86Assembly Language Reference Manual•January2005TokensThere arefive classes of tokens:I Identifiers(symbols)I KeywordsI Numerical constantsI String ConstantsI OperatorsIdentifiersAn identifier is an arbitrarily-long sequence of letters and digits.Thefirst character must be a letter;the underscore(_)(ASCII0x5F)and the period(.)(ASCII0x2E)are considered to be letters.Case is significant:uppercase and lowercase letters are different.KeywordsKeywords such as x86instruction mnemonics(“opcodes”)and assembler directives are reserved for the assembler and should not be used as identifiers.See Chapter3for a list of the Solaris x86mnemonics.See“Assembler Directives”on page20for the list of as assembler directives.Numerical ConstantsNumbers in the x86architecture can be integers orfloating point.Integers can be signed or unsigned,with signed integers represented in two’s complement representation. Floating-point numbers can be:single-precisionfloating-point;double-precisionfloating-point;and double-extended precisionfloating-point.Integer ConstantsIntegers can be expressed in several bases:I Decimal.Decimal integers begin with a non-zero digit followed by zero or moredecimal digits(0–9).I Binary.Binary integers begin with“0b”or“0B”followed by zero or more binarydigits(0,1).I Octal.Octal integers begin with zero(0)followed by zero or more octal digits(0–7).I Hexadecimal.Hexadecimal integers begin with“0x”or“0X”followed by one ormore hexadecimal digits(0–9,A–F).Hexadecimal digits can be either uppercase or lowercase.Chapter2•Solaris x86Assembly Language Syntax15Floating Point ConstantsFloating point constants have the following format:I Sign(optional)–either plus(+)or minus(–)I Integer(optional)–zero or more decimal digits(0–9)I Fraction(optional)–decimal point(.)followed by zero or more decimal digitsI Exponent(optional)–the letter“e”or“E”,followed by an optional sign(plus orminus),followed by one or more decimal digits(0–9)A validfloating point constant must have either an integer part or a fractional part.String ConstantsA string constant consists of a sequence of characters enclosed in double quotes(")(ASCII0x22).To include a double-quote character("),single-quote character(’),orbackslash character(\)within a string,precede the character with a backslash(\)(ASCII0x5C).A character can be expressed in a string as its ASCII value in octalpreceded by a backslash(for example,the letter“J”could be expressed as“\112”).Theassembler accepts the following escape sequences in strings:Escape Sequence Character Name ASCII Value(hex)\n newline0A\r carriage return0D\b backspace08\t horizontal tab09\f form feed0C\v vertical tab0BOperatorsThe assembler supports the following operators for use in expressions.Operators haveno assigned precedence.Expressions can be grouped in square brackets([])toestablish precedence.+Addition-Subtraction\*Multiplication\/Division&Bitwise logical AND16x86Assembly Language Reference Manual•January2005|Bitwise logical OR>>Shift right<<Shift left\%Remainder!Bitwise logical AND NOT^Bitwise logical XORNote–The asterisk(*),slash(/),and percent sign(%)characters are overloaded.When used as operators in an expression,these characters must be preceded by the backslash character(\).Instructions,Operands,and Addressing Instructions are operations performed by the CPU.Operands are entities operated upon by the instruction.Addresses are the locations in memory of specified data.InstructionsAn instruction is a statement that is executed at runtime.An x86instruction statement can consist of four parts:I Label(optional)I Instruction(required)I Operands(instruction specific)I Comment(optional)See“Statements”on page13for the description of labels and comments.The terms instruction and mnemonic are used interchangeably in this document to refer to the names of x86instructions.Although the term opcode is sometimes used as a synonym for instruction,this document reserves the term opcode for the hexadecimal representation of the instruction value.Chapter2•Solaris x86Assembly Language Syntax17For most instructions,the Solaris x86assembler mnemonics are the same as the Intelor AMD mnemonics.However,the Solaris x86mnemonics might appear to bedifferent because the Solaris mnemonics are suffixed with a one-character modifier thatspecifies the size of the instruction operands.That is,the Solaris assembler derives itsoperand type information from the instruction name and the suffix.If a mnemonic isspecified with no type suffix,the operand type defaults to long.Possible operandtypes and their instruction suffixes are:b Byte(8–bit)w Word(16–bit)l Long(32–bit)(default)q Quadword(64–bit)The assembler recognizes the following suffixes for x87floating-point instructions:[no suffix]Instruction operands are registers onlyl(“long”)Instruction operands are64–bits(“short”)Instruction operands are32–bitSee Chapter3for a mapping between Solaris x86assembly language mnemonics andthe equivalent Intel or AMD mnemonics.OperandsAn x86instruction can have zero to three operands.Operands are separated bycommas(,)(ASCII0x2C).For instructions with two operands,thefirst(lefthand)operand is the source operand,and the second(righthand)operand is the destinationoperand(that is,source→destination).Note–The Intel assembler uses the opposite order(destination←source)for operands.Operands can be immediate(that is,constant expressions that evaluate to an inlinevalue),register(a value in the processor number registers),or memory(a value stored inmemory).An indirect operand contains the address of the actual operand value.Indirect operands are specified by prefixing the operand with an asterisk(*)(ASCII0x2A).Only jump and call instructions can use indirect operands.I Immediate operands are prefixed with a dollar sign($)(ASCII0x24)I Register names are prefixed with a percent sign(%)(ASCII0x25)18x86Assembly Language Reference Manual•January2005I Memory operands are specified either by the name of a variable or by a register thatcontains the address of a variable.A variable name implies the address of avariable and instructs the computer to reference the contents of memory at that address.Memory references have the following syntax:segment:offset(base,index,scale).I Segment is any of the x86architecture segment registers.Segment is optional:ifspecified,it must be separated from offset by a colon(:).If segment is omitted,the value of%ds(the default segment register)is assumed.I Offset is the displacement from segment of the desired memory value.Offset isoptional.I Base and index can be any of the general32–bit number registers.I Scale is a factor by which index is to be multipled before being added to base tospecify the address of the operand.Scale can have the value of1,2,4,or8.Ifscale is not specified,the default value is1.Some examples of memory addresses are:movl var,%eaxMove the contents of memory location var into number register%eax.movl%cs:var,%eaxMove the contents of memory location var in the code segment(register%cs)into number register%eax.movl$var,%eaxMove the address of var into number register%eax.movl array_base(%esi),%eaxAdd the address of memory location array_base to the contents of numberregister%esi to determine an address in memory.Move the contents of thisaddress into number register%eax.movl(%ebx,%esi,4),%eaxMultiply the contents of number register%esi by4and add the result to thecontents of number register%ebx to produce a memory reference.Move thecontents of this memory location into number register%eax.movl struct_base(%ebx,%esi,4),%eaxMultiply the contents of number register%esi by4,add the result to thecontents of number register%ebx,and add the result to the address ofstruct_base to produce an address.Move the contents of this address intonumber register%eax.Chapter2•Solaris x86Assembly Language Syntax19Assembler DirectivesDirectives are commands that are part of the assembler syntax but are not related to thex86processor instruction set.All assembler directives begin with a period(.)(ASCII0x2E)..align integer,padThe.align directive causes the next data generated to be aligned modulo integerbytes.Integer must be a positive integer expression and must be a power of2.Ifspecified,pad is an integer bye value used for padding.The default value of pad forthe text section is0x90(nop);for other sections,the default value of pad is zero(0)..ascii"string"The.ascii directive places the characters in string into the object module at thecurrent location but does not terminate the string with a null byte(\0).String mustbe enclosed in double quotes(")(ASCII0x22).The.ascii directive is not valid forthe.bss section..bcd integerThe.bcd directive generates a packed decimal(80-bit)value into the currentsection.The.bcd directive is not valid for the.bss section..bssThe.bss directive changes the current section to.bss..bss symbol,integerDefine symbol in the.bss section and add integer bytes to the value of the locationcounter for.bss.When issued with arguments,the.bss directive does notchange the current section to.bss.Integer must be positive..byte byte1,byte2,...,byteNThe.byte directive generates initialized bytes into the current section.The.bytedirective is not valid for the.bss section.Each byte must be an8-bit value..2byte expression1,expression2,...,expressionNRefer to the description of the.value directive..4byte expression1,expression2,...,expressionNRefer to the description of the.long directive..8byte expression1,expression2,...,expressionNRefer to the description of the.quad directive..comm name,size,alignmentm directive allocates storage in the data section.The storage is referencedby the identifier name.Size is measured in bytes and must be a positive integer.Name cannot be predefined.Alignment is optional.If alignment is specified,theaddress of name is aligned to a multiple of alignment..dataThe.data directive changes the current section to.data.20x86Assembly Language Reference Manual•January2005。

aurora_64b66b_protocol_spec_sp011

aurora_64b66b_protocol_spec_sp011

aurora_64b66b_protocol_spec_sp011Aurora 64B/66B Protocol SpecificationSP011 (v1.2) July 23, 2010Xilinx is disclosing to you this Specification (hereinafter "the Specification") for use in the development of designs in connection with semiconductor devices. Xilinx expressly disclaims any liability arising out of your use of the Specification. Xilinx does not convey any license under its patents, copyrights, or any rights of others in connection with the Specification. Y ou are responsible for obtaining any rights you may require for your use or implementation of the Specification. Xilinx reserves the right to make changes, at any time, to the Specification without notice and at the sole discretion of Xilinx. Xilinx assumes no obligation to correct any errors contained in the Specification or to advise you of any corrections or updates. Xilinx expressly disclaims any liability in connection with technical support or assistance that may be provided to you in connection with the Specification.THE SPECIFICA TION IS DISCLOSED TO YOU "AS-IS" WITH NO WARRANTY OF ANY KIND. YOU BEAR THE ENTIRE RISK AS TO ITS IMPLEMENTA TION AND USE. YOU ACKNOWLEDGE AND AGREE THA T YOU HAVE NOT RELIED ON ANY ORAL OR WRITTEN INFORMATION OR ADVICE, WHETHER GIVEN BY XILINX, ITS EMPLOYEES OR CONTRACTORS. XILINX MAKES NO OTHER WARRANTIES, WHETHER EXPRESS, IMPLIED, OR STA TUTORY, REGARDING THE SPECIFICATION, INCLUDING ANY WARRANTIES OF MERCHANTABILITY, FITNESS FOR A P ARTICULAR PURPOSE, OR NONINFRINGEMENT OF THIRD-PARTY RIGHTS.IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL, INDIRECT, EXEMPLARY, SPECIAL, OR INCIDENTAL DAMAGES, INCLUDING ANY LOSS OF DA TA OR LOST PROFITS, ARISING FROM OR RELATING TO YOUR USE OF THE SPECIFICA TION, EVEN IF YOU HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.2008, 2010 Xilinx, Inc. All rights reserved.XILINX, the Xilinx logo, the Brand Window, and other designated brands included herein are trademarks of Xilinx, Inc. All other trademarks are the property of their respective owners.Revision HistoryThe following table shows the revision history for this document.Date Version Revision03/31/08 1.0Initial Xilinx release.09/19/08 1.1Minor typographical edits. Changed block codes to blocks. Removed Not Ready blocks from Simplex in Table4-1, page36. Clarified simplex Aurora channel bonding inSection4.2.2“Channel Bonding,” page36. Added Appendix1, “References.”07/23/10 1.2Updated Section1.2“Scope” and Section8.1“Overview.”Deleted Sections 8.4 Transmitter Specifications, 8.5 Receiver Specifications, and 8.6Receiver Eye Diagrams.Table of ContentsSchedule of Figures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Schedule of Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Preface: About This SpecificationSpecification Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Typographical. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12Online Document. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12State Diagram Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Section1: Introduction and Overview1.1:Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.2:Scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.3:Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Section2: Data Transmission and Reception2.1:Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.2:Block Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.3:Frame Transmission Procedure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.3.1:Link-Layer Frame Delineation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242.3.2:64B/66B Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242.3.3:Serialization and Clock Encoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.3.4:Multi-Lane Transmission. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242.4:Frame Reception Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.4.1:Deserialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.4.2:64B/66B Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.4.3:Control Block Stripping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262.4.4:Multi-Lane Reception. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262.5:Data and Separator Block Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Section3: Flow Control3.1:Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.2:Native Flow Control Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293.3:Native Flow Control Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.4:Native Flow Control Block Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303.5:User Flow Control Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.6:User Flow Control Message Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31Section4: Initialization and Error Handling4.1:Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.2:Aurora Channel Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344.2.1:Lane Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344.2.2:Channel Bonding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.2.3:Wait For Remote . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374.3:Error Handling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384.4:CRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Section5: PCS Layer5.1:Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395.2:Aurora Encoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395.2.1:Block Codes in 64B/66B. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395.2.2:Idle/Not Ready/Clock Compensation/Channel Bonding Block Code. . . . . . 405.2.3:Native Flow Control Block Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425.2.4:Data Block Code for Frame Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425.2.5:Separator Block Code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425.2.6:Separator-7 Block Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435.2.7:User Flow Control Block Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435.2.8:Data Block Code for User Flow Control Message . . . . . . . . . . . . . . . . . . . . . . . . 445.2.9:User K-Block Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445.3:64B/66B Scrambling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455.4:64B/66B Gearbox . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455.5:Channel Bonding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455.6:Clock Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Section6: Channel Control6.1:Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476.2:Idle Block Striping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476.2.1:Not Ready Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476.2.2:Idle Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476.2.3:Clock Compensation Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476.2.4:Channel Bonding Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476.3:Native Flow Control Striping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476.4:Frame Data Striping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486.5:Strict-Alignment Frame Data Striping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486.6:User Flow Control Striping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486.7:Strict-Alignment User Flow Control Striping . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486.8:User K-Block Striping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Section7: PMA Layer7.1:Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497.2:Bit and Byte Ordering Convention. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497.3:Serialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49Section8: Electrical Specifications8.1:Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518.2:Signal Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518.3:Equalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Appendix1: ReferencesSchedule of FiguresPreface: About This SpecificationFigure P-1:Properties of Literals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Figure P-2:State Machine Diagram Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15Section1: Introduction and OverviewFigure 1-1:Aurora Protocol Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18Figure 1-2:A Simplex Connection Between a Pair of Aurora Lanes . . . . . . . . . . . . . . . . . 18Figure 1-3:A Single-Lane, Simplex Aurora Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19Figure 1-4:A Multi-Lane, Simplex Aurora Channel. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19Figure 1-5:A Single-Lane, Full-Duplex Aurora Channel. . . . . . . . . . . . . . . . . . . . . . . . . . . 20Figure 1-6:A Multi-Lane, Full-Duplex Aurora Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . 20Section2: Data Transmission and ReceptionFigure 2-1:Mapping Frames to Encoded Block Codes for Transmission. . . . . . . . . . . . . 23Figure 2-2:Receiving Data from an Aurora Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25Figure 2-3:Data Block Used for Frame Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26Figure 2-4:Separator Block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26Figure 2-5:Separator-7 Block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27Figure 2-6:Example of Frame Data Transfer through a Single-Lane Channel . . . . . . . . 27Figure 2-7:Example of Frame Data Transfer through a Multi-Lane Channel . . . . . . . . . 27Section3: Flow ControlFigure 3-1:NFC Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30Figure 3-2:UFC Block with UFC Header. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31Figure 3-3:Data Block Used to Carry UFC Message Data . . . . . . . . . . . . . . . . . . . . . . . . . . 31Figure 3-4:Example UFC Messages for Single-Lane Channel . . . . . . . . . . . . . . . . . . . . . . 31Figure 3-5:Example UFC Messages for a Multi-Lane Channel. . . . . . . . . . . . . . . . . . . . . . 32Section4: Initialization and Error HandlingFigure 4-1:Initialization Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34Figure 4-2:Block Sync State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35Section5: PCS LayerFigure 5-1:Idle/Not Ready/NFC Block Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41Figure 5-2:Native Flow Control Block Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42Figure 5-3:Data Block Code Carrying Frame Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42Figure 5-4:Separator Block Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42Figure 5-5:Separator-7 Block Code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43Figure 5-6:User Flow Control Block Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Figure 5-7:Data Block Code Carrying User Flow Control Message Data. . . . . . . . . . . . . 44 Figure 5-8:User K-Block Code Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44Section6: Channel ControlSection7: PMA LayerFigure 7-1:Serialization Order for Aurora 64B/66B Block Codes. . . . . . . . . . . . . . . . . . . . 49Section8: Electrical SpecificationsFigure 8-1:Differential Peak-To-Peak Voltage of Transmitter or Receiver. . . . . . . . . . . 51Appendix1: ReferencesSchedule of TablesPreface: About This SpecificationTable P-1:Radix Specifics of Literals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Table P-2:Examples of Extended Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Section1: Introduction and OverviewSection2: Data Transmission and ReceptionTable 2-1:Aurora 64B/66B Blocks Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21Table 2-2:Normal Aurora 64B/66B Block Transmission Priority . . . . . . . . . . . . . . . . . . . . 22Table 2-3:Aurora 64B/66B Block Transmission Priority during Flow Control Countdown 23 Section3: Flow Control Section4: Initialization and Error HandlingTable 4-1:Required Block Transmission during Lane Initialization. . . . . . . . . . . . . . . . . 36Table 4-2:Required State Transition after Lane Initialization . . . . . . . . . . . . . . . . . . . . . . 36Table 4-3:Required State Transition after Successful Channel Bonding. . . . . . . . . . . . . 37Section5: PCS LayerTable 5-1:Valid Block Type Field Values in Aurora 64B/66B. . . . . . . . . . . . . . . . . . . . . . . 40Table 5-2:Valid Octet Count Field Values for Separator Block Code. . . . . . . . . . . . . . . . 43Table 5-3:Valid Block Type Field Values for User K-Blocks . . . . . . . . . . . . . . . . . . . . . . . 44 Section6: Channel Control Section7: PMA LayerSection8: Electrical SpecificationsAppendix1: ReferencesPreface About This SpecificationThis specification describes the Aurora 64B/66B protocol. Aurora is a lightweight link-layer protocol that can be used to move data point-to-point across one or more high-speed serial lanes. Aurora 64B/66B is a version of the protocol using 64B/66B encoding instead of 8B/10B.Specification ContentsThis manual contains the following:Section1, “Introduction and Overview”provides an overview of the Aurora 64B/66B protocol.Section2, “Data Transmission and Reception”describes the procedures for transmitting and receiving data using an Aurora 64B/66B Channel.Section3, “Flow Control”describes the optional flow control features in the Aurora64B/66B protocol.Section4, “Initialization and Error Handling”describes the procedure used to preparean Aurora channel for operation.Section5, “PCS Layer”specifies the functions performed in the physical coding sub-layer (PCS) of the Aurora 64B/66B protocol.Section6, “Channel Control”defines the striping rules for using multi-lane channels. Section7, “PMA Layer”specifies the functions performed in the PMA layer of the Aurora 64B/66B Protocol.Section8, “Electrical Specifications”describes the AC specifications, covering both single- and multi-lane implementations.ConventionsThis document uses the following conventions.T ypographicalThe following typographical conventions are used in this document:Online DocumentThe following conventions are used in this document:NumericalConventionMeaning or UseExampleItalic fontReferences to other manualsSee the Development System Reference Guide for more information.Emphasis in textIf a wire is drawn so that itoverlaps the pin of a symbol, the two nets are not connected.To emphasize a term the first time it is used The state machine uses one-hot encoding.REG[FIELD]Abbreviations or acronyms for registers are shown in uppercasetext. Specific bits, fields, or ranges appear in bracketsREG[11:14]ConventionMeaning or UseExampleBlue textCross-reference link to a location in the current document See the section “AdditionalResources” for details.Refer to “Title Formats” inSection 1 for details.Red textCross-reference link to a location in another document See Figure 2-5 in the Virtex-II Platform FPGA User Guide.Blue, underlined textHyperlink to a website (URL)Go to /doc/10fb3b7b1711cc7931b716ea.htmlfor the latest speed files.Convention Meaning or Usen A decimal value[n:m ]Used to express a numerical range from n to m x Unknown value zHigh impedanceValues of LiteralsLiterals are represented by specifying three of their properties as listed and shown in Figure P-1 and in Table P-1 and Table P-2:1.Width in bits 2.Radix (Base)3.ValueTable P-1 shows the Radix specifics:All values are extended with zero except those with x or z in the most significant place; they extend with x or z respectively. A list of examples is shown in Table P-2:Figure P-1:Properties of LiteralsTable P-1:Radix Specifics of LiteralsRadix SpecifierRadixb Binary d Decimal h Hexadecimal oOctalTable P-2:Examples of Extended ValuesNumber Value Comment8’b000000000An 8-bit binary number with value of zero. (Zero extended to get 8 bits.)8’bx xxxxxxxxAn 8-bit binary number with value unknown. (x extended to get 8 bits.)8’b1x 0000001x An 8-bit binary number with value of 2 or 3, depending on the value of x.8’b0x 0000000x An 8-bit binary number with value of 0 or 1, depending on the value of x.8’hx xxxxxxxx An 8-bit hexadecimal number with value unknown.(x extended to get 8 bits.)8’hzx zzzzxxxx An 8-bit hexadecimal number with the upper four bits not driven and the lower four bitsunknown.8’b100000001An 8-bit binary number with value of one.8’hz1zzzz0001An 8-bit hexadecimal number with the upper four bits not driven and the lower four bits having value of one.8’bx1xxxxxxx1An 8-bit binary number that is odd.8’bx0xxxxxxx0An 8-bit binary number that is even.State Diagram ConventionsThis section describes the conventions used in the state diagrams for this document. The numbered sections correspond to the call-outs shown in the state machine diagram in Figure P-2, page 15.States1. A state is represented by a rectangle.2.The name of the state is indicated in bold.State T ransitions3.State transition is indicated by an arrow annotated in italics.State Machine OutputsOutputs are shown in plain text. Outputs can be shown inside of state rectangles or can be part of the annotation associated with a transition arrow. If a signal is not listed in a state rectangle or on a transition arrow, its value at that time is 0 (not asserted). If a registered output does not appear in the state rectangle or transition arrow annotation, then its value is unchanged from the previous value.Output T ypesOutputs are divided into three classes as shown in the examples below.4.Asserting control signals:go = 1link reset = 15.Register initialization:XYZ Register = 78New Counter = 0xmit = /SP/ (an ordered set)6.Incrementing or decrementing a register:XYZ Register = XYZ Register + 1New Counter = New Counter – 68’hz zzzzzzzz An 8-bit hexadecimal number with value not driven. (z extended to get 8 bits.)8’h0z 0000zzzzAn 8-bit hexadecimal number with upper nibble specified and the lower not driven.11’d n n An 11-bit decimal number with value n .6’h n nA 6-bit hexadecimal number with value n .w’b101(101)A binary number with value 5 and an unknown width.Table P-2:Examples of Extended Values (Cont’d)Number Value CommentFigure P-2:State Machine Diagram ConventionsSection1 Introduction and Overview1.1IntroductionAurora is a lightweight link-layer protocol that can be used to move data point-to-pointacross one or more high-speed serial lanes. Aurora 64B/66B is a version of the protocolusing 64B/66B encoding instead of 8B/10B.1.2ScopeThe Aurora 64B/66B Protocol Specification defines the following:Electrical specifications: This includes signaling levels for an Aurora serial link.PMA layer: This includes specification for serialization bit ordering and byteordering.Physical coding sub-layer (PCS): This includes specification for data encoding anddecoding, data scrambling, the 64B/66B gearbox, clock compensation and channelbonding.Channel control: This includes specifications for multi-lane striping and forscheduling the transmission of data and control information.Cyclic redundancy check (CRC): The Aurora protocol recommends a CRCmechanism compatible with the standard 64B/66B scrambling algorithm.1.3OverviewThe Aurora protocol (Figure1-1, page18) describes the transfer of user data across anAurora channel, consisting of one or more Aurora lanes. Each Aurora lane is a serial dataconnection, either full-duplex or simplex. Devices communicating across the channel arecalled channel partners.Aurora interfaces allow user applications to transfer data through the Aurora channel. Theuser interface on each Aurora interface is not defined in this specification and can bedecided independently for each implementation of the protocol.Aurora channels have the following properties:Data is transferred through the Aurora channel in frames.Frames share the channel with control information such as flow control messages,clock compensation sequences and idles.Frames can be of any length, and can have any format. Only the delineation of framesis defined in this specification.Frames in Aurora do not have to be contiguous — they can be interrupted at any time by flow control messages or idles.There is no gap required between frames in Aurora.Figure 1-1:Aurora Protocol OverviewFigure1-2 shows a simplex connection between a pair of Aurora lanes, depicting the functional blocks comprising the PCS and PMA layers of an Aurora connection. These blocks are specified in detail in this document.Figure 1-2: A Simplex Connection Between a Pair of Aurora LanesAurora interfaces allow applications to communicate using Aurora channels. Aurora interfaces are made up of one or more Aurora lanes, either simplex or full-duplex. The four possible configurations of Aurora interfaces are shown in Figure1-3, Figure1-4,Figure1-5, page20, and Figure1-6, page20.Figure1-3 shows a single-lane, simplex Aurora interface transmitting to another single-lane, simplex Aurora interface. In this configuration, each interface uses a single lane to transmit or receive from the Aurora channel. Channel control in each interface initializes the channel passing control to the user application.Figure 1-3: A Single-Lane, Simplex Aurora ChannelFigure1-4 shows a multi-lane, simplex Aurora interface transmitting to another multi-lane, simplex Aurora interface. In multi-lane configurations, the channel control bonds the lanes to eliminate skew between channels as a part of the channel initialization procedure. During normal operation, the channel control logic distributes data and control information across all the lanes in the channel.Figure 1-4: A Multi-Lane, Simplex Aurora Channel。

CompactPCI+a+Specification标准

CompactPCI+a+Specification标准

P r o p e r t y o f M o t o r o l a F orI nternalUseO nl y-Ext ernalD is tr ibutionPr ohibi te d PICMG 2.0 R3.0 CompactPCI® Specification October 1, 1999P r o p e r t y o f M o t o r o l aF o r I n t e r n a l U s e O n l y - E x t e r n a l D i s t r i b u t i o n P r o h i b i t e dP r o p e r t y o f M o t o r o l aF orI nternalUseO nl y-Ext ernalD is tr ibutionPr ohibi te dRelease Note for PICMG 2.0 Revision 3.0 CompactPCI ® Specification October 1, 1999P r o p e r t y o f M o t o r o l aF orI nternalUseO nl y-Ext ernalD is tr ibutionPr ohibi te d Purpose This Release Note records some issues raised in the course of developing and balloting PICMG 2.0 Revision 3.0, the CompactPCI core specification. 1. System Management Bus pin assignments . This specification reserves pins on J1/P1 of all slots and J2/P2 of the System Slot for definition as I 2C System Management Busses by PICMG 2.9, CompactPCI System Management Specification. These signals have been tentatively assigned by the PICMG 2.9 as indicated in Section 3.2.7.7 and in Tables 13 through 16 with their notes. The IPMB_SDA pin is an I2C data bus connecting all slots in a backplane. The IPMB_SCL pin is the clock associated with that data line, and the IPMB_PWR pin is a power pin for the IPMB node. The data and clock pins providing System Slot access to platform devices from J2/P2 were designated ICMB_SDA and ICMB_SCL in the draft specification reviewed and adopted by the Executive Membership on October 1, 1999. These signal names are misleading, implying the use of an RS-485 UART bus as specified in the Intel IPMI documents. These signals are designated SMB_SDA and SMB_SCL in the released document. A second System Management power pin, designated ICMB_PWR in the executive draft, was also reserved on J2/P2 of the System Slot. As of the approval of PICMG 2.0 Revision 3.0, the PICMG 2.9 subcommittee is in doubt as to whether this pin will actually be used for power, and is considering assigning a different function to this reserved pin. The released specification accord designates this pin as SMB_RSV. 2. System Slot Hot Swap Signals . This specification designates Pin J1/P1 D15 as a short BD_SEL# (Board Select) signal in agreement with PICMG 2.1, CompactPCI Hot Swap Specification, but only on peripheral slots. The pin is shown as a ground on System Slots. Implementers of CompactPCI boards and systems should anticipate that this signal may also be designated as BD_SEL# on System Slots in PICMG 2.13, CompactPCI Redundant System Slot Specification. J1/P1 Pin B4 is designated as the HEALTHY# signal on System and Peripheral Slots in this specification. ###P r o p e r t y o f M o t o r o l a F orI nternalUseO nl y-Ext ernalD is tr ibutionPr ohibi te d PICMG 2.0 R3.0CompactPCI® SpecificationOctober 1, 1999P r o p e r t y o f M o t o r o l aF orI nternalUseO nl y-Ext ernalD is tr ibutionPr ohibi te d PICMG 2.0 R3.0 10/1/99ii ©Copyright 1995, 1996, 1997, 1998, 1999 PCI Industrial Computers Manufacturers Group (PICMG).The attention of adopters is directed to the possibility that compliance with or adoption of PICMG ® specifications may require use of an invention covered by patent rights.PICMG ® shall not be responsible for identifying patents for which a license may be required by any PICMG ® specification, or for conducting legal inquiries into the legal validity or scope of those patents that are brought to its attention. PICMG ® specifications are prospective and advisory only. Prospective users are responsible for protecting themselves against liability for infringement of patents.NOTICE:The information contained in this document is subject to change without notice. The material in this document details a PICMG ® specification in accordance with the license and notices set forth on this page. This document does not represent a commitment to implement any portion of this specification in any company's products.WHILE THE INFORMATION IN THIS PUBLICATION IS BELIEVED TO BE ACCURATE, PICMG ® MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL INCLUDING, BUT NOT LIMITED TO ANY WARRANTY OF TITLE OR OWNERSHIP, IMPLIED WARRANTY OF MERCHANTABILITY OR WARRANTY OF FITNESS FOR PARTICULAR PURPOSE OR USE.In no event shall PICMG ® be liable for errors contained herein or for indirect, incidental,special, consequential, reliance or cover damages, including loss of profits, revenue, data or use, incurred by any user or any third pliance with this specification does not absolve manufacturers of CompactPCI equipment, from the requirements of safety and regulatory agencies (UL, CSA, FCC,IEC, etc.).PICMG ®, CompactPCI ®, and the PICMG ® and CompactPCI ® logos are registered trademarks of the PCI Industrial Computers Manufacturers Group.All other brand or product names may be trademarks or registered trademarks of their respective holders.P r o p e r t y o f M o t o r o l aF orI nternalUseO nl y-Ext ernalD is tr ibutionPr ohibi te d CompactPCI ® Core Specification PICMG 2.0 R3.0 10/1/99iii Contents1OVERVIEW.........................................................................................................................................91.1C OMPACT PCI O BJECTIVES ................................................................................................................91.2B ACKGROUND AND T ERMINOLOGY ....................................................................................................91.3D ESIRED A UDIENCE ...........................................................................................................................91.4C OMPACT PCI F EATURES .................................................................................................................101.5A PPLICABLE D OCUMENTS ................................................................................................................101.6A DMINISTRATION .............................................................................................................................111.7N AME A ND L OGO U SAGE .................................................................................................................112FEATURE SET..................................................................................................................................132.1F ORM F ACTOR .................................................................................................................................132.2C ONNECTOR .....................................................................................................................................152.3M ODULARITY ...................................................................................................................................162.4H OT S WAP C APABILITY ....................................................................................................................163ELECTRICAL REQUIREMENTS..................................................................................................173.1B OARD D ESIGN R ULES .....................................................................................................................173.1.1Decoupling Requirements......................................................................................................173.1.2CompactPCI Signal Additions...............................................................................................183.1.3CompactPCI Stub Termination..............................................................................................183.1.4Peripheral Board Signal Stub Length ...................................................................................183.1.5Characteristic Impedance......................................................................................................193.1.6System Slot Board Signal Stub Length ..................................................................................193.1.7Peripheral Board PCI Clock Signal Length..........................................................................193.1.8Pull-Up Location...................................................................................................................193.1.9Board Connector Shield Requirements.................................................................................203.2B ACKPLANE D ESIGN R ULES .............................................................................................................213.2.1Characteristic Impedance......................................................................................................213.2.2Eight-Slot Backplane Termination........................................................................................213.2.3Signaling Environment..........................................................................................................223.2.4IDSEL Assignment.................................................................................................................223.2.5REQ#/GNT# Assignment.......................................................................................................233.2.6PCI Interrupt Binding............................................................................................................243.2.7CompactPCI Signal Additions...............................................................................................253.2.8Power Distribution................................................................................................................283.2.9Power Decoupling.................................................................................................................293.2.10Healthy (Healthy#)................................................................................................................303.333 MH Z PCI C LOCK D ISTRIBUTION .................................................................................................303.3.1Backplane Clock Routing Design Rules................................................................................313.3.2System Slot Board Clock Routing Design Rules....................................................................313.464-B IT D ESIGN R ULES ......................................................................................................................313.566 MH Z E LECTRICAL R EQUIREMENTS .............................................................................................333.5.166 MHz Board Design Rules.................................................................................................333.5.266 MHz System Board Design Rules.....................................................................................343.5.366MHz Backplane Design Rules...........................................................................................343.5.466MHz PCI Clock Distribution.............................................................................................343.5.566 MHz System Slot Board Clock Routing Design Rules (35)3.5.666 MHz Hot Swap (35)3.6S YSTEM AND B OARD G ROUNDING (36)3.6.1Board Front Panel Grounding Requirements (36)3.6.2Backplane Grounding Requirements (36)3.7C OMPACT PCI B UFFER M ODELS (36)P r o p e r t y o f M o t o r o l aF orI nternalUseO nl y-Ext ernalD is tr ibutionPr ohibi te d PICMG 2.0 R3.0 10/1/99iv 4MECHANICAL REQUIREMENTS................................................................................................374.1B OARD R EQUIREMENTS ...................................................................................................................374.1.13U Boards..............................................................................................................................374.1.26U Boards..............................................................................................................................374.1.3Rear-panel I/O Boards..........................................................................................................374.1.4ESD Discharge Strip.............................................................................................................384.1.5ESD Clip................................................................................................................................384.1.6Cross Sectional View.............................................................................................................394.1.7Component Outline and Warpage.........................................................................................394.1.8Solder Side Cover..................................................................................................................394.1.9Front Panels..........................................................................................................................484.1.10System Slot Identification......................................................................................................494.2R EAR -P ANEL I/O B OARD R EQUIREMENTS .......................................................................................524.2.1Mechanicals...........................................................................................................................524.2.2Power.....................................................................................................................................524.2.3Rear Panel Keying.................................................................................................................534.3B ACKPLANE R EQUIREMENTS ...........................................................................................................534.3.1Connector Orientation...........................................................................................................534.3.2Slot Spacing...........................................................................................................................534.3.3Slot Designation....................................................................................................................544.3.4Bus Segments.........................................................................................................................544.3.5Backplane Dimensions..........................................................................................................545CONNECTOR IMPLEMENTATION.............................................................................................585.1O VERVIEW .......................................................................................................................................585.1.1Location.................................................................................................................................585.1.2Housing Types.......................................................................................................................595.1.3Connector Tail Lengths.........................................................................................................595.1.4Backplane / Board Population Options.................................................................................595.2J1 (32-B IT PCI S IGNALS ).................................................................................................................595.3J2 C ONNECTOR ................................................................................................................................605.3.1Peripheral Slot 64-Bit PCI....................................................................................................605.3.2Peripheral Slot Rear-Panel I/O.............................................................................................605.3.3System Slot 64-bit PCI...........................................................................................................605.3.4System Slot Rear-Panel I/O...................................................................................................605.4B USSED R ESERVED P INS ..................................................................................................................605.5N ON -B USSED R ESERVED P INS .........................................................................................................605.6P OWER P INS .....................................................................................................................................605.75V/3.3V PCI K EYING ......................................................................................................................615.8P IN A SSIGNMENTS PACTPCI BUFFER MODELS...............................................................................................69B.CONNECTOR IMPLEMENTATION.............................................................................................73B.1G ENERAL .........................................................................................................................................73B.2C ONNECTORS ...................................................................................................................................73B.3A LIGNMENT .....................................................................................................................................73B.3.1Front Plug-In Board Alignment............................................................................................73B.3.2Rear Panel I/O Board Alignment..........................................................................................74B.3.3Backward Compatibility for Rear Panel I/O Boards. (74)P r o p e r t y o f M o t o r o l aF orI nternalUseO nl y-Ext ernalD is tr ibutionPr ohibi te d CompactPCI ® Core Specification PICMG 2.0 R3.0 10/1/99v TablesT ABLE 1. C ODING K EY C OLOR A SSIGNMENTS ..............................................................................................15T ABLE 2. B OARD D ECOUPLING R EQUIREMENTS ...........................................................................................17T ABLE 3. S TUB T ERMINATION R ESISTOR ......................................................................................................18T ABLE 4. B OARD C HARACTERISTICS .............................................................................................................19T ABLE 5. P ULL -UP R ESISTOR V ALUES ...........................................................................................................20T ABLE 6. B ACKPLANE C HARACTERISTICS .....................................................................................................21T ABLE 7. S YSTEM TO L OGICAL S LOT S IGNAL A SSIGNMENTS ........................................................................23T ABLE 8. S YSTEM TO L OGICAL S LOT I NTERRUPT A SSIGNMENTS ..................................................................24T ABLE 9. P HYSICAL S LOT A DDRESSES ..........................................................................................................27T ABLE 10. P OWER S PECIFICATIONS ...............................................................................................................28T ABLE 11. B ACKPLANE D ECOUPLING R ECOMMENDATIONS ..........................................................................30T ABLE 12. C ODING K EY C OLOR A SSIGNMENTS AND P ART N UMBERS ...........................................................61T ABLE 13. C OMPACT PCI P ERIPHERAL S LOT 64-B IT C ONNECTOR P IN A SSIGNMENTS ...................................62T ABLE 14 C OMPACT PCI P ERIPHERAL S LOT R EAR -P ANEL I/O C ONNECTOR P IN A SSIGNMENTS ....................63T ABLE 15. C OMPACT PCI S YSTEM S LOT 64-BIT C ONNECTOR P IN A SSIGNMENT .............................................64T ABLE 16. C OMPACT PCI S YSTEM S LOT R EAR -P ANEL I/O C ONNECTOR P IN A SSIGNMENTS ..........................65T ABLE 17. R EVISION H ISTORY . (67)P r o p e r t y o f M o t o r o l a F o r I n t e r n a l U s e O n l y - E x t e r n a l D i s t r i b u t i o n P r o h i b i t e d PICMG 2.0 R3.0 10/1/99vi This page is left intentionally blank.P r o p e r t y o f M o t o r o l aF orI nternalUseO nl y-Ext ernalD is tr ibutionPr ohibi te d CompactPCI ® Core Specification PICMG 2.0 R3.0 10/1/99vii IllustrationsF IGURE 1. 3U 64-B IT C OMPACT PCI F ORM F ACTOR ......................................................................................13F IGURE 2. 3U C OMPACT PCI B ACKPLANE E XAMPLE .....................................................................................14F IGURE 3. PCI S IGNAL T ERMINATION ...........................................................................................................22F IGURE 4. L OCAL 64 B IT I NITIALIZATION ......................................................................................................33F IGURE 5. ESD C LIP L OCATION ....................................................................................................................39F IGURE 6. 3U B OARD ....................................................................................................................................40F IGURE 7. 6U B OARD ....................................................................................................................................41F IGURE 8. F RONT S IDE B OARD ESD D IMENSIONS .........................................................................................42F IGURE 9. 3U R EAR -P ANEL I/O B OARD D IMENSIONS ...................................................................................43F IGURE 10. 6U R EAR P ANEL I/O B OARD D IMENSIONS ..................................................................................44F IGURE 11. R EAR P ANEL I/O ESD D IMENSIONS ...........................................................................................45F IGURE 12. C ROSS S ECTIONAL B OARD , C ONNECTOR , B ACKPLANE AND F RONT P ANEL V IEW ......................46F IGURE 13. C OMPONENT O UTLINE ................................................................................................................47F IGURE 15. C OMPACT PCI C OMPATIBILITY G LYPHS ......................................................................................48F IGURE 16. C OMPACT PCI L OGO ...................................................................................................................48F IGURE 17. 3U EMC F RONT P ANEL ..............................................................................................................50F IGURE 18. 6U EMC F RONT P ANEL ..............................................................................................................51F IGURE 19. 3U B ACKPLANE E XAMPLE - F RONT V IEW ..................................................................................53F IGURE 20. 3U B ACKPLANE D IMENSIONS .....................................................................................................56F IGURE 21. 6U B ACKPLANE D IMENSIONS .....................................................................................................57F IGURE 22. 3U C ONNECTOR I MPLEMENTATION ............................................................................................58F IGURE 23. 6U C ONNECTOR I MPLEMENTATION ............................................................................................58F IGURE 24. 5V S TRONG PCI M ODEL ............................................................................................................69F IGURE 25. 5V W EAK PCI M ODEL ...............................................................................................................70F IGURE 26. 3.3V S TRONG PCI M ODEL .........................................................................................................70F IGURE 27. 3.3V W EAK PCI M ODEL (71)P r o p e r t y o f M o t o r o l aF orI nternalUseO nl y-Ext ernalD is tr ibutionPr ohibi te d PICMG 2.0 R3.0 10/1/99viii This page is left intentionally blank.P r o p e r t y o f M o t o r o l aF orI nternalUseO nl y-Ext ernalD is tr ibutionPr ohibi te d 1. Overview CompactPCI ® Core Specification PICMG 2.0 R3.0 10/1/99Page 9 of 741 Overview 1.1 CompactPCI Objectives CompactPCI is an adaptation of the Peripheral Component Interconnect (PCI)Specification 2.1 or later for industrial and/or embedded applications requiring a more robust mechanical form factor than desktop PCI. CompactPCI uses industry standard mechanical components and high performance connector technologies to provide an optimized system intended for rugged applications. CompactPCI provides a system that is electrically compatible with the PCI Specification, allowing low cost PCI components to be utilized in a mechanical form factor suited for rugged pactPCI is an open specification supported by the PICMG (PCI Industrial Co m-puter Manufacturers Group), which is a consortium of companies involved in utiliz-ing PCI for embedded applications. PICMG controls this specification.1.2 Background and Terminology Eurocard - A series of mechanical board form factor sizes for rack-based systems as used in VME, Multibus II, and other applications defined by the Institute of Electri-cal and Electronics Engineers (IEEE) and International Electrotechnical Committee (IEC).ISA - Industry Standard Architecture. A specification by which Personal Com puters (PCs) add boards.PCI - Peripheral Component Interconnect. A specification for defining a common in-terconnect between logic components. Typically used for interconnecting high-speed,PC-compatible chipset components. The PCI specification is issued through the PCI Special Interest Group (PCI SIG).This specification utilizes several key words, which are defined below:may : A key word indicating flexibility of choice with no implied preference.shall : A key word indicating a mandatory requirement. Designers shall im-plement such mandatory requirements to ensure interchangeability and to claim conformance with the specification.should: A key word indicating flexibility of choice with a strongly preferred implementation.1.3 Desired AudienceCompactPCI exists to provide a standard form factor for those applications requiring the high performance of PCI as well as the small size and ruggedness of a rack mount system. CompactPCI provides a mechanism for OEM and end users to di-rectly apply PCI components and technology to a new mechanical form factor while。

80C52

80C52

Rev. E (31/08/95)
MATRA MHS
Figure 2. Pin Configuration
80CT2EX P1.0/T2 NC VCC P0.0/A0 P0.1/A1 P0.2/A2 P0.3/A3
P1.5 P1.6 P1.7 RST RxD/P3.0
查询80C32-12D供应商
MATRA MHS
80C32/80C52
CMOS 0 to 44 MHz Single-chip 8 Bit Microcontroller
Description
MHS’s 80C52 and 80C32 are high performance CMOS versions of the 8052/8032 NMOS single chip 8 bit µC.
MHS’s 80C52 and 80C32 are also available at 16 MHz with 2.7 V < VCC < 5.5 V.
D 80C32 : Romless version of the 80C52 D 80C32/80C52-L16 : Low power version
The 80C32 is identical to the 80C52 except that it has no on-chip ROM. MHS’s 80C52/80C32 are manufactured using SCMOS process which allows them to run from 0 up to 44 MHz with Vcc = 5 V.
Vcc : 2.7 – 5.5 V Freq : 0-16 MHz D 80C32/80C52-12 : 0 to 12 MHz D 80C32/80C52-16 : 0 to 16 MHz D 80C32/80C52-20 : 0 to 20 MHz D 80C32/80C52-25 : 0 to 25 MHz D 80C32/80C52-30 : 0 to 30 MHz

Microchip最新选型指南

Microchip最新选型指南


Microchip: A Partner in Your Success
Microchip is a leading provider of microcontroller and analog semiconductors, providing low-risk product development, lower total system cost and faster time to market for thousands of diverse customer applications worldwide. Offering outstanding technical support along with dependable delivery and quality, Microchip serves over 63,000 customers in more than 65 countries who are designing high-volume embedded control applications in the consumer, automotive, office-automation, communications and industrial-control markets worldwide.
32-bit PIC® Microcontrollers
The PIC32 family adds more performance and more memory while maintaining pin, peripheral and software compatibility with Microchip’s 16-bit MCU/DSC families. The PIC32 family operates at up to 80 MHz and offers ample code and data space capabilities with up to 512 KB Flash and 128 KB RAM. For more information visit: /32bit

MK64FN1M0xxx12_flash.ld链接文件解析

MK64FN1M0xxx12_flash.ld链接文件解析

MK64FN1M0xxx12_flash.ld链接⽂件解析1.前⾔本⽂主要对MK64FN1M0xxx12_flash.ld⽂件进⾏分析,以此来加深对链接⽂件的理解2.⽂件详解/*** ###################################################################** Processors: MK64FN1M0CAJ12** MK64FN1M0VDC12** MK64FN1M0VLL12** MK64FN1M0VLQ12** MK64FN1M0VMD12**** Compiler: GNU C Compiler** Reference manual: K64P144M120SF5RM, Rev.2, January 2014** Version: rev. 2.9, 2016-03-21** Build: b170817**** Abstract:** Linker file for the GNU C Compiler**** Copyright 2016 Freescale Semiconductor, Inc.** Copyright 2016-2017 NXP** Redistribution and use in source and binary forms, with or without modification,** are permitted provided that the following conditions are met:**** 1. Redistributions of source code must retain the above copyright notice, this list** of conditions and the following disclaimer.**** 2. Redistributions in binary form must reproduce the above copyright notice, this** list of conditions and the following disclaimer in the documentation and/or** other materials provided with the distribution.**** 3. Neither the name of the copyright holder nor the names of its** contributors may be used to endorse or promote products derived from this** software without specific prior written permission.**** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.**** http: ** mail: support@**** ###################################################################*//* Entry Point */NOTE:程序中第⼀条运⾏的指令被称为⼊⼝点entry point,可以使⽤ENTRY链接脚本命令设置entry point,参数是⼀个符号名:有⼏种⽅法可以设置entry point,链接器会按照如下的顺序来try各种⽅法,只要任何⼀种⽅法成功则会停⽌:the ‘-e’ entry command-line option;the ENTRY(symbol) command in a linker script;the value of the symbol start, if defined;the address of the first byte of the ‘.text’ section, if present;The address 0ENTRY(Reset_Handler)/*DEFINED(symbol)⽤于判断symbol在符号表中是否有定义,如果有定义则返回1否则返回0*/HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; /* Specify the memory areas */ /*定义内存区域的起始地址和长度*/MEMORY{m_interrupts (RX) : ORIGIN = 0x00000000, LENGTH = 0x00000400m_flash_config (RX) : ORIGIN = 0x00000400, LENGTH = 0x00000010m_text (RX) : ORIGIN = 0x00000410, LENGTH = 0x000FFBF0m_data (RW) : ORIGIN = 0x1FFF0000, LENGTH = 0x00010000m_data_2 (RW) : ORIGIN = 0x20000000, LENGTH = 0x00030000}/* Define output sections */SECTIONS{/* The startup code goes first into internal flash */.interrupts :{. = ALIGN(4);/*isr_vector在start.S中定义:.section .isr_vector, "a",按照MEMORY命令说明,isr_vector由于没有指定输出section,因此会创建与输⼊section同名的输出section,且会按照isr_vector的属性放到合适的内存区域,此处KEEP是保证isr_vector的输出section不会被删除*/KEEP(*(.isr_vector)) /* Startup code */. = ALIGN(4);} > m_interrupts.flash_config :{. = ALIGN(4);KEEP(*(.FlashConfig)) /* Flash Configuration Field (FCF) */. = ALIGN(4);} > m_flash_config/* The program code and other data goes into internal flash */.text :{. = ALIGN(4);*(.text) /* .text sections (code) */*(.text*) /* .text* sections (code) */*(.rodata) /* .rodata sections (constants, strings, etc.) */*(.rodata*) /* .rodata* sections (constants, strings, etc.) */*(.glue_7) /* glue arm to thumb code */*(.glue_7t) /* glue thumb to arm code */*(.eh_frame)KEEP (*(.init))KEEP (*(.fini)). = ALIGN(4);} > m_text.ARM.extab :{*(.ARM.extab* .gnu.linkonce.armextab.*)} > m_text.ARM :{__exidx_start = .;*(.ARM.exidx*)__exidx_end = .;} > m_text.ctors :{__CTOR_LIST__ = .;/* gcc uses crtbegin.o to find the start ofthe constructors, so we make sure it isfirst. Because this is a wildcard, itdoesn't matter if the user does notactually link against crtbegin.o; thelinker won't look for a file to match awildcard. The wildcard also means that itdoesn't matter which directory crtbegin.ois in. */KEEP (*crtbegin.o(.ctors))KEEP (*crtbegin?.o(.ctors))/* We don't want to include the .ctor section fromfrom the crtend.o file until after the sorted ctors.The .ctor section from the crtend file contains theend of ctors marker and it must be last */KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))KEEP (*(SORT(.ctors.*)))KEEP (*(.ctors))__CTOR_END__ = .;} > m_text.dtors :{__DTOR_LIST__ = .;KEEP (*crtbegin.o(.dtors))KEEP (*crtbegin?.o(.dtors))KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))KEEP (*(SORT(.dtors.*)))KEEP (*(.dtors))__DTOR_END__ = .;} > m_text.preinit_array :{PROVIDE_HIDDEN (__preinit_array_start = .);KEEP (*(.preinit_array*))PROVIDE_HIDDEN (__preinit_array_end = .);} > m_text.init_array :{PROVIDE_HIDDEN (__init_array_start = .);KEEP (*(SORT(.init_array.*)))KEEP (*(.init_array*))PROVIDE_HIDDEN (__init_array_end = .);} > m_text.fini_array :{PROVIDE_HIDDEN (__fini_array_start = .);KEEP (*(SORT(.fini_array.*)))KEEP (*(.fini_array*))PROVIDE_HIDDEN (__fini_array_end = .);} > m_text__etext = .; /* define a global symbol at end of code */__DATA_ROM = .; /* Symbol is used by startup for data initialization */.data : AT(__DATA_ROM){. = ALIGN(4);__DATA_RAM = .;__data_start__ = .; /* create a global symbol at data start */*(.data) /* .data sections */*(.data*) /* .data* sections */KEEP(*(.jcr*)). = ALIGN(4);__data_end__ = .; /* define a global symbol at data end */} > m_data__DATA_END = __DATA_ROM + (__data_end__ - __data_start__);text_end = ORIGIN(m_text) + LENGTH(m_text);ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") /* Uninitialized data section */.bss :{/* This is used by the startup in order to initialize the .bss section */. = ALIGN(4);__START_BSS = .;__bss_start__ = .;*(.bss)*(.bss*)*(COMMON). = ALIGN(4);__bss_end__ = .;__END_BSS = .;} > m_data.heap :{. = ALIGN(8);__end__ = .;PROVIDE(end = .);__HeapBase = .;. += HEAP_SIZE;__HeapLimit = .;__heap_limit = .; /* Add for _sbrk */} > m_data_2.stack :{. = ALIGN(8);. += STACK_SIZE;} > m_data_2/* Initializes stack on the end of block */__StackTop = ORIGIN(m_data_2) + LENGTH(m_data_2);__StackLimit = __StackTop - STACK_SIZE;PROVIDE(__stack = __StackTop);.ARM.attributes 0 : { *(.ARM.attributes) }ASSERT(__StackLimit >= __HeapLimit, "region m_data_2 overflowed with stack and heap") }。

Neo_M660模块AT指令集_V2.1

Neo_M660模块AT指令集_V2.1

4
网络服务指令............................................................................................................................................... 18 4.1 4.2 4.3 信号强度:+CSQ................................................................................................................................... 18 网络选择:+COPS................................................................................................................................. 19 设置频段:+XBANDSEL......................................................................................................................... 20
移动设备控制和状态报告.............................................................................................................................. 9 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 模块状态查询:+CPAS............................................................................................................................ 9 网络注册状态查询:+CREG.................................................................................................................... 9 设置模块功能:+CFUN......................................................................................................................... 10 低功耗设置:+ ENPWRSAVE................................................................................................................. 11 时钟:+CCLK......................................................................................................................................... 11 设置模块波特率:+IPR......................................................................................................................... 12 输入 PIN 码:+CPIN.............................................................................................................................. 12 PIN 使能与查询功能指令:+CLCK........................................................................................................ 13 PIN 修改密码指令:+CPWD................................................................................................................. 14 奇偶校验:+ICF.................................................................................................................................... 15 扩展错误报告:+CEER.......................................................................................................................... 15 设置错误提示信息:+CMEE................................................................................................................. 16 设置信号灯闪烁状态:+SIGNAL........................................................................................................... 16 充电状态查询:+CHRSTATE.................................................................................................................. 17 充电电流设置:+CHRCURRENT............................................................................................................ 18

saej833美国假人尺寸标准

saej833美国假人尺寸标准

人体尺寸(修订本)——SAE J833发布:1962-06修订:1989-05 代替原J833 DEC831、适用范围 (2)2、引用标准 (2)2.1引用标准 (2)3、人体尺寸 (2)3.1概述 (2)3.2术语 (2)3.3尺寸 (2)3.4人体活动角度范围 (5)3.5尺寸变化 (5)4、说明 (6)4.1版本说明 (6)4.2坐姿状态 (6)4.3站立状态 (7)副表1 (9)副表2 (12)1、适用范围推荐本标准用于定义世界范围内的使用到的人体尺寸(使用在建筑、普通工业、农用拖拉机、林学以及SAE J1116 JUN86中对专门的采矿机械的分类方面)。

2、引用标准2.1 引用标准在相关最新的SAE标准公布之前,下列标准构成本标准特定的引用范围。

2.1.1 SAE标准SAEJ898OCT87——路外工程机械的位置控制SAEJ925DEC87——路外工程机械的最小通过尺寸SAEJ1116JUN86——路外自动机械的分类3、人体尺寸3.1概述在图1和图2上,分别给出了站立和坐姿的人体转动关节尺寸的较大、中间、较小值。

3.2术语3.2.1较小人体——指5%的女性,只有5%的女性的人体尺寸低于这个数值。

3.2.2中间人体——介于较大和较小人体尺寸的中间值。

3.2.3较大人体——指95%的男性,只有5%的男性的人体尺寸高于这个数值。

3.3尺寸图1和图2中的尺寸包含穿上鞋和轻便服装时的高度。

表1为穿上冬季厚重衣物时的尺寸增加量。

图1 坐姿图2 站姿表1 穿上厚重衣物的尺寸增加量3.4人体活动角度范围身体活动角度范围按SAE J898 OCT87标准规定。

3.5尺寸变化3.5.1人体自然变化3.5.1.1对于坐姿,较大人体可以降低90mm,较小人体可以降低50mm。

3.5.1.2对于站姿,任何尺寸的人体都可以降低30mm。

3.5.2不同人种之间的差别3.5.2.1非洲人种与本标准提供的人体相比,手臂长增加2%,腿长增加4%。

30_signal_and_power_integrity

30_signal_and_power_integrity

• Is every thing ok because the ambient “Functional Test” passed?
Purple - 3.3 V 0.5 V/div Note more noise as AD driven “High”
Green - D Gnd 0.5 V/div Note more noise as AD driven “Low” Yellow - AD 12 2 V/div
• Signal Integrity ensures signals are of sufficient quality to reliably transmit their required information, and do not cause problems to themselves or to other components in the system. • Signal Integrity applies to Digital, Analog and Power electronics • Signal Integrity issues are more common now because electronics are more dense and chips have faster rise times – Assuring Signal Integrity now involves more knowledge of such RF techniques as terminations, impedance matching • Major function of engineering, next to conceiving the correct design, is implementing the design correctly • Signal integrity assures the circuit design operates as intended and must be designed in. – Correct design relies on experience, best practices, analysis and simulation to ensure desired signal quality.

GEFRAN 600 CONTROLLER 产品说明书

GEFRAN 600 CONTROLLER 产品说明书

600 CONTROLLERMain applications •Extrusion lines•Injection presses for plastics •Heat punches•Presses for rubber •Packaging machines •Packing machines •Polymerization and synthetic fiber plants•Food processing pants•Die-casting plants•Cooling plants•Climatic cells and test benches •Dryers for ceramics and construction parts•Ovens•Painting plants Main features•Universal input configurable from faceplate •Accuracy better than 0.2% f.s. under nominal conditions•Control output: relay, logic, Triac , continuous, digital insulated•Hot/cold function with selection of cooling fluid• 3 alarms with completely configurable function•Analog retransmission output•Isolated digital input with configurable function•Auxiliary input for CT (TA) (50mAac)•Heater break or probe short-circuit alarm •Self-tuning, Auto-tuning, Soft-start, bumpless Man/Auto function•Double set, set ramp, timed output function •Optically isolated RS485 serial line. Protocol:GEFRAN CENCAL or MODBUS RTU •Self-diagnosis•Rapid configuration from PC with WinstrumpacketPROFILEMicroprocessor controller, format 48x48(1/16 DIN) manufactured using SMT. Provides a complete operator interface protected by a Lexan membrane that ensures level IP65 faceplate protection.It has 4 keys, two green LED displays, each with 4 digits, 4 red signal LED's for the 4 logic or relay outputs, and 3 other programmable LED's to signal the various operational states of the instrument.The main input for process variable is universal, and many types of signals can be connected: thermocouples, resistance thermometers, thermistors, normalized linear inputs, all with possibility of custom linearization using the faceplate keys.The type of input is selected from the faceplate keys; no external shunts are required.A second auxiliary analog input from the current transformer is also available.With the isolated digital input you can select: one of the two presettable setpoints, select Manual-Automatic mode, reset the alarms memory, or enable the hold function. The instrument can have up to 4 outputs: relay (5A at 250Vac/30Vdc cosϕ= 1), logic 24V±10%(10V min at 20mA), digital insulated, triac.An analog output in voltage or current is also available.The function of each output is freely configurable from the faceplate keys.In addition to control and alarm outputs, youcan have outputs that repeat the state of thedigital or retransmission input by processvariable, setpoint, drift, alarm limits andvalues acquired from serial line.Another output (at 10 or 24Vdc, 30mA max.)is available to power external transmitters.The serial communication option (availablein RS485 standard) allows connection tosupervision systems and PLCs with twoprotocols: GEFRAN CENCAL and MODBUSRTU.Instrument programming is facilitated bygrouping parameters in functional blocks(CFG for control parameters, Inp for inputs,Out for outputs, etc.).The instrument can also select displayparameters based on hardwareconfiguration, automatically maskingirrelevant parameters.The instrument is supplied with an "EASY"configuration with just a few parameters(only those for the model ordered andessential for controller operation).In this way, you just have to set the setpointand alarm, and launch selftuning from thebutton.The 600 does all the rest.A PC programming kit is available for evensimpler configuration, composed of a cableand a guided program for Windowsenvironment (see data sheet codeWINSTRUM).TECHNICAL DATAI NPUTSAccuracy 0,2% f.s. ±1digit.Sampling time 120msec.TC- ThermocoupleJ0...1000°C/32...1832°FK0...1300°C/32...2372°FR0...1750°C/32...3182°FS0...1750°C/32...3182°FT-200...400°C/-328...752°FB44...1800°C/111...3272°FE-100...750°C/-148...1382°FN0...1300°C/32...2372°FL-GOST0...600°C/32...1112°FU-200...400°C/ -328...752°FG0...2300°C/32...4172°FD0...2300°C/32...4172°FC0...2300°C/32...4172°F(NI-Ni18Mo)0...1100°C / 32...2012°Fcustom-1999 (9999)RTD 2/3 wiresPT100 -200...850°C /-328...1562°FJPT100 -200...600°C/ -328...1112°FPTC990Ω, 25°C -55...120°C/-67...248°FNTC1KΩ, 25°C -10...70°C/14...158°FGEFRAN spa reserves the right to make any aesthetic or functional change at any time and without prior noticeGEFRAN spa via Sebina, 74 - 25050 Provaglio d’Iseo (BS)Tel.03098881 - fax 0309839063 - Internet: DTS_600_1107_ENG。

Lorex MPX HDSe

Lorex MPX HDSe
2. Se connecter avec le nom d’utilisateur du système (par défaut : admin) et le mot de passe (par défaut : 000000).
3.
2. Clic Droit: • En mode visionnement en direct :
Contrôle des caméras PTZ (non incluses) Ajuste les réglages de la couleur et de l’image de la caméra Voir les informations du système Démarrer/arrêter le mode séquence Esactiver l’alarme sonore
6: EN MARCHE
Bip
Si le système émet un signal sonore au démarrage, le câble Ethernet n’est peut-être pas branché, ou le système n’est peut-être pas connecté à Internet. Pour arrêter le signal sonore : 1. Brancher un câble Ethernet du système au routeur et redémarrer le système. OU 2. Cliquer avec le bouton droit et cliquer sur Disable Beep.
Cliquer sur et sélectionner SETTING
4. Cliquer sur GENERAL et sélectionner l’onglet Date&Time.

HT66FXX中文版详细资料

HT66FXX中文版详细资料
9 P B 5 /S C S /V R E F
H T66F30 1 6 D IP -A /N S O P -A /S S O P -A
P A 0 /C 0 X /T P 0 _ 0 /A N 0 1 VSS&AVSS 2 P B 4 /X T 2 3 P B 3 /X T 1 4 P B 2 /O S C 2 5 P B 1 /O S C 1 6 VDD&AVDD 7 P B 0 /R E S 8
型号
外部 VDD ROM RAM EEPROM I/O 中断 A/D
TM 模块
接口 (SPI/I2C)
UART
堆栈
封装形式
HT66F20*
2.2V~ 5.5V
1K×14
64×8
32×8
18
2
12-bit×8
10-bit CTM×1 10-bit STM×1

√4
16DIP/NSOP/SSOP 20DIP/SOP/SSOP
在模拟特性方面,这款单片机包含一个多通道 12 位 A/D 转换器和双比较器功能。还带有多个 使用灵活的定时器模块,可提供定时功能、脉冲产生功能及 PWM 产生功能。内建完整的 SPI 和 I2C 功能,为设计者提供了一个易与外部硬件通信的接口。内部看门狗定时器、低电压复位和低电压检 测等内部保护特性,外加优秀的抗干扰和 ESD 保护性能,确保单片机在恶劣的电磁干扰环境下可靠 地运行。
fSYS=8MHz:2.2V~5.5V fSYS=12MHz:2.7V~5.5V fSYS=20MHz:4.5V~5.5V • VDD=5V,系统时钟为 20MHz 时,指令周期 为 0.2µs • 提供暂停和唤醒功能,以降低功耗 • 五种振荡模式: 外部晶振 -- HXT 外部 32.768kHz 晶振 -- LXT 外部 RC -- ERC 内部 RC -- HIRC 内部 32kHz RC -- LIRC • 多种工作模式:正常、低速、空闲和休眠 • 内部集成 4MHz,8MHz 和 12MHz 振荡器, 无需外接元件 • 所有指令都可在 1 或 2 个指令周期内完成 • 查表指令 • 63 条指令 • 多达 12 层堆栈

第3章ARM汇编语言程序设计GNU汇编ppt课件

第3章ARM汇编语言程序设计GNU汇编ppt课件
BL 子程序名 即可完成子程序的调用。 该指令在执行时完成如下操作:将子程序的返回地址存放在连接寄存器LR中,同
时将程序计数器PC指向子程序的入口点,当子程序执行完毕需要返回调用处时, 只需要将存放在LR中的返回地址重新复制给程序计数器PC即可。在调用子程序的 同时,也可以完成参数的传递和从子程序返回运算的结果,通常可以使用寄存器 R0~R3完成。 以下是使用BL指令调用子程序的汇编语言源程序的基本结构:
.string/.asciz/.ascii
语法格式 .string/.asciz/.ascii 表达式{,表达式}...
作用
.string/.asciz/.ascii定义多个字符串。 注意:ascii伪操作定义的字符串需要自动添加结尾字符'\0'
举例
.string "abcd","hello"
bne 1f @跳转到1标号去执行 局部标号代表它所在的地址,因此也可以当作变量或
者函数来使用。
Linux汇编程序中的分段
(1).section伪操作
用户可以通过.section伪操作来自定义一个段,格式如下 :
.section section_name [, "flags"[, %type[,flag_specif
地址表达式expr的取值范围如下:
当地址值是字节对齐时,其取指范围为−255B~255B;
当地址值是字对齐时,其取指范围为−1020B~1020B。
ARM伪指令——小范围的地址读取
ADR伪指令将基于PC相对偏移的地址值或基于寄存器相对偏移的 地址值读取到寄存器中。在汇编编译器编译源程序时,ADR伪指令被 编译器替换成一条合适的指令。通常,编译器用一条ADD指令或SUB 指令来实现该ADR伪指令的功能,若不能用一条指令实现,则产生错 误,编译失败。

ARM嵌入式系统结构与编程,课后练习及答案

ARM嵌入式系统结构与编程,课后练习及答案

第一章思考与练习1、举出3个书本中未提到的嵌入式系统的例子。

答:红绿灯控制,数字空调,机顶盒2、什么叫嵌入式系统?嵌入式系统:以应用为中心、以计算机技术为基础、软件硬件可裁剪、适应应用系统对功能、可靠性、成本、体积、功耗严格要求的专用计算机系统。

3、什么叫嵌入式处理器?嵌入式处理器分为哪几类?嵌入式处理器是为完成特殊的应用而设计的特殊目的的处理器。

嵌入式微处理器(Embedded Microprocessor Unit, EMPU)嵌入式微控制器(Microcontroller Unit, MCU)嵌入式DSP 处理器(Embedded Digital Signal Processor, EDSP)嵌入式片上系统(System On Chip)4、什么是嵌入式操作系统?为何要使用嵌入式操作系统?是一段在嵌入式系统启动后首先执行的背景程序,首先,嵌入式实时操作系统提高了系统的可靠性。

其次,提高了开发效率,缩短了开发周期。

再次,嵌入式实时操作系统充分发挥了 32 位CPU 的多任务潜力。

第二章1、嵌入式系统项目开发的生命周期分哪几个阶段?各自的具体任务是什么?项目的生命周期一般分为识别需求、提出解决方案、执行项目和结束项目4 个阶段。

识别需求阶段的主要任务是确认需求,分析投资收益比,研究项目的可行性,分析厂商所应具备的条件。

提出解决方案阶段由各厂商向客户提交标书、介绍解决方案。

执行项目阶段细化目标,制定工作计划,协调人力和其他资源;定期监控进展,分析项目偏差,采取必要措施以实现目标。

结束项目阶段主要包括移交工作成果,帮助客户实现商务目标;系统交接给维护人员;结清各种款项。

2、为何要进行风险分析?嵌入式项目主要有哪些方面的风险?在一个项目中,有许多的因素会影响到项目进行,因此在项目进行的初期,在客户和开发团队都还未投入大量资源之前,风险的评估可以用来预估项目进行可能会遭遇的难题。

需求风险;时间风险;资金风险;项目管理风险3、何谓系统规范?制定系统规范的目的是什么?规格制定阶段的目的在于将客户的需求,由模糊的描述,转换成有意义的量化数据。

DIN-GB标准件对照表

DIN-GB标准件对照表
21
DIN261
T型头螺栓
T-headbolts
22
DIN315AF
蝶型螺母(美
制)
WingnutsAmericaform
23
DIN315DF
蝶型螺母(德
制)
Wingnutsgermanyform
GB62-88
24
DIN316AF
蝶型螺母(美
制)
WingscrewsAmericaform
蝶型螺母(德
withcollar
46
DIN466
滚花高螺母
Knurledthumbnutswithcollar
GB806-88
47
DIN467
潦花溥螺母
Knurledthumbthinnuts
GB807-88
48
DIN470
锁紧垫圈
Sealingwashers
49
DIN471
轴用弹性垫圈
Retainingringsfor
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Flatcountersunknibbolts
72
DIN605
沉头长方颈马车
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Flatcountersunklongsquareneckbolts
73
DIN607
半圆头带插销马
车螺栓
Cupheadnibbolts
74
DIN608
沉头短方颈马车
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Flatcountersunkshort
squareneckbolts
Hexagonscrews
ISO4018
64
DIN561
八角头圆柱端
紧定螺钉
Hexagonsetscrewswithfull

BOSS ME-25 吉他多效器说明书.pdf_1702059371.3535774

BOSS ME-25 吉他多效器说明书.pdf_1702059371.3535774

16ME-25Guitar Multiple EffectsPowerhouse FX with Stompbox Simplicity MPowerful COSM ®amp models and effects onboard, from classic to contemporaryMSuper simple user-friendly interfaceM SOUND LIBRARY provides extensive collection of ready-to-use tones; simply choose a category and select a variationM Sounds can be instantly edited with the Drive, Tone, Level knobs and Expression pedalM SUPER STACK adds immensely heavy low-end and punch MPhrase Loop function with 38 seconds of recording timeMFunctions as a USB audio interfaceM Built-in AUX input for jamming along with external music devices (MP3/CD players, etc.)M Runs on six AA batteries or AC adaptorM Includes Cakewalk SONAR 8.5 LE software and dozens of audio loops, rhythms and songs for jamming or practiceM Free downloadable Librarian software ME-25 SpecificationsI AD Conversion 24-bit + AF method * I DA Conversion 24-bit I Sampling Frequency 44.1 kHzI Memory 60 I Sound Library 60 I Sound Library Category CLEAN, CRUNCH, DRIVE, HEAVY , LEAD, EXTREME I Effect Type COMP/FX (Compressor/Effect): COMP , T.WAH, AC SIM, OD/DS (Overdrive/Distortion): BOOST, OD-1, T-SCREAM, BLUES, DIST, CLASSIC, MODERN, METAL, CORE, FUZZ, PREAMP: CLEAN, TWIN, TWEED, VO DRIVE, BG LEAD, MS VINTAGE, MS MODERN, 5150 DRIVE, R-FIER, ULTRA METAL, MODULATION: CHORUS, PHASER, FLANGER, ROTARY , UNI-V, TREMOLO, HARMONIST, OCTAVE, DELAY: 1-99ms, 100-990ms, 1000-6000ms, TAP , REVERB: ROOM, HALL, PEDAL FX (Pedal Effect): WAH, +1 OCTAVE, -1 OCTAVE, FREEZE, NS (Noise Suppressor) I Nominal Input Level INPUT: -10 dBu, AUX IN: -18 dBu I Input Impedance INPUT: 1M , AUX IN: 22k I NominalOutput Level -10 dBu I Output Impedance 2k I Display 7 segments, 2 digits LED I Power Supply DC 9 V Dry Batteries (R6/LR6 (AA) type) x 6, AC Adaptor (BOSS PSA-Series: sold separately) I CurrentDraw 150 mA I Expected battery life under continuous use Alkaline: 9 hours, Carbon: 3 hours (These figures will vary depending on the actual conditions of use.) I Dimensions 300 (W) x 191 (D) x 72 (H) mm/ 11-13/16 (W) x 7-9/16 (D) x 2-7/8 (H) inches I Maximum height 300 (W) x 191 (D) x 93 (H) mm/ 11-13/16 (W) x 7-9/16 (D) x 3-11/16 (H) inches I Weight 1.9 kg, 4 lbs 4 oz (including batteries)I Accessories Owner’s Manual, ME-25 DVD-ROM, Sound Library/Memory List (Leaflet), Sound Library Sticker, Dry Batteries (Alkaline: LR6 (AA) type) x 6, Roland Service (Information Sheet) I Options AC Adaptor BOSS PSA-Series* 1 AF method (Adaptive Focus method) / This is a proprietary method from Roland & BOSSthat vastly improves the signal-to-noise (S/N) ratio of the A/D and D/A converters.* 0 dBu = 0.775 Vrms* The specifications are subject to change without notice.FX with Stompbox Simplicity。

ssd1963ql9使用手册

ssd1963ql9使用手册
5.1 5.2 80 BALLS TFBGA................................................................................................................................................10 128 PINS LQFP ....................................................................................................................................................11
7.1 MCU INTERFACE .................................................................................................................................................16 7.1.1 6800 Mode ..................................................................................................................................................16 7.1.2 8080 Mode ..................................................................................................................................................16 7.1.3 Register Pin Mapping .................................................................................................................................16 7.1.4 Pixel Data Format ......................................................................................................................................16 7.1.5 Tearing Effect Signal (TE) ..........................................................................................................................17 7.2 SYSTEM CLOCK GENERATION .............................................................................................................................18 7.3 FRAME BUFFER....................................................................................................................................................19 7.4 SYSTEM CLOCK AND RESET MANAGER ...............................................................................................................19 7.5 LCD CONTROLLER ..............................................................................................................................................20 7.5.1 Display Format ...........................................................................................................................................20 7.5.2 General Purpose Input/Output (GPIO) ......................................................................................................20
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8th Bharat Ratna Rajiv Gandhi Memorial Lecture-2009Space Technology Applications forRural Development in IndiaDr. G. Madhavan NairIt gives me immense pleasure to be with you today at the Colloquium on ‘Grassroots Level Planning and Local Government In stitutions in India’ organised by the Academy of Grassroots Studies and Research of India (AGRASRI). It is a great privilege and special honour for me to deliver the 8th Bharat Ratna Rajiv Gandhi Memorial lecture in this august gathering, which in the past was delivered by eminent personalities like Shri Mani Shanker Aiyar, Shri Shivraj Patil, Dr. Turlapaty Kutumba Rao, Prof. U.R. Rao, Prof. M.S. Swaminathan, Dr. R.A. Mashelkar and Dr. C. Rangarajan. I am also pleased to note that AGRASRI has been organising this annual event since 2002 to commemorate the contribution of our former Prime Minister, Bharat Ratna Shri Rajiv Gandhi, a great visionary with a passion for modern technology, who strongly advocated its use in all its facets, and take India to the 21st Century in a transformed manner. A quote from Rajiv Gandhi while addressing the joint session of the US congress and India is appropriate here:“I am young, and I too have a dream. I dream of an India - strong, independent,self-reliant and in the front-rank of the nations of the world in the service ofmankind...”Rajiv Gandhi introduced India to modern science and technology, which he considered as the very essence of development. He said, …Freedom and racism cannot co-exist. Science and poverty cannot co-exist.‟ He wanted Indian industry to develop to its fullest capacity. He laid great emphasis on the Green revolution and Yellow revolution which he looked upon as being extremely important for development of agriculture.It was Rajiv Gandhi who initiated the telecom revolution in the country, which has resulted in a massive increase in tele-density across the country. Today’s Information Technology boom in India is because of his prudence on the importance of ICT. He had increased government support for science and technology and associated industries, and reduced taxes and tariffs on technology based industries, especially for computers, airlines, defence and telecommunications. Rajiv Gandhi dreamt of a 21st century India at par with the rest of the world and recognition of India as part of G8 + 5 countries is an indication in this line.Rajiv Gandhi also realised that democracy would be meaningless unless it was decentralized at the grassroots level, and this led to the strengthening of the Panchayati Raj. It is the most vibrant system of democracy at the panchayat level in operation today. Nearly 85% of funds under rural development today are being used through Panchayati Raj system. He also advocated a minimum of 33% representation for women in the Panchayati Raj system, which is one of the major steps towards empowerment of women.Rajiv Gandhi was especially concerned about the deteriorating environment. He believed that the destruction of the environment would lead to a vicious cycle of poverty anddisplacement. Today, when we hear the concerns raised by the entire world community and the programmes initiated across the world to protect the environment, we are astonished and surmised to know what a visionary he was!Space Technology also received a great boost during his time, and application of space technology for natural resources management got tremendous impetus. For the first time, satellite images were used to prepare groundwater prospect maps, at detailed scale, for finding drinking water in villages, which eventually became an integral part of the Rajiv Gandhi National Drinking Water Mission, aiming to provide safe drinking water in all needy villages and habitations of the country.As it is the Academy of Grassroots Studies and Research of India (AGRASRI) organising this event, and in the context of the theme of the colloquium, I thought, it is appropriate for me to talk on ‘Space Technology Applications for Rural Development‟. I profusely thank the organisers for inviting me to deliver this prestigious lecture, and honoring me with ‘Bharat Ratna Rajiv Gandhi Outstanding Leadership‟ award.Rural DevelopmentAs you are aware, among the developing countries, India is ranked as one of the fastest growing economies. Indi a’s GDP growth, as per our Planning Commission, would cross 10% towards 2025. We are all aware, while our country is progressing well in the economic front, the major livelihoods of rural India, the agriculture, is suffering due to various uncertainties, and currently shares only 18% of GDP.As told by Mahatma Gandhiji, ‘India lives in its villages‟. Nearly 700 million of our population lives in 600,000 villages. In spite of various efforts to improve the living standards of rural masses, around half of our villages still have poor socio-economic conditions. The rural mass depends on agriculture and allied activities for their sustenance, which is often associated with unforeseen risks. Most of the villages are deprived of basic amenities and services, such as infrastructure, sanitation, education and healthcare. Rural India is also characterised by low literacy due to livelihood compulsions. Transforming rural India is thus a great challenge.Though India has taken significant steps over past decades towards reducing poverty, large numbers of people are still below poverty line - which was 46% in 1985, 36% in 1995 and around 26% in 2005. There is also a clear gap between rural and urban poverty. The challenge is to bridge the divide between the ‘haves’ and ‘have-nots’, dealing with poverty and inequity. Hence, rural development as an integrated concept of growth and poverty alleviation has been a paramount importance to the country.The many efforts of the government for rural development, as we are aware, include: National Food Security Mission (NFSM), Rajiv Gandhi Rashtriya Krishi Vikas Yojana (RGKVY), Pradhan Mantri Gram Sadak Yojana (PMGSY), Rural Housing (RH), Integrated Wasteland Development Programme (IWDP), Accelerated Rural Water Supply Programme (ARWSP), Total Sanitation Programme (TSP), National Rural Health Mission (NHRM), etc. Towards realising the growth potential of rural India, Bharat Nirman, a business plan for rural India, was conceived by the government, and is being implemented. It addresses variousrelated components such as irrigation, all weather roads, rural housing, rural water supply, rural electrification and rural telecommunication connectivity.We need to substantiate the government’s efforts to start a revolution, whi ch can take its 6 lakh villages ‘fast forward’ in time - converting them into economically viable units and growth engines. Realizing the advantage of space as a vantage point, the visionary in Dr. Vikram Sarabhai, the father of the Indian space programme, saw an opportunity to exploit the space technology as a resource for community outreach, capable of serving the remote villages transcending geographical boundaries. And today, India’s space programme distinctly exemplifies how space technology could be the harbinger of rural development.Space TechnologyMaking a modest beginning in 1963 with the launch of a small sounding rocket from Thumba (near Thiruvananthapuram), we have come a long way in establishing space systems like the Indian National Satellite (INSAT) and Indian Remote Sensing (IRS) satellite systems that form a crucial part of our national infrastructure for telecommunication, television broadcasting, meteorology, natural resources survey and management. We have succeeded in building our own satellites, INSAT and IRS, and our own Polar Satellite Launch Vehicle (PSLV) for launching the IRS class of satellites and Geosynchronous Satellite Launch Vehicle (GSLV) for launching the INSAT class of satellites.At present, we have a constellation of IRS satellites covering the whole globe with a revisit period of 2 to 26 days to cater to various applications. Starting with IRS-1A in 1988, we have launched many remote sensing satellites into orbit such as IRS-1B, IRS-1C, IRS-1D, IRS-P3, Oceansat-1, Resourcesat-1, Cartosat-1, Cartosat-2, Cartosat-2A and RISAT-2. Today, India has 9 IRS satellites operating in orbit making it one of the largest constellations of remote sensing satellites in the world. The data from these satellites have been put to u se for various applications ranging from agriculture, fisheries and forestry to urban planning and environment monitoring.The Indian National Satellite (INSAT) system, currently with nine of them in orbit, is one of the largest domestic satellite communication systems in the world. INSAT, since its commissioning in 1983, has brought in vast advancement in telecommunications, television broadcasting, radio networking, meteorology and disaster management services. Presently, INSAT family of satellites with 220 transponders in frequency spectrum of S, C, Ext-C and Ku bands is providing communication network across the country.Space Technology Applications for Rural DevelopmentSatellite communication and earth observation satellites have demonstrated their capabilities to provide the services relating to healthcare, education, weather, land and water resources, land records, agricultural advisories, etc., relevant at communities/ village level. The value-added, high-resolution earth observation images provide community-centric, geo-referenced spatial information for management of natural resources, such as land use/ land cover, terrain morphology, surface water and groundwater, soil characteristics, environment and infrastructure.Satellite CommunicationOne of the major components and driving force related to rural development is communication. It has been given highest priority for bringing desirable social and behavioural change among the most vulnerable rural society. Satellite communications has the ability to simultaneously reach a large population, spread over vast distances, and inherently is a powerful tool to support development education and training.ISRO had undertaken several projects that focused on development of humanity through sophisticated satellite-based communication. Right from the inception of utilizing space programmes for development, the experiments like Satellite Instructional Television Experiment (SITE), Kheda Communications Project (KCP), Jhabua Development Communications Project (JDCP), Training and Development Communication Channel (TDCC) have been carried out. We started with the basic premise that television communication would facilitate rural development, and we demonstrated the impact of television broadcast and interactive programmes on the rural society.Tele-EducationThe tele-education programme launched by ISRO, serviced by the exclusive satellite ‘EDUSAT’, is primarily intended for school, college and higher levels of education to support both curricula based as well as vocational education. With 5 Ku-band transponders providing spot beams, and one Ku-band transponder providing national beam, and 6 extended C-band transponders with national coverage beams, EDUSAT is specifically configured for audio-visual medium, employing digital interactive classroom and multimedia multi-centric system. Many important institutions such as the IGNOU, UGC, IITs, and many State Education Departments and Universities are making use of the EDUSAT network. Presently, more than 34,500 classrooms are in the EDUSAT network out of which 3,400 are interactive terminals.Tele-MedicineA healthy citizen contributes to make a healthy nation. Over the years, the government has introduced various healthcare initiatives and policies, which has resulted in the increase in life expectancy of our citizens. However, providing healthcare to millions of people in rural India is really a formidable challenge. It is a matter of concern that a meager 3% of the qualified doctors, who are attached to about 23,000 Primary and 3,000 Community Health Centres, are available to attend to the 70% of the Indian population. Satellite communication technology, combined with information technology provides a technological means of taking the benefits of the advances in medical sciences to large sections of people spread out in remote and inaccessible villages. ISRO’s telemedicine network has enabled many poor rural villagers hitherto denied with quality medical services to get the best of medical services available in the country. As pf now, we have 377 tele-medicine nodes consisting of 320 remote/ district/ medical college/ mobile hospitals connected to 57 super specialty hospitals in different cities through ISRO’s satellites. The ISRO telemedicine network is expanding to various regions in the country and has become one of the most visible and sociological applications in the world today.Earth ObservationRajiv Gandhi had a lot of concerns for the Indian farmers. He wished that the yield in the drought prone areas is as important as the yield in non-irrigated and rainfed areas. He wanted to ensure that water resources are used efficiently. He paid more attention to the irrigation projects and minor irrigation systems. He emphasized on intr oducing the modern methods in irrigation. In view of the scarcity of water and rainfall, he wanted to improve the weather forecasting system for accurate planning and decisions. In this line, I would like to share some of the operationally demonstrated remote sensing projects, which served the country’s pursuit and Rajiv Gandhi’s dreams for rural development.About 16% of the country’s geographical area is characterized by wastelands, both cultivable and non-cultivable; and reclamation of such lands is a must forenhancing agricultural productivity, improving ecology, and also for non-agriculture related uses. Mapping and monitoring of wastelands over entirecountry has been carried out using remote sensing data at the behest ofMinistry of Rural Development for planning and implementing variousreclamation activities. It is observed that during the period 1998 to 2003, about8 mha ha of wastelands have been reclaimed.In India, 60% of total food grain production comes from the irrigated area, and the management of water supplies for irrigation in command areas requiresinformation on total demand and its distribution. The multi-temporal satellitedata forms the basis for the performance evaluation in terms of croppingsystems, cropping intensity and the water-use efficiency. Towards this, 14large irrigated commands in 5 States (Andhra Pradesh, Assam, Maharashtra,Rajasthan and West Bengal), covering a total culturable command area (CCA)of 3.3 mha have been studied for their performance.To increase the irrigation efficiency, the gap between the irrigation potential created and that utilized through micro level infrastructure development is to bemonitored. The Cartosat data is being utilized in irrigation infrastructureassessment under Accelerated Irrigation Benefit programme (AIBP). Thesatellite data has also been used to map the current status and to monitor thespatial extent of water logging and soil salinity & alkalinity in more than 800major and medium irrigation commands.Under the ‘Rajiv Gandhi National Drinking Water Mission’ of Ministry of Rural Development, remote sensing technology has been used for preparinggroundwater prospects maps on 1:50,000 scale in 10 states. Favourablezones/ sites for constructing thousands of recharge structures are alsoidentified in these maps. With such remote sensing derived information, thesuccess rate of bore wells has gone around 90% in most of the States. Theproject is now being extended, in phases, to cover the entire country.Watershed Development Programme is one of the major initiatives in the country towards conservation of soil and water resources in the rainfed area forenhancing agricultural production, and to ensure livelihood security to ruralpeople, besides eco-development. Such endeavour needs scientific databasesfor evolving suitable strategies for planning. Remote sensing applications haveresponded to such requirements of watershed development. The Integrated Mission for Sustainable Development (IMSD), carried out for 25% of co untry’s geographical area, has catered to the needs of Drought Prone Area development Programme (DPAP) and National Watershed Development Programme for Rain-fed Areas (NWDPRA). We have also enabled the local planning officials at desert/ dry areas with land and water resources development plans.I would like to emphasise on the community driven watershed developmentprogramme in Karnataka called ‘Sujala Watershed Development Project’, which is implemented by Government of Karnataka with the World Bank assistance.The project is implemented in 5 drought-prone districts covering an area of around 0.5 million ha, and benefiting more than 400,000 households. The main objective of the Sujala project is to improve the productivity of degraded watersheds, reduce poverty and strengthen local communities and institutions.The project aims to increase the productivity of the watersheds through physical and financial interventions, alternate farming systems, adoption of agro-forestry and agro-horticultural systems integrated with livestock and income generating activities through micro-credit enterprises. The communities are involved in the participatory planning, implementation and maintenance of assets, while the NGOs and the Government departments act as facilitators.The unique feature of this project is the way remote sensing, GIS and the Management Information System (MIS) are dynamically linked with the impact assessment, both in terms of development of natural resources as well as socio-economic indicators. It is important that such success stories in the dry land agricultural areas are scaled-up, and replicated in different agro-ecological regions of the country, which would bring 90 mha of dry lands into optimal productive capacity.The Department of Land Resources of Ministry of Rural Development has recently embarked upon an important and most ambitious programme, the ‘National Land Records Modernization Programme (NLRMP)’. This programme aims at creating ‘conclusive titles’ for all land holdings in the country, and making the scientific development efforts of the Government ‘citizen-centric’.This phenomenal task requires right mix of technologies as suited for timely realisation of its goals.The synergy of contemporary technologies like remote sensing, Geographical Information System (GIS), GPS & ICT have led to an overall change in the planning process. Cadastral-referenced databases by geo-referencing village and cadastral maps in Chhattisgarh, Gujarat and Maharashtra States serves asa model for implementing it all over the country. The ample advantages of theproject include scientific land-use planning and their implementation at absolute local level. Such databases also are very useful for planning and mitigation activities during disasters.Farming in our country strongly depends on the weather. From the satellite meteorological observation point of view, India is having the INSAT/ KALPANA VHRR system operating over the past two decades, providing continuousmonitoring of the weather systems over the Indian region. This system hasenabled deriving various meteorological parameters such as cloud cover, cloudtop temperature, cloud motion vectors, atmospheric winds, and sea-surfacetemperature. One can also monitor the developing weather systems such asTropical Cyclones. One of the key elements for improved weather forecastingis to substantially augment the surface observation network, and networking itwith the central weather modeling station. In this context, I would like tomention about the development of low-cost Automatic Weather Stations (AWS)and Doppler Weather Radars (DWR) by ISRO associating Indian industries.The indigenously developed AWS is capable of recording weather data on acontinuous basis and transmit through the INSAT system. The data from AWSnetwork and the DWR will be of substantial use in the models beingoperationally run by the National Centre for Medium Range WeatherForecasting (NCMRWF) and the India Meteorological Department (IMD) forproviding meteorological Services for agricultural purposes.Disaster Management SupportIndia is one of the most disaster prone countries in the world with increasing vulnerability to cyclones, floods, landslides, droughts and earthquakes. In order to strengthen India’s reso lves towards disaster management, ISRO has evolved the Disaster Management Support (DMS) programme, which is a convergence of space communications and remote sensing capabilities. Today, INSAT and IRS satellite systems provide disaster management support for the preparedness, early warning, risk information, impact and damage assessment and emergency communication. The space based information is used by the stakeholders for various disasters such as floods, cyclones, drought, forest fires, earthquakes, etc., for relief and rehabilitation measures. INSAT Mobile Satellite Services (MSS) terminals are being put to use during emergencies for providing necessary connectivity.Village Resource CentreAmong the many societal development related initiatives, I would like to emphasize on a unique programme of ISRO called ‘Village Resource Centres (VRC)’. It is being implemented in association with the stakeholders at local levels, to reach the benefits of space and other IT enabled services directly to the common man. The VRCs are a step to bridge the societal divides, and are proving to be vital in improving the quality of life in villages - by way of providing locale-specific advisories for farm sector development, livestock management, local governance, skill development for livelihood support, awareness creation, market information, building disaster resilience, etc. All these services are reaching the doorsteps of common man, in local language. So far over 470 VRCs are set up in 22 States and Union Territories, and many more are in the offing. The uniqueness of VRCs is the knowledge connectivity between the experts at agricultural universities, research institutes and doctors at hospitals, and the village community. We are also making the natural resources data available at VRCs, which could be used to work out development plans at local levels.Way AheadWe have many more programmes using space based inputs in the years to come for planning and development. At the behest of the Planning Commission of India, ISRO is launching a National Mission - ‘Space based Information Support for Decentralised Planning’. It would provide ICT enabled geo-spatial platform involving local bodies to carry out developmental activities under Panchayati Raj in a decentralised, speedy and transparent manner. The Mission aims to harness the space technology and the information systems at the local bodies to create information base and provide services. We also focus on capacity building at Panchayat level to use these space based inputs. We are sure, that if the human resources at Panchayat level are enriched with the knowledge of using space based inputs, many issues related to land use or reclamation of wastelands, agriculture, horticulture, infrastructure development, water harvesting, etc., specific to the local environment can be solved.The future is bright and full of promise. Let us carry the spirit of our former Primer Minister Bharat Ratna Sri Rajiv Gandhi with our insatiable desire to know, explore and understand. I am happy to state that the Indian space community would continue to harness the space technology to evolve new programmes and avenues towards transforming rural India.Let me conclude my talk with the quote of Pandit Jawaharlal Nehru. I quote,“The ambition of the greatest men of our generation has been to wipe every tearfrom every eye. That may be beyond us, but so long as there are tears andsuffering, so long our work will not be over.”I sincerely thank the Academy of Grassroots Studies and Research of India for giving me an opportunity to present the space-based solutions for rural development before you.Thank You.Padma Vibhushan Dr. G. Madhavan Nair is Chairman, Indian Space Commission; Chairman,Indian Space Research Organisation and Secretary, Department of Space, Government of India,Bangalore.Tex t o f the Spee ch o f the 8th Bharat Ratna Rajiv Gandhi Me morial Lecture on ‘S paceTechnology Applications for Rural Development in India’,deliv ered by Dr. G.Madhavan Nair on 20th Au gus t 2009 a t Ho te l Bl is s (Darbar Hall), Tirupati, und er theaegis o f A cade my of Grassroo ts S tudie s and Research o f Ind ia (AGRASRI), inCollabora tion wi th Raj iv Rural Dev elop men t Founda tion, Tirupa ti (And hra Pradesh).。

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