NDS332中文资料

元器件交易网
June 1997
NDS332P P-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description
These P-Channel logic level enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. These devices are particularly suited for low voltage applications such as notebook computer power management, portable electronics, and other battery powered circuits where fast high-side switching, and low in-line power loss are needed in a very small outline surface mount package.
1.8
R DS(ON) , NORMALIZED
I D = -1A V GS = -2.7
R DS(on), NORMALIZED
V GS = -2.7 V
1.6 1.4 1.2 1 0.8 0.6 0.4
TJ = 125°C
25°C
-55°C
-25
0 25 50 75 100 T , JUNCTION TEMPERATURE (°C)
J
125
150
0
-0.5
-1 -1.5 -2 I , DRAIN CURRENT (A)
D
-2.5
-3
Figure 3. On-Resistance Variation with Temperature.
Figure 4. On-Resistance Variation with Drain Current and Temperature.
Symbol Parameter Conditions Min Typ Max Units OFF CHARACTERISTICS BVDSS IDSS Drain-Source Breakdown Voltage Zero Gate Voltage Drain Current VGS = 0 V, ID = -250 µA VDS = -16 V, VGS = 0 V TJ = 55°C IGSS IGSS Gate - Body Leakage Current Gate - Body Leakage Current VGS = 8 V, VDS= 0 V VGS = -8 V, VDS= 0 V -20 -1 -10 100 -100 V µA µA nA nA
T A = 25°C unless otherwise noted
NDS332P -20 ±8
(Note 1a)
Units V V A
Gate-Source Voltage - Continuous Drain Current - Continuous - Pulsed Maximum Power Dissipation
Features
-1 A, -20 V, RDS(ON) = 0.41 Ω @ VGS= -2.7 V RDS(ON) = 0.3 Ω @ VGS = -4.5 V. Very low level gate drive requirements allowing direct operation in 3V circuits. VGS(th) < 1.0V. Proprietary package design using copper lead frame for superior thermal and electrical capabilities. High density cell design for extremely low RDS(ON). Exceptional on-resistance and maximum DC current capability. Compact industry standard SOT-23 surface Mount package.
(Note 1a) (Note 1b)
-1 -10 0.5 0.46 -55 to 150
W
Operating and Storage Temperature Range
°C
THERMAL CHARACTERISTICS RθJA RθJC Thermal Resistance, Junction-to-Ambient Thermal Resistance, Junction-to-Case
ON CHARACTERISTICS (Note 2) VGS(th) Gate Threshold Voltage VDS = VGS, ID = -250 µA TJ =125°C RDS(ON) Static Drain-Source On-Resistance VGS = -2.7 V, ID = -1 A TJ =125°C VGS = -4.5 V, ID = -1.1 A ID(ON) On-State Drain Current VGS = -2.7 V, VDS = -5 V VGS = -4.5 V, VDS = -5 V gFS Ciss Coss Crss tD(on) tr tD(off) tf Qg Qgs Qgd -1.5 -2.5 2.2 -0.4 -0.3 -0.6 -0.45 0.35 0.5 0.26 -1 -0.8 0.41 0.74 0.3 A V
NDS332P Rev. E
元器件交易网
Electrical Characteristics (TA = 25°C unless otherwise noted)
Symbol Parameter Conditions Min Typ Max Units DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS IS VSD Maximum Continuous Source Current Drain-Source Diode Forward Voltage VGS = 0 V, IS = -0.42 A (Note 2) -0.75 -0.42 -1.2 A V
1 0.8 0.6 0.4
-2.7 -3.0 -3.5 -4.5
-1
-1.5
-0.5
0
0
-0.5 V
DS
-1 -1.5 -2 -2.5 , DRAIN-SOURCE VOLTAGE (V)
-3
0
-0.5
-1 -1.5 -2 I , DRAIN CURRENT (A)
D
-2.5
-3
Figure 1. On-Region Characteristics.
________________________________________________________________________________
D
G
S
Asolute Maximum Ratings
Symbol VDSS VGSS ID PD TJ,TSTG Parameter Drain-Source Voltage
1a
1b
Scale 1 : 1 on letter size paper 2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
NDS332P Rev. E
元器件交易网
Typical Electrical Characteristics
Notes: 1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is guaranteed by design while RθCA is determined by the user's board design.
V DS = - 3V-1.225°源自 T = -55°C J 125°C
Vth , NORMALIZED
GATE-SOURCE THRESHOLD VOLTAGE (V)
-1.5
1.15 1.1
V DS = VGS I
Figure 2. On-Resistance Variation with Drain Current and Gate Voltage.
1.8 DRAIN-SOURCE ON-RESISTANCE DRAIN-SOURCE ON-RESISTANCE 1.6 1.4 1.2 1 0.8 0.6 0.4 -50
DYNAMIC CHARACTERISTICS 195 105 40
SWITCHING CHARACTERISTICS (Note 2) Turn - On Delay Time Turn - On Rise Time Turn - Off Delay Time Turn - Off Fall Time Total Gate Charge Gate-Source Charge Gate-Drain Charge VDS = -5 V, ID = -1 A, VGS = -4.5 V VDD = -6 V, ID = -1 A, VGS = -4.5 V, RGEN = 6 Ω 8 30 25 27 3.7 0.5 0.9 15 45 45 45 5 ns ns ns ns nC nC nC