HD74ALVCH162260资料

2B H L 2B0 *1 2B0 *1 H L 2B0 *1 Z Z Active Active
H : High level L : Low level X : Immaterial Z : High impedance Note: 1. Output level before the indicated steady state input conditions were established.
3
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HD74ALVCH162260
Absolute Maximum Ratings
Item
Symbol
Ratings
Unit Conditions
Supply voltage
VCC
Input voltage *1, 2
VI
Output voltage *1, 2 Input clamp current Output clamp current Continuous output current VCC, GND current / pin Maximum power dissipation at Ta = 55°C (in still air) *3
HD74ALVCH162260
Logic Diagram
LE1B 2 LE2B 27
30
LEA1B LEA2B 55
OE2B 56 OE1B 29
OEA 1
28
SEL
8
A1
C1 G1
1
1D
1
C1
1D
C1
1D
C1 1D
To eleven other channels
23
1B1
6
2B1
6
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HD74ALVCH162260
12-bit to 24-bit Multiplexed D-type Latches with 3-state Outputs
ADE-205-177B (Z) 3rd. Edition
December 1999
Description
V
VCC
V
–12
mA
VCC = 2.3 V
–12
VCC = 2.7 V
–24
VCC = 3.0 V
–6
mA
VCC = 2.3 V
–8
VCC = 2.7 V
–12
VCC = 3.0 V
12
mA
VCC = 2.3 V
12
VCC = 2.7 V
24
VCC = 3.0 V
6
mA
VCC = 2.3 V
8
VCC = 2.7 V
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HD74ALVCH162260
Function Table
Inputs
1B
2B
SEL
H
X
H
L
X
H
X
X
H
X
H
L
X
L
L
X
X
L
X
X
X
LE1B
LE2B
H
X
H
X
L
X
X
H
X
H
X
L
X
X
B-to-A (OEB = H)
OEA L L L L L L H
Output A
H L A0 *1 H L A0 *1 Z
VO I IK I OK IO ICC or IGND PT
–0.5 to 4.6 –0.5 to 4.6 –0.5 to VCC +0.5 –0.5 to VCC +0.5 –50 ±50 ±50 ±100 1
V
V
Except I/O ports
I/O ports
V
mA
VI < 0
mA
VO < 0 or VO > VCC
3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
4
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Inputs A H L H L H L X X X X X
LEA1B H H H H L L L X X X X
LEA2B H H L L H H L X X X X
OE1B
OE2B
L
L
L
L
LLLL来自LLL
L
L
L
H
H
L
H
H
L
L
L
A-to-B (OEA = H)
Outputs 1B H L H L 1B0 *1 1B0 *1 1B0 *1 Z Active Z Active
2.3
VI
0
VO
0
IOH (A port) —
—
—
IOH (B port) — —
—
Low level output current
IOL (A port) — —
—
IOL (B port) — —
—
Input transition rise or fall rate ∆t / ∆v
0
3.6
V
VCC
2
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Pin Arrangement
HD74ALVCH162260
OEA 1 LE1B 2
2B3 3 GND 4 2B2 5 2B1 6 VCC 7
A1 8 A2 9 A3 10 GND 11 A4 12 A5 13 A6 14 A7 15 A8 16 A9 17 GND 18 A10 19 A11 20 A12 21 VCC 22 1B1 23 1B2 24 GND 25 1B3 26 LE2B 27 SEL 28
Features
• VCC = 2.3 V to 3.6 V • Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C) • Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C) • High output current ±12 mA (@VCC = 3.0 V) • Bus hold on data inputs eliminates the need for external pullup / pulldown resistors • B-port outputs have equivalent 26 Ω series resistors, so no external resistors are required.
HD74ALVCH162260
Recommended Operating Conditions
Item
Symbol
Min
Max
Unit Conditions
Supply voltage Input voltage Output voltage High level output current
VCC
mA
VO = 0 to VCC
mA
W
TSSOP
Storage temperature
Tstg
–65 to 150
°C
Notes:
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
VIL
2.3 to 2.7 —
0.7
2.7 to 3.6 —
0.8
VOH (A port) Min to Max VCC–0.2 —
1. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
2. This value is limited to 4.6 V maximum.
12
VCC = 3.0 V
10
ns / V
Operating temperature
Ta
–40
85
°C
Note: Unused control inputs must be held high or low to prevent them from floating.
5
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The HD74ALVCH162260 is a 12-bit to 24-bit multiplexed D-type latch used in applications where two separate data paths must be multiplexed onto, or demultiplexed from, a single data path. Typical applications include multiplexing and / or demultiplexing of address and data information in microprocessor or bus interface applications. This device is also useful in memory interleaving applications. Three 12-bit I / O ports (A1-A12, 1B1-1B12, and 2B1-2B12) are available for address and / or data transfer. The output enable (OE1B, OE2B, and OEA) inputs control the bus transceiver functions. The OE1B and OE2B control signals also allow bank control in the A-to-B direction. Address and / or data information can be stored using the internal storage latches. The latch enable (LE1B, LE2B, LEA1B, and LEA2B) inputs are used to control data storage. When the latch enable input is high, the latch is transparent. When the latch enable input goes low, the data present at the inputs is latched and remains latched until the latch enable input is returned high. Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic level. The B outputs, which are designed to sink up to 12 mA, include 26 Ω resistors to reduce overshoot and undershoot.
(Top view)
56 OE2B 55 LEA2B 54 2B4 53 GND 52 2B5 51 2B6 50 VCC 49 2B7 48 2B8 47 2B9 46 GND 45 2B10 44 2B11 43 2B12 42 1B12 41 1B11 40 1B10 39 GND 38 1B9 37 1B8 36 1B7 35 VCC 34 1B6 33 1B5 32 GND 31 1B4 30 LEA1B 29 OE1B
HD74ALVCH162260
Electrical Characteristics (Ta = –40 to 85°C)
Item Input voltage
Output voltage
Symbol VIH
VCC (V) *1 Min 2.3 to 2.7 1.7 2.7 to 3.6 2.0
Max — —