UPA2712GR资料

2002

DATA SHEET

Document No.G15980EJ2V0DS00 (2nd edition)Date Published November 2002 NS CP(K)Printed in Japan

The mark ! shows major revised points.

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DESCRIPTION

The µPA2712GR is P-Channel MOS Field Effect Transistor designed for power management applications of notebook computers and Li-ion battery protection circuit.

FEATURES

•Low on-state resistance

R DS(on)1 = 13 m Ω MAX. (V GS = −10 V, I D = −5.0 A)R DS(on)2 = 21 m Ω MAX. (V GS = −4.5 V, I D = −5.0 A)R DS(on)3 = 26 m Ω MAX. (V GS = −4.0 V, I D = −5.0 A)•Low C iss : C iss = 2000 pF TYP.

•Small and surface mount package (Power SOP8)

ORDERING INFORMATION

PART NUMBER

PACKAGE µPA2712GR

Power SOP8

ABSOLUTE MAXIMUM RATINGS (T A = 25°C, All terminals are connected.)

Drain to Source Voltage (V GS = 0 V)V DSS −30V Gate to Source Voltage (V DS = 0 V)V GSS m 20V Drain Current (DC)I D(DC)m 10A Drain Current (pulse)

Note1

I D(pulse)m 40A Total Power Dissipation Note2P T12W Total Power Dissipation Note3

P T22W Channel Temperature T ch 150

°C Storage Temperature

T stg

−55 to +150

°C Single Avalanche Current Note4

I AS −10

A Single Avalanche Energy Note4

E AS

10

mJ

Notes 1.

PW ≤ 10 µs, Duty Cycle ≤ 1%

2.Mounted on ceramic substrate of 1200 mm 2

x 2.2 mm

3. Mounted on a glass epoxy board (1 inch x 1 inch x 0.8 mm), PW = 10 sec

4.

Starting T ch = 25°C, V DD = −15 V, R G = 25 Ω, L = 100 µH, V GS = −20 → 0 V

Remark Strong electric field, when exposed to this device, can cause destruction of the gate oxide and ultimately

degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible,and quickly dissipate it once, when it has occurred.

PACKAGE DRAWING (Unit: mm)

1.8 M A X .

EQUIVALENT CIRCUIT

Body Diode

Data Sheet G15980EJ2V0DS

2

ELECTRICAL CHARACTERISTICS (T A = 25°C, All terminals are connected.)

CHARACTERISTICS

SYMBOL TEST CONDITIONS

MIN.

TYP.

MAX.UNIT

Zero Gate Voltage Drain Current I DSS V DS = −30 V, V GS = 0 V −1

µA Gate Leakage Current I GSS V GS = m 20 V, V DS = 0 V m 100

nA Gate Cut-off Voltage V GS(off)V DS = −10 V, I D = −1 mA −1.0−2.5

V Forward Transfer Admittance | y fs

|V DS = −10 V, I D = −5.0 A 7

15S Drain to Source On-state Resistance

R DS(on)1V GS = −10 V, I D = −5.0 A 1013

m

ΩR DS(on)2V GS = −

4.5 V, I D = −

5.0 A 1521m ΩR DS(on)3

V GS = −4.0 V, I D = −5.0 A 1926

m ΩInput Capacitance C iss V DS = −10 V 2000pF Output Capacitance

C oss

V GS

= 0 V 550

pF Reverse Transfer Capacitance C rss f = 1 MHz

340pF Turn-on Delay Time t d(on)V DD = −15 V, I D = −5.0 A 10ns Rise Time

t r V GS = −10 V 16ns Turn-off Delay Time t d(off)R G = 10 Ω

92ns Fall Time

t f 51ns Total Gate Charge Q G V DD = −24 V 42nC Gate to Source Charge Q GS V GS = −10 V 6nC Gate to Drain Charge Q GD I D = 10 A

12nC Body Diode Forward Voltage V F(S-D)I F = 10 A, V GS = 0 V 0.82V Reverse Recovery Time t rr I F = 10 A, V GS = 0 V 46ns Reverse Recovery Charge

Q rr di/dt = 100 A/µs

33

nC

TEST CIRCUIT 3 GATE CHARGE

V GS = −20 →TEST CIRCUIT 1 AVALANCHE CAPABILITY

L DD

TEST CIRCUIT 2 SWITCHING TIME

L DD

= 1 s Duty Cycle ≤ 1%

τ

µ